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GET /api/patches/1415012/?format=api
{ "id": 1415012, "url": "http://patchwork.ozlabs.org/api/patches/1415012/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-37-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-37-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:58", "name": "[v1,36/50] mips: octeon: Add cvmx-helper-cfg.c", "commit_ref": "b8eaf8c5633f207d6c99dfb1bc293d8275b1d893", "pull_url": null, "state": "accepted", "archived": false, "hash": "de41be3921287b513d34bc0c92027ae0de4c5b5f", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-37-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1415012/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1415012/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=TUpWaEtC;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4Cswnf4lsnz9sTL\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:13:42 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id CA01D827CC;\n\tFri, 11 Dec 2020 17:08:59 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id AAAF3827B7; Fri, 11 Dec 2020 17:08:28 +0100 (CET)", "from mx2.mailbox.org (mx2a.mailbox.org\n [IPv6:2001:67c:2050:104:0:2:25:2])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 868BB826EB\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:29 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org\n [IPv6:2001:67c:2050:105:465:1:1:0])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id 38070A0E5F;\n Fri, 11 Dec 2020 17:06:29 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter05.heinlein-hosting.de (spamfilter05.heinlein-hosting.de\n [80.241.56.123]) (amavisd-new, port 10030)\n with ESMTP id WcQT0fKuBJ8q; Fri, 11 Dec 2020 17:06:24 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702939;\n\tbh=OUq1F73FeoGQFFcBsbY/AJ0AYkzIFHPQ2klwFBcQw30=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=TUpWaEtCX7Qn6XFbzJ92urRNjTpGhcyO62YvQzLRPeO2fIEvwqBKy+XUaB19zUQUU\n\t ucV9FSK+HqIM4DId66xtUgy4Qbyi/zDdn4ESl0bsofDU44qlR3sVsXpnxiOpgy9sO7\n\t uG9HBAw3Z8nbUFgfZgeLddj6ZFhQUr77SQF2t+MF3pU0xmVBKRPu17F+wlwOOssxeR\n\t 2O4r48Z5gykweGR6VSWLYA/UNamgmwYGTzS3d5cwTsQi9nOhU8DzMpsmFc4MAmm5GT\n\t GQi8PnCa5oGwAgdAA0vY3rtp25vQ4Nh/DEqpvR31bqb99FnFfIBbMpxjBWr7khYKyD\n\t 4tDmhfbYFfAQg==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 36/50] mips: octeon: Add cvmx-helper-cfg.c", "Date": "Fri, 11 Dec 2020 17:05:58 +0100", "Message-Id": "<20201211160612.1498780-37-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-0.71 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "21F7F1871", "X-Rspamd-UID": "7c0352", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-helper-cfg.c from 2013 U-Boot. It will be used by the later\nadded drivers to support PCIe and networking on the MIPS Octeon II / III\nplatforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n arch/mips/mach-octeon/cvmx-helper-cfg.c | 1914 +++++++++++++++++++++++\n 1 file changed, 1914 insertions(+)\n create mode 100644 arch/mips/mach-octeon/cvmx-helper-cfg.c", "diff": "diff --git a/arch/mips/mach-octeon/cvmx-helper-cfg.c b/arch/mips/mach-octeon/cvmx-helper-cfg.c\nnew file mode 100644\nindex 0000000000..6b7dd8ac4d\n--- /dev/null\n+++ b/arch/mips/mach-octeon/cvmx-helper-cfg.c\n@@ -0,0 +1,1914 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Helper Functions for the Configuration Framework\n+ */\n+\n+#include <log.h>\n+#include <linux/delay.h>\n+\n+#include <mach/cvmx-regs.h>\n+#include <mach/cvmx-csr.h>\n+#include <mach/cvmx-bootmem.h>\n+#include <mach/octeon-model.h>\n+#include <mach/cvmx-fuse.h>\n+#include <mach/octeon-feature.h>\n+#include <mach/cvmx-qlm.h>\n+#include <mach/octeon_qlm.h>\n+#include <mach/cvmx-pcie.h>\n+#include <mach/cvmx-coremask.h>\n+\n+#include <mach/cvmx-agl-defs.h>\n+#include <mach/cvmx-bgxx-defs.h>\n+#include <mach/cvmx-gmxx-defs.h>\n+#include <mach/cvmx-ipd-defs.h>\n+#include <mach/cvmx-pki-defs.h>\n+\n+#include <mach/cvmx-helper.h>\n+#include <mach/cvmx-helper-board.h>\n+#include <mach/cvmx-helper-fdt.h>\n+#include <mach/cvmx-helper-bgx.h>\n+#include <mach/cvmx-helper-cfg.h>\n+#include <mach/cvmx-helper-util.h>\n+#include <mach/cvmx-helper-pki.h>\n+\n+#include <mach/cvmx-global-resources.h>\n+#include <mach/cvmx-pko-internal-ports-range.h>\n+#include <mach/cvmx-ilk.h>\n+#include <mach/cvmx-pip.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+int cvmx_npi_max_pknds;\n+static bool port_cfg_data_initialized;\n+\n+struct cvmx_cfg_port_param cvmx_cfg_port[CVMX_MAX_NODES][CVMX_HELPER_MAX_IFACE]\n+\t\t\t\t\t[CVMX_HELPER_CFG_MAX_PORT_PER_IFACE];\n+/*\n+ * Indexed by the pko_port number\n+ */\n+static int __cvmx_cfg_pko_highest_queue;\n+struct cvmx_cfg_pko_port_param\n+cvmx_pko_queue_table[CVMX_HELPER_CFG_MAX_PKO_PORT] = {\n+\t[0 ... CVMX_HELPER_CFG_MAX_PKO_PORT - 1] = {\n+\t\tCVMX_HELPER_CFG_INVALID_VALUE,\n+\t\tCVMX_HELPER_CFG_INVALID_VALUE\n+\t}\n+};\n+\n+cvmx_user_static_pko_queue_config_t\n+__cvmx_pko_queue_static_config[CVMX_MAX_NODES];\n+\n+struct cvmx_cfg_pko_port_map\n+cvmx_cfg_pko_port_map[CVMX_HELPER_CFG_MAX_PKO_PORT] = {\n+\t[0 ... CVMX_HELPER_CFG_MAX_PKO_PORT - 1] = {\n+\t\tCVMX_HELPER_CFG_INVALID_VALUE,\n+\t\tCVMX_HELPER_CFG_INVALID_VALUE,\n+\t\tCVMX_HELPER_CFG_INVALID_VALUE\n+\t}\n+};\n+\n+/*\n+ * This array assists translation from ipd_port to pko_port.\n+ * The ``16'' is the rounded value for the 3rd 4-bit value of\n+ * ipd_port, used to differentiate ``interfaces.''\n+ */\n+static struct cvmx_cfg_pko_port_pair\n+ipd2pko_port_cache[16][CVMX_HELPER_CFG_MAX_PORT_PER_IFACE] = {\n+\t[0 ... 15] = {\n+\t\t[0 ... CVMX_HELPER_CFG_MAX_PORT_PER_IFACE - 1] = {\n+\t\t\tCVMX_HELPER_CFG_INVALID_VALUE,\n+\t\t\tCVMX_HELPER_CFG_INVALID_VALUE\n+\t\t}\n+\t}\n+};\n+\n+/*\n+ * Options\n+ *\n+ * Each array-elem's initial value is also the option's default value.\n+ */\n+static u64 cvmx_cfg_opts[CVMX_HELPER_CFG_OPT_MAX] = {\n+\t[0 ... CVMX_HELPER_CFG_OPT_MAX - 1] = 1\n+};\n+\n+/*\n+ * MISC\n+ */\n+\n+static int cvmx_cfg_max_pko_engines; /* # of PKO DMA engines allocated */\n+static int cvmx_pko_queue_alloc(u64 port, int count);\n+static void cvmx_init_port_cfg(void);\n+static const int dbg;\n+\n+int __cvmx_helper_cfg_pknd(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\tint pkind;\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\n+\t/*\n+\t * Only 8 PKNDs are assigned to ILK channels. The channels are wrapped\n+\t * if more than 8 channels are configured, fix the index accordingly.\n+\t */\n+\tif (OCTEON_IS_MODEL(OCTEON_CN78XX)) {\n+\t\tif (cvmx_helper_interface_get_mode(xiface) ==\n+\t\t CVMX_HELPER_INTERFACE_MODE_ILK)\n+\t\t\tindex %= 8;\n+\t}\n+\n+\tpkind = cvmx_cfg_port[xi.node][xi.interface][index].ccpp_pknd;\n+\treturn pkind;\n+}\n+\n+int __cvmx_helper_cfg_bpid(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\n+\t/*\n+\t * Only 8 BIDs are assigned to ILK channels. The channels are wrapped\n+\t * if more than 8 channels are configured, fix the index accordingly.\n+\t */\n+\tif (OCTEON_IS_MODEL(OCTEON_CN78XX)) {\n+\t\tif (cvmx_helper_interface_get_mode(xiface) ==\n+\t\t CVMX_HELPER_INTERFACE_MODE_ILK)\n+\t\t\tindex %= 8;\n+\t}\n+\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].ccpp_bpid;\n+}\n+\n+int __cvmx_helper_cfg_pko_port_base(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].ccpp_pko_port_base;\n+}\n+\n+int __cvmx_helper_cfg_pko_port_num(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].ccpp_pko_num_ports;\n+}\n+\n+int __cvmx_helper_cfg_pko_queue_num(int pko_port)\n+{\n+\treturn cvmx_pko_queue_table[pko_port].ccppp_num_queues;\n+}\n+\n+int __cvmx_helper_cfg_pko_queue_base(int pko_port)\n+{\n+\treturn cvmx_pko_queue_table[pko_port].ccppp_queue_base;\n+}\n+\n+int __cvmx_helper_cfg_pko_max_queue(void)\n+{\n+\treturn __cvmx_cfg_pko_highest_queue;\n+}\n+\n+int __cvmx_helper_cfg_pko_max_engine(void)\n+{\n+\treturn cvmx_cfg_max_pko_engines;\n+}\n+\n+int cvmx_helper_cfg_opt_set(cvmx_helper_cfg_option_t opt, uint64_t val)\n+{\n+\tif (opt >= CVMX_HELPER_CFG_OPT_MAX)\n+\t\treturn -1;\n+\n+\tcvmx_cfg_opts[opt] = val;\n+\n+\treturn 0;\n+}\n+\n+uint64_t cvmx_helper_cfg_opt_get(cvmx_helper_cfg_option_t opt)\n+{\n+\tif (opt >= CVMX_HELPER_CFG_OPT_MAX)\n+\t\treturn (uint64_t)CVMX_HELPER_CFG_INVALID_VALUE;\n+\n+\treturn cvmx_cfg_opts[opt];\n+}\n+\n+/*\n+ * initialize the queue allocation list. the existing static allocation result\n+ * is used as a starting point to ensure backward compatibility.\n+ *\n+ * @return 0 on success\n+ * -1 on failure\n+ */\n+int cvmx_pko_queue_grp_alloc(u64 start, uint64_t end, uint64_t count)\n+{\n+\tu64 port;\n+\tint ret_val;\n+\n+\tfor (port = start; port < end; port++) {\n+\t\tret_val = cvmx_pko_queue_alloc(port, count);\n+\t\tif (ret_val == -1) {\n+\t\t\tprintf(\"ERROR: %sL Failed to allocate queue for port=%d count=%d\\n\",\n+\t\t\t __func__, (int)port, (int)count);\n+\t\t\treturn ret_val;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+int cvmx_pko_queue_init_from_cvmx_config_non_pknd(void)\n+{\n+\tint ret_val = -1;\n+\tu64 count, start, end;\n+\n+\tstart = 0;\n+\tend = __cvmx_pko_queue_static_config[0].non_pknd.pko_ports_per_interface[0];\n+\tcount = __cvmx_pko_queue_static_config[0].non_pknd.pko_queues_per_port_interface[0];\n+\tcvmx_pko_queue_grp_alloc(start, end, count);\n+\n+\tstart = 16;\n+\tend = start + __cvmx_pko_queue_static_config[0].non_pknd.pko_ports_per_interface[1];\n+\tcount = __cvmx_pko_queue_static_config[0].non_pknd.pko_queues_per_port_interface[1];\n+\tret_val = cvmx_pko_queue_grp_alloc(start, end, count);\n+\tif (ret_val != 0)\n+\t\treturn -1;\n+\n+\tif (OCTEON_IS_MODEL(OCTEON_CN70XX)) {\n+\t\t/* Interface 4: AGL, PKO port 24 only, DPI 32-35 */\n+\t\tstart = 24;\n+\t\tend = start + 1;\n+\t\tcount = __cvmx_pko_queue_static_config[0].non_pknd.pko_queues_per_port_interface[4];\n+\t\tret_val = cvmx_pko_queue_grp_alloc(start, end, count);\n+\n+\t\tif (ret_val != 0)\n+\t\t\treturn -1;\n+\t\tend = 32; /* DPI first PKO poty */\n+\t}\n+\n+\tstart = end;\n+\tend = 36;\n+\tcount = __cvmx_pko_queue_static_config[0].non_pknd.pko_queues_per_port_pci;\n+\tcvmx_pko_queue_grp_alloc(start, end, count);\n+\tif (ret_val != 0)\n+\t\treturn -1;\n+\n+\tstart = end;\n+\tend = 40;\n+\tcount = __cvmx_pko_queue_static_config[0].non_pknd.pko_queues_per_port_loop;\n+\tcvmx_pko_queue_grp_alloc(start, end, count);\n+\tif (ret_val != 0)\n+\t\treturn -1;\n+\n+\tstart = end;\n+\tend = 42;\n+\tcount = __cvmx_pko_queue_static_config[0].non_pknd.pko_queues_per_port_srio[0];\n+\tcvmx_pko_queue_grp_alloc(start, end, count);\n+\tif (ret_val != 0)\n+\t\treturn -1;\n+\n+\tstart = end;\n+\tend = 44;\n+\tcount = __cvmx_pko_queue_static_config[0].non_pknd.pko_queues_per_port_srio[1];\n+\tcvmx_pko_queue_grp_alloc(start, end, count);\n+\tif (ret_val != 0)\n+\t\treturn -1;\n+\n+\tstart = end;\n+\tend = 46;\n+\tcount = __cvmx_pko_queue_static_config[0].non_pknd.pko_queues_per_port_srio[2];\n+\tcvmx_pko_queue_grp_alloc(start, end, count);\n+\tif (ret_val != 0)\n+\t\treturn -1;\n+\n+\tstart = end;\n+\tend = 48;\n+\tcount = __cvmx_pko_queue_static_config[0].non_pknd.pko_queues_per_port_srio[3];\n+\tcvmx_pko_queue_grp_alloc(start, end, count);\n+\tif (ret_val != 0)\n+\t\treturn -1;\n+\treturn 0;\n+}\n+\n+int cvmx_helper_pko_queue_config_get(int node, cvmx_user_static_pko_queue_config_t *cfg)\n+{\n+\t*cfg = __cvmx_pko_queue_static_config[node];\n+\treturn 0;\n+}\n+\n+int cvmx_helper_pko_queue_config_set(int node, cvmx_user_static_pko_queue_config_t *cfg)\n+{\n+\t__cvmx_pko_queue_static_config[node] = *cfg;\n+\treturn 0;\n+}\n+\n+static int queue_range_init;\n+\n+int init_cvmx_pko_que_range(void)\n+{\n+\tint rv = 0;\n+\n+\tif (queue_range_init)\n+\t\treturn 0;\n+\tqueue_range_init = 1;\n+\trv = cvmx_create_global_resource_range(CVMX_GR_TAG_PKO_QUEUES,\n+\t\t\t\t\t CVMX_HELPER_CFG_MAX_PKO_QUEUES);\n+\tif (rv != 0)\n+\t\tprintf(\"ERROR: %s: Failed to initialize pko queues range\\n\", __func__);\n+\n+\treturn rv;\n+}\n+\n+/*\n+ * get a block of \"count\" queues for \"port\"\n+ *\n+ * @param port the port for which the queues are requested\n+ * @param count the number of queues requested\n+ *\n+ * @return 0 on success\n+ * -1 on failure\n+ */\n+static int cvmx_pko_queue_alloc(u64 port, int count)\n+{\n+\tint ret_val = -1;\n+\tint highest_queue;\n+\n+\tinit_cvmx_pko_que_range();\n+\n+\tif (cvmx_pko_queue_table[port].ccppp_num_queues == count)\n+\t\treturn cvmx_pko_queue_table[port].ccppp_queue_base;\n+\n+\tif (cvmx_pko_queue_table[port].ccppp_num_queues > 0) {\n+\t\tprintf(\"WARNING: %s port=%d already %d queues\\n\",\n+\t\t __func__, (int)port,\n+\t\t (int)cvmx_pko_queue_table[port].ccppp_num_queues);\n+\t\treturn -1;\n+\t}\n+\n+\tif (port >= CVMX_HELPER_CFG_MAX_PKO_QUEUES) {\n+\t\tprintf(\"ERROR: %s port=%d > %d\\n\", __func__, (int)port,\n+\t\t CVMX_HELPER_CFG_MAX_PKO_QUEUES);\n+\t\treturn -1;\n+\t}\n+\n+\tret_val = cvmx_allocate_global_resource_range(CVMX_GR_TAG_PKO_QUEUES,\n+\t\t\t\t\t\t port, count, 1);\n+\n+\tdebug(\"%s: pko_e_port=%i q_base=%i q_count=%i\\n\",\n+\t __func__, (int)port, ret_val, (int)count);\n+\n+\tif (ret_val == -1)\n+\t\treturn ret_val;\n+\tcvmx_pko_queue_table[port].ccppp_queue_base = ret_val;\n+\tcvmx_pko_queue_table[port].ccppp_num_queues = count;\n+\n+\thighest_queue = ret_val + count - 1;\n+\tif (highest_queue > __cvmx_cfg_pko_highest_queue)\n+\t\t__cvmx_cfg_pko_highest_queue = highest_queue;\n+\treturn 0;\n+}\n+\n+/*\n+ * return the queues for \"port\"\n+ *\n+ * @param port the port for which the queues are returned\n+ *\n+ * @return 0 on success\n+ * -1 on failure\n+ */\n+int cvmx_pko_queue_free(uint64_t port)\n+{\n+\tint ret_val = -1;\n+\n+\tinit_cvmx_pko_que_range();\n+\tif (port >= CVMX_HELPER_CFG_MAX_PKO_QUEUES) {\n+\t\tdebug(\"ERROR: %s port=%d > %d\", __func__, (int)port,\n+\t\t CVMX_HELPER_CFG_MAX_PKO_QUEUES);\n+\t\treturn -1;\n+\t}\n+\n+\tret_val = cvmx_free_global_resource_range_with_base(\n+\t\tCVMX_GR_TAG_PKO_QUEUES, cvmx_pko_queue_table[port].ccppp_queue_base,\n+\t\tcvmx_pko_queue_table[port].ccppp_num_queues);\n+\tif (ret_val != 0)\n+\t\treturn ret_val;\n+\n+\tcvmx_pko_queue_table[port].ccppp_num_queues = 0;\n+\tcvmx_pko_queue_table[port].ccppp_queue_base = CVMX_HELPER_CFG_INVALID_VALUE;\n+\tret_val = 0;\n+\treturn ret_val;\n+}\n+\n+void cvmx_pko_queue_free_all(void)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < CVMX_HELPER_CFG_MAX_PKO_PORT; i++)\n+\t\tif (cvmx_pko_queue_table[i].ccppp_queue_base !=\n+\t\t CVMX_HELPER_CFG_INVALID_VALUE)\n+\t\t\tcvmx_pko_queue_free(i);\n+}\n+\n+void cvmx_pko_queue_show(void)\n+{\n+\tint i;\n+\n+\tcvmx_show_global_resource_range(CVMX_GR_TAG_PKO_QUEUES);\n+\tfor (i = 0; i < CVMX_HELPER_CFG_MAX_PKO_PORT; i++)\n+\t\tif (cvmx_pko_queue_table[i].ccppp_queue_base !=\n+\t\t CVMX_HELPER_CFG_INVALID_VALUE)\n+\t\t\tdebug(\"port=%d que_base=%d que_num=%d\\n\", i,\n+\t\t\t (int)cvmx_pko_queue_table[i].ccppp_queue_base,\n+\t\t\t (int)cvmx_pko_queue_table[i].ccppp_num_queues);\n+}\n+\n+void cvmx_helper_cfg_show_cfg(void)\n+{\n+\tint i, j;\n+\n+\tfor (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++) {\n+\t\tdebug(\"%s: interface%d mode %10s nports%4d\\n\", __func__, i,\n+\t\t cvmx_helper_interface_mode_to_string(cvmx_helper_interface_get_mode(i)),\n+\t\t cvmx_helper_interface_enumerate(i));\n+\n+\t\tfor (j = 0; j < cvmx_helper_interface_enumerate(i); j++) {\n+\t\t\tdebug(\"\\tpknd[%i][%d]%d\", i, j,\n+\t\t\t __cvmx_helper_cfg_pknd(i, j));\n+\t\t\tdebug(\" pko_port_base[%i][%d]%d\", i, j,\n+\t\t\t __cvmx_helper_cfg_pko_port_base(i, j));\n+\t\t\tdebug(\" pko_port_num[%i][%d]%d\\n\", i, j,\n+\t\t\t __cvmx_helper_cfg_pko_port_num(i, j));\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < CVMX_HELPER_CFG_MAX_PKO_PORT; i++) {\n+\t\tif (__cvmx_helper_cfg_pko_queue_base(i) !=\n+\t\t CVMX_HELPER_CFG_INVALID_VALUE) {\n+\t\t\tdebug(\"%s: pko_port%d qbase%d nqueues%d interface%d index%d\\n\",\n+\t\t\t __func__, i, __cvmx_helper_cfg_pko_queue_base(i),\n+\t\t\t __cvmx_helper_cfg_pko_queue_num(i),\n+\t\t\t __cvmx_helper_cfg_pko_port_interface(i),\n+\t\t\t __cvmx_helper_cfg_pko_port_index(i));\n+\t\t}\n+\t}\n+}\n+\n+/*\n+ * initialize cvmx_cfg_pko_port_map\n+ */\n+void cvmx_helper_cfg_init_pko_port_map(void)\n+{\n+\tint i, j, k;\n+\tint pko_eid;\n+\tint pko_port_base, pko_port_max;\n+\tcvmx_helper_interface_mode_t mode;\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\t/*\n+\t * one pko_eid is allocated to each port except for ILK, NPI, and\n+\t * LOOP. Each of the three has one eid.\n+\t */\n+\tpko_eid = 0;\n+\tfor (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++) {\n+\t\tmode = cvmx_helper_interface_get_mode(i);\n+\t\tfor (j = 0; j < cvmx_helper_interface_enumerate(i); j++) {\n+\t\t\tpko_port_base = cvmx_cfg_port[0][i][j].ccpp_pko_port_base;\n+\t\t\tpko_port_max = pko_port_base + cvmx_cfg_port[0][i][j].ccpp_pko_num_ports;\n+\t\t\tif (!octeon_has_feature(OCTEON_FEATURE_PKO3)) {\n+\t\t\t\tcvmx_helper_cfg_assert(pko_port_base !=\n+\t\t\t\t\t\t CVMX_HELPER_CFG_INVALID_VALUE);\n+\t\t\t\tcvmx_helper_cfg_assert(pko_port_max >= pko_port_base);\n+\t\t\t}\n+\t\t\tfor (k = pko_port_base; k < pko_port_max; k++) {\n+\t\t\t\tcvmx_cfg_pko_port_map[k].ccppl_interface = i;\n+\t\t\t\tcvmx_cfg_pko_port_map[k].ccppl_index = j;\n+\t\t\t\tcvmx_cfg_pko_port_map[k].ccppl_eid = pko_eid;\n+\t\t\t}\n+\n+\t\t\tif (!(mode == CVMX_HELPER_INTERFACE_MODE_NPI ||\n+\t\t\t mode == CVMX_HELPER_INTERFACE_MODE_LOOP ||\n+\t\t\t mode == CVMX_HELPER_INTERFACE_MODE_ILK))\n+\t\t\t\tpko_eid++;\n+\t\t}\n+\n+\t\tif (mode == CVMX_HELPER_INTERFACE_MODE_NPI ||\n+\t\t mode == CVMX_HELPER_INTERFACE_MODE_LOOP ||\n+\t\t mode == CVMX_HELPER_INTERFACE_MODE_ILK)\n+\t\t\tpko_eid++;\n+\t}\n+\n+\t/*\n+\t * Legal pko_eids [0, 0x13] should not be exhausted.\n+\t */\n+\tif (!octeon_has_feature(OCTEON_FEATURE_PKO3))\n+\t\tcvmx_helper_cfg_assert(pko_eid <= 0x14);\n+\n+\tcvmx_cfg_max_pko_engines = pko_eid;\n+}\n+\n+void cvmx_helper_cfg_set_jabber_and_frame_max(void)\n+{\n+\tint interface, port;\n+\t/*Set the frame max size and jabber size to 65535. */\n+\tconst unsigned int max_frame = 65535;\n+\n+\t// FIXME: should support node argument for remote node init\n+\tif (octeon_has_feature(OCTEON_FEATURE_BGX)) {\n+\t\tint ipd_port;\n+\t\tint node = cvmx_get_node_num();\n+\n+\t\tfor (interface = 0;\n+\t\t interface < cvmx_helper_get_number_of_interfaces();\n+\t\t interface++) {\n+\t\t\tint xiface = cvmx_helper_node_interface_to_xiface(node, interface);\n+\t\t\tcvmx_helper_interface_mode_t imode = cvmx_helper_interface_get_mode(xiface);\n+\t\t\tint num_ports = cvmx_helper_ports_on_interface(xiface);\n+\n+\t\t\t// FIXME: should be an easier way to determine\n+\t\t\t// that an interface is Ethernet/BGX\n+\t\t\tswitch (imode) {\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_SGMII:\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_XAUI:\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_RXAUI:\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_XLAUI:\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_XFI:\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_10G_KR:\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_40G_KR4:\n+\t\t\t\tfor (port = 0; port < num_ports; port++) {\n+\t\t\t\t\tipd_port = cvmx_helper_get_ipd_port(xiface, port);\n+\t\t\t\t\tcvmx_pki_set_max_frm_len(ipd_port, max_frame);\n+\t\t\t\t\tcvmx_helper_bgx_set_jabber(xiface, port, max_frame);\n+\t\t\t\t}\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\t/*Set the frame max size and jabber size to 65535. */\n+\t\tfor (interface = 0; interface < cvmx_helper_get_number_of_interfaces();\n+\t\t interface++) {\n+\t\t\tint xiface = cvmx_helper_node_interface_to_xiface(cvmx_get_node_num(),\n+\t\t\t\t\t\t\t\t\t interface);\n+\t\t\t/*\n+\t\t\t * Set the frame max size and jabber size to 65535, as the defaults\n+\t\t\t * are too small.\n+\t\t\t */\n+\t\t\tcvmx_helper_interface_mode_t imode = cvmx_helper_interface_get_mode(xiface);\n+\t\t\tint num_ports = cvmx_helper_ports_on_interface(xiface);\n+\n+\t\t\tswitch (imode) {\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_SGMII:\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_QSGMII:\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_XAUI:\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_RXAUI:\n+\t\t\t\tfor (port = 0; port < num_ports; port++)\n+\t\t\t\t\tcsr_wr(CVMX_GMXX_RXX_JABBER(port, interface), 65535);\n+\t\t\t\t/* Set max and min value for frame check */\n+\t\t\t\tcvmx_pip_set_frame_check(interface, -1);\n+\t\t\t\tbreak;\n+\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_RGMII:\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_GMII:\n+\t\t\t\t/* Set max and min value for frame check */\n+\t\t\t\tcvmx_pip_set_frame_check(interface, -1);\n+\t\t\t\tfor (port = 0; port < num_ports; port++) {\n+\t\t\t\t\tcsr_wr(CVMX_GMXX_RXX_FRM_MAX(port, interface), 65535);\n+\t\t\t\t\tcsr_wr(CVMX_GMXX_RXX_JABBER(port, interface), 65535);\n+\t\t\t\t}\n+\t\t\t\tbreak;\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_ILK:\n+\t\t\t\t/* Set max and min value for frame check */\n+\t\t\t\tcvmx_pip_set_frame_check(interface, -1);\n+\t\t\t\tfor (port = 0; port < num_ports; port++) {\n+\t\t\t\t\tint ipd_port = cvmx_helper_get_ipd_port(interface, port);\n+\n+\t\t\t\t\tcvmx_ilk_enable_la_header(ipd_port, 0);\n+\t\t\t\t}\n+\t\t\t\tbreak;\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_SRIO:\n+\t\t\t\t/* Set max and min value for frame check */\n+\t\t\t\tcvmx_pip_set_frame_check(interface, -1);\n+\t\t\t\tbreak;\n+\t\t\tcase CVMX_HELPER_INTERFACE_MODE_AGL:\n+\t\t\t\t/* Set max and min value for frame check */\n+\t\t\t\tcvmx_pip_set_frame_check(interface, -1);\n+\t\t\t\tcsr_wr(CVMX_AGL_GMX_RXX_FRM_MAX(0), 65535);\n+\t\t\t\tcsr_wr(CVMX_AGL_GMX_RXX_JABBER(0), 65535);\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * Enable storing short packets only in the WQE\n+ * unless NO_WPTR is set, which already has the same effect\n+ */\n+void cvmx_helper_cfg_store_short_packets_in_wqe(void)\n+{\n+\tint interface, port;\n+\tcvmx_ipd_ctl_status_t ipd_ctl_status;\n+\tunsigned int dyn_rs = 1;\n+\n+\tif (octeon_has_feature(OCTEON_FEATURE_PKI))\n+\t\treturn;\n+\n+\t/* NO_WPTR combines WQE with 1st MBUF, RS is redundant */\n+\tipd_ctl_status.u64 = csr_rd(CVMX_IPD_CTL_STATUS);\n+\tif (ipd_ctl_status.s.no_wptr) {\n+\t\tdyn_rs = 0;\n+\t\t/* Note: consider also setting 'ignrs' wtn NO_WPTR is set */\n+\t}\n+\n+\tfor (interface = 0; interface < cvmx_helper_get_number_of_interfaces(); interface++) {\n+\t\tint num_ports = cvmx_helper_ports_on_interface(interface);\n+\n+\t\tfor (port = 0; port < num_ports; port++) {\n+\t\t\tcvmx_pip_port_cfg_t port_cfg;\n+\t\t\tint pknd = port;\n+\n+\t\t\tif (octeon_has_feature(OCTEON_FEATURE_PKND))\n+\t\t\t\tpknd = cvmx_helper_get_pknd(interface, port);\n+\t\t\telse\n+\t\t\t\tpknd = cvmx_helper_get_ipd_port(interface, port);\n+\t\t\tport_cfg.u64 = csr_rd(CVMX_PIP_PRT_CFGX(pknd));\n+\t\t\tport_cfg.s.dyn_rs = dyn_rs;\n+\t\t\tcsr_wr(CVMX_PIP_PRT_CFGX(pknd), port_cfg.u64);\n+\t\t}\n+\t}\n+}\n+\n+int __cvmx_helper_cfg_pko_port_interface(int pko_port)\n+{\n+\treturn cvmx_cfg_pko_port_map[pko_port].ccppl_interface;\n+}\n+\n+int __cvmx_helper_cfg_pko_port_index(int pko_port)\n+{\n+\treturn cvmx_cfg_pko_port_map[pko_port].ccppl_index;\n+}\n+\n+int __cvmx_helper_cfg_pko_port_eid(int pko_port)\n+{\n+\treturn cvmx_cfg_pko_port_map[pko_port].ccppl_eid;\n+}\n+\n+#define IPD2PKO_CACHE_Y(ipd_port) (ipd_port) >> 8\n+#define IPD2PKO_CACHE_X(ipd_port) (ipd_port) & 0xff\n+\n+static inline int __cvmx_helper_cfg_ipd2pko_cachex(int ipd_port)\n+{\n+\tint ipd_x = IPD2PKO_CACHE_X(ipd_port);\n+\n+\tif (ipd_port & 0x800)\n+\t\tipd_x = (ipd_x >> 4) & 3;\n+\treturn ipd_x;\n+}\n+\n+/*\n+ * ipd_port to pko_port translation cache\n+ */\n+int __cvmx_helper_cfg_init_ipd2pko_cache(void)\n+{\n+\tint i, j, n;\n+\tint ipd_y, ipd_x, ipd_port;\n+\n+\tfor (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++) {\n+\t\tn = cvmx_helper_interface_enumerate(i);\n+\n+\t\tfor (j = 0; j < n; j++) {\n+\t\t\tipd_port = cvmx_helper_get_ipd_port(i, j);\n+\t\t\tipd_y = IPD2PKO_CACHE_Y(ipd_port);\n+\t\t\tipd_x = __cvmx_helper_cfg_ipd2pko_cachex(ipd_port);\n+\t\t\tipd2pko_port_cache[ipd_y][ipd_x] = (struct cvmx_cfg_pko_port_pair){\n+\t\t\t\t__cvmx_helper_cfg_pko_port_base(i, j),\n+\t\t\t\t__cvmx_helper_cfg_pko_port_num(i, j)\n+\t\t\t};\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int cvmx_helper_cfg_ipd2pko_port_base(int ipd_port)\n+{\n+\tint ipd_y, ipd_x;\n+\n+\t/* Internal PKO ports are not present in PKO3 */\n+\tif (octeon_has_feature(OCTEON_FEATURE_PKI))\n+\t\treturn ipd_port;\n+\n+\tipd_y = IPD2PKO_CACHE_Y(ipd_port);\n+\tipd_x = __cvmx_helper_cfg_ipd2pko_cachex(ipd_port);\n+\n+\treturn ipd2pko_port_cache[ipd_y][ipd_x].ccppp_base_port;\n+}\n+\n+int cvmx_helper_cfg_ipd2pko_port_num(int ipd_port)\n+{\n+\tint ipd_y, ipd_x;\n+\n+\tipd_y = IPD2PKO_CACHE_Y(ipd_port);\n+\tipd_x = __cvmx_helper_cfg_ipd2pko_cachex(ipd_port);\n+\n+\treturn ipd2pko_port_cache[ipd_y][ipd_x].ccppp_nports;\n+}\n+\n+/**\n+ * Return the number of queues to be assigned to this pko_port\n+ *\n+ * @param pko_port\n+ * @return the number of queues for this pko_port\n+ *\n+ */\n+static int cvmx_helper_cfg_dft_nqueues(int pko_port)\n+{\n+\tcvmx_helper_interface_mode_t mode;\n+\tint interface;\n+\tint n;\n+\tint ret;\n+\n+\tinterface = __cvmx_helper_cfg_pko_port_interface(pko_port);\n+\tmode = cvmx_helper_interface_get_mode(interface);\n+\n+\tn = NUM_ELEMENTS(__cvmx_pko_queue_static_config[0].pknd.pko_cfg_iface);\n+\n+\tif (mode == CVMX_HELPER_INTERFACE_MODE_LOOP) {\n+\t\tret = __cvmx_pko_queue_static_config[0].pknd.pko_cfg_loop.queues_per_port;\n+\t} else if (mode == CVMX_HELPER_INTERFACE_MODE_NPI) {\n+\t\tret = __cvmx_pko_queue_static_config[0].pknd.pko_cfg_npi.queues_per_port;\n+\t}\n+\n+\telse if ((interface >= 0) && (interface < n)) {\n+\t\tret = __cvmx_pko_queue_static_config[0].pknd.pko_cfg_iface[interface].queues_per_port;\n+\t} else {\n+\t\t/* Should never be called */\n+\t\tret = 1;\n+\t}\n+\t/* Override for sanity in case of empty static config table */\n+\tif (ret == 0)\n+\t\tret = 1;\n+\treturn ret;\n+}\n+\n+static int cvmx_helper_cfg_init_pko_iports_and_queues_using_static_config(void)\n+{\n+\tint pko_port_base = 0;\n+\tint cvmx_cfg_default_pko_nports = 1;\n+\tint i, j, n, k;\n+\tint rv = 0;\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\n+\t/* When not using config file, each port is assigned one internal pko port*/\n+\tfor (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++) {\n+\t\tn = cvmx_helper_interface_enumerate(i);\n+\t\tfor (j = 0; j < n; j++) {\n+\t\t\tcvmx_cfg_port[0][i][j].ccpp_pko_port_base = pko_port_base;\n+\t\t\tcvmx_cfg_port[0][i][j].ccpp_pko_num_ports = cvmx_cfg_default_pko_nports;\n+\t\t\t/*\n+\t\t\t * Initialize interface early here so that the\n+\t\t\t * cvmx_helper_cfg_dft_nqueues() below\n+\t\t\t * can get the interface number corresponding to the\n+\t\t\t * pko port\n+\t\t\t */\n+\t\t\tfor (k = pko_port_base; k < pko_port_base + cvmx_cfg_default_pko_nports;\n+\t\t\t k++) {\n+\t\t\t\tcvmx_cfg_pko_port_map[k].ccppl_interface = i;\n+\t\t\t}\n+\t\t\tpko_port_base += cvmx_cfg_default_pko_nports;\n+\t\t}\n+\t}\n+\tcvmx_helper_cfg_assert(pko_port_base <= CVMX_HELPER_CFG_MAX_PKO_PORT);\n+\n+\t/* Assigning queues per pko */\n+\tfor (i = 0; i < pko_port_base; i++) {\n+\t\tint base;\n+\n+\t\tn = cvmx_helper_cfg_dft_nqueues(i);\n+\t\tbase = cvmx_pko_queue_alloc(i, n);\n+\t\tif (base == -1) {\n+\t\t\tprintf(\"ERROR: %s: failed to alloc %d queues for pko port=%d\\n\", __func__,\n+\t\t\t n, i);\n+\t\t\trv = -1;\n+\t\t}\n+\t}\n+\treturn rv;\n+}\n+\n+/**\n+ * Returns if port is valid for a given interface\n+ *\n+ * @param xiface interface to check\n+ * @param index port index in the interface\n+ *\n+ * @return status of the port present or not.\n+ */\n+int cvmx_helper_is_port_valid(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].valid;\n+}\n+\n+void cvmx_helper_set_port_valid(int xiface, int index, bool valid)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].valid = valid;\n+}\n+\n+void cvmx_helper_set_mac_phy_mode(int xiface, int index, bool valid)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].sgmii_phy_mode = valid;\n+}\n+\n+bool cvmx_helper_get_mac_phy_mode(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].sgmii_phy_mode;\n+}\n+\n+void cvmx_helper_set_1000x_mode(int xiface, int index, bool valid)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].sgmii_1000x_mode = valid;\n+}\n+\n+bool cvmx_helper_get_1000x_mode(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].sgmii_1000x_mode;\n+}\n+\n+void cvmx_helper_set_agl_rx_clock_delay_bypass(int xiface, int index, bool valid)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].agl_rx_clk_delay_bypass = valid;\n+}\n+\n+bool cvmx_helper_get_agl_rx_clock_delay_bypass(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].agl_rx_clk_delay_bypass;\n+}\n+\n+void cvmx_helper_set_agl_rx_clock_skew(int xiface, int index, uint8_t value)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].agl_rx_clk_skew = value;\n+}\n+\n+uint8_t cvmx_helper_get_agl_rx_clock_skew(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].agl_rx_clk_skew;\n+}\n+\n+void cvmx_helper_set_agl_refclk_sel(int xiface, int index, uint8_t value)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].agl_refclk_sel = value;\n+}\n+\n+uint8_t cvmx_helper_get_agl_refclk_sel(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].agl_refclk_sel;\n+}\n+\n+void cvmx_helper_set_port_force_link_up(int xiface, int index, bool value)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].force_link_up = value;\n+}\n+\n+bool cvmx_helper_get_port_force_link_up(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].force_link_up;\n+}\n+\n+void cvmx_helper_set_port_phy_present(int xiface, int index, bool value)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].phy_present = value;\n+}\n+\n+bool cvmx_helper_get_port_phy_present(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].phy_present;\n+}\n+\n+int __cvmx_helper_init_port_valid(void)\n+{\n+\tint i, j, node;\n+\tbool valid;\n+\tstatic void *fdt_addr;\n+\tint rc;\n+\tstruct cvmx_coremask pcm;\n+\n+\tocteon_get_available_coremask(&pcm);\n+\n+\tif (fdt_addr == 0)\n+\t\tfdt_addr = __cvmx_phys_addr_to_ptr((u64)gd->fdt_blob, 128 * 1024);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tif (octeon_has_feature(OCTEON_FEATURE_BGX)) {\n+\t\trc = __cvmx_helper_parse_bgx_dt(fdt_addr);\n+\t\tif (!rc)\n+\t\t\trc = __cvmx_fdt_parse_vsc7224(fdt_addr);\n+\t\tif (!rc)\n+\t\t\trc = __cvmx_fdt_parse_avsp5410(fdt_addr);\n+\t\tif (!rc && octeon_has_feature(OCTEON_FEATURE_BGX_XCV))\n+\t\t\trc = __cvmx_helper_parse_bgx_rgmii_dt(fdt_addr);\n+\n+\t\t/* Some ports are not in sequence, the device tree does not\n+\t\t * clear them.\n+\t\t *\n+\t\t * Also clear any ports that are not defined in the device tree.\n+\t\t * Apply this to each node.\n+\t\t */\n+\t\tfor (node = 0; node < CVMX_MAX_NODES; node++) {\n+\t\t\tif (!cvmx_coremask_get64_node(&pcm, node))\n+\t\t\t\tcontinue;\n+\t\t\tfor (i = 0; i < CVMX_HELPER_MAX_GMX; i++) {\n+\t\t\t\tint j;\n+\t\t\t\tint xiface = cvmx_helper_node_interface_to_xiface(node, i);\n+\n+\t\t\t\tfor (j = 0; j < cvmx_helper_interface_enumerate(i); j++) {\n+\t\t\t\t\tcvmx_bgxx_cmrx_config_t cmr_config;\n+\n+\t\t\t\t\tcmr_config.u64 =\n+\t\t\t\t\t\tcsr_rd_node(node, CVMX_BGXX_CMRX_CONFIG(j, i));\n+\t\t\t\t\tif ((cmr_config.s.lane_to_sds == 0xe4 &&\n+\t\t\t\t\t cmr_config.s.lmac_type != 4 &&\n+\t\t\t\t\t cmr_config.s.lmac_type != 1 &&\n+\t\t\t\t\t cmr_config.s.lmac_type != 5) ||\n+\t\t\t\t\t ((cvmx_helper_get_port_fdt_node_offset(xiface, j) ==\n+\t\t\t\t\t CVMX_HELPER_CFG_INVALID_VALUE)))\n+\t\t\t\t\t\tcvmx_helper_set_port_valid(xiface, j, false);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\treturn rc;\n+\t}\n+\n+\t/* TODO: Update this to behave more like 78XX */\n+\tfor (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++) {\n+\t\tint n = cvmx_helper_interface_enumerate(i);\n+\n+\t\tfor (j = 0; j < n; j++) {\n+\t\t\tint ipd_port = cvmx_helper_get_ipd_port(i, j);\n+\n+\t\t\tvalid = (__cvmx_helper_board_get_port_from_dt(fdt_addr, ipd_port) == 1);\n+\t\t\tcvmx_helper_set_port_valid(i, j, valid);\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+typedef int (*cvmx_import_config_t)(void);\n+cvmx_import_config_t cvmx_import_app_config;\n+\n+int __cvmx_helper_init_port_config_data_local(void)\n+{\n+\tint rv = 0;\n+\tint dbg = 0;\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\n+\tif (octeon_has_feature(OCTEON_FEATURE_PKND)) {\n+\t\tif (cvmx_import_app_config) {\n+\t\t\trv = (*cvmx_import_app_config)();\n+\t\t\tif (rv != 0) {\n+\t\t\t\tdebug(\"failed to import config\\n\");\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\n+\t\tcvmx_helper_cfg_init_pko_port_map();\n+\t\t__cvmx_helper_cfg_init_ipd2pko_cache();\n+\t} else {\n+\t\tif (cvmx_import_app_config) {\n+\t\t\trv = (*cvmx_import_app_config)();\n+\t\t\tif (rv != 0) {\n+\t\t\t\tdebug(\"failed to import config\\n\");\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tif (dbg) {\n+\t\tcvmx_helper_cfg_show_cfg();\n+\t\tcvmx_pko_queue_show();\n+\t}\n+\treturn rv;\n+}\n+\n+/*\n+ * This call is made from Linux octeon_ethernet driver\n+ * to setup the PKO with a specific queue count and\n+ * internal port count configuration.\n+ */\n+int cvmx_pko_alloc_iport_and_queues(int interface, int port, int port_cnt, int queue_cnt)\n+{\n+\tint rv, p, port_start, cnt;\n+\n+\tif (dbg)\n+\t\tdebug(\"%s: intf %d/%d pcnt %d qcnt %d\\n\", __func__, interface, port, port_cnt,\n+\t\t queue_cnt);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tif (octeon_has_feature(OCTEON_FEATURE_PKND)) {\n+\t\trv = cvmx_pko_internal_ports_alloc(interface, port, port_cnt);\n+\t\tif (rv < 0) {\n+\t\t\tprintf(\"ERROR: %s: failed to allocate internal ports forinterface=%d port=%d cnt=%d\\n\",\n+\t\t\t __func__, interface, port, port_cnt);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tport_start = __cvmx_helper_cfg_pko_port_base(interface, port);\n+\t\tcnt = __cvmx_helper_cfg_pko_port_num(interface, port);\n+\t} else {\n+\t\tport_start = cvmx_helper_get_ipd_port(interface, port);\n+\t\tcnt = 1;\n+\t}\n+\n+\tfor (p = port_start; p < port_start + cnt; p++) {\n+\t\trv = cvmx_pko_queue_alloc(p, queue_cnt);\n+\t\tif (rv < 0) {\n+\t\t\tprintf(\"ERROR: %s: failed to allocate queues for port=%d cnt=%d\\n\",\n+\t\t\t __func__, p, queue_cnt);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+static void cvmx_init_port_cfg(void)\n+{\n+\tint node, i, j;\n+\n+\tif (port_cfg_data_initialized)\n+\t\treturn;\n+\n+\tfor (node = 0; node < CVMX_MAX_NODES; node++) {\n+\t\tfor (i = 0; i < CVMX_HELPER_MAX_IFACE; i++) {\n+\t\t\tfor (j = 0; j < CVMX_HELPER_CFG_MAX_PORT_PER_IFACE; j++) {\n+\t\t\t\tstruct cvmx_cfg_port_param *pcfg;\n+\t\t\t\tstruct cvmx_srio_port_param *sr;\n+\n+\t\t\t\tpcfg = &cvmx_cfg_port[node][i][j];\n+\t\t\t\tmemset(pcfg, 0, sizeof(*pcfg));\n+\n+\t\t\t\tpcfg->port_fdt_node = CVMX_HELPER_CFG_INVALID_VALUE;\n+\t\t\t\tpcfg->phy_fdt_node = CVMX_HELPER_CFG_INVALID_VALUE;\n+\t\t\t\tpcfg->phy_info = NULL;\n+\t\t\t\tpcfg->ccpp_pknd = CVMX_HELPER_CFG_INVALID_VALUE;\n+\t\t\t\tpcfg->ccpp_bpid = CVMX_HELPER_CFG_INVALID_VALUE;\n+\t\t\t\tpcfg->ccpp_pko_port_base = CVMX_HELPER_CFG_INVALID_VALUE;\n+\t\t\t\tpcfg->ccpp_pko_num_ports = CVMX_HELPER_CFG_INVALID_VALUE;\n+\t\t\t\tpcfg->agl_rx_clk_skew = 0;\n+\t\t\t\tpcfg->valid = true;\n+\t\t\t\tpcfg->sgmii_phy_mode = false;\n+\t\t\t\tpcfg->sgmii_1000x_mode = false;\n+\t\t\t\tpcfg->agl_rx_clk_delay_bypass = false;\n+\t\t\t\tpcfg->force_link_up = false;\n+\t\t\t\tpcfg->disable_an = false;\n+\t\t\t\tpcfg->link_down_pwr_dn = false;\n+\t\t\t\tpcfg->phy_present = false;\n+\t\t\t\tpcfg->tx_clk_delay_bypass = false;\n+\t\t\t\tpcfg->rgmii_tx_clk_delay = 0;\n+\t\t\t\tpcfg->enable_fec = false;\n+\t\t\t\tsr = &pcfg->srio_short;\n+\t\t\t\tsr->srio_rx_ctle_agc_override = false;\n+\t\t\t\tsr->srio_rx_ctle_zero = 0x6;\n+\t\t\t\tsr->srio_rx_agc_pre_ctle = 0x5;\n+\t\t\t\tsr->srio_rx_agc_post_ctle = 0x4;\n+\t\t\t\tsr->srio_tx_swing_override = false;\n+\t\t\t\tsr->srio_tx_swing = 0x7;\n+\t\t\t\tsr->srio_tx_premptap_override = false;\n+\t\t\t\tsr->srio_tx_premptap_pre = 0;\n+\t\t\t\tsr->srio_tx_premptap_post = 0xF;\n+\t\t\t\tsr->srio_tx_gain_override = false;\n+\t\t\t\tsr->srio_tx_gain = 0x3;\n+\t\t\t\tsr->srio_tx_vboost_override = 0;\n+\t\t\t\tsr->srio_tx_vboost = true;\n+\t\t\t\tsr = &pcfg->srio_long;\n+\t\t\t\tsr->srio_rx_ctle_agc_override = false;\n+\t\t\t\tsr->srio_rx_ctle_zero = 0x6;\n+\t\t\t\tsr->srio_rx_agc_pre_ctle = 0x5;\n+\t\t\t\tsr->srio_rx_agc_post_ctle = 0x4;\n+\t\t\t\tsr->srio_tx_swing_override = false;\n+\t\t\t\tsr->srio_tx_swing = 0x7;\n+\t\t\t\tsr->srio_tx_premptap_override = false;\n+\t\t\t\tsr->srio_tx_premptap_pre = 0;\n+\t\t\t\tsr->srio_tx_premptap_post = 0xF;\n+\t\t\t\tsr->srio_tx_gain_override = false;\n+\t\t\t\tsr->srio_tx_gain = 0x3;\n+\t\t\t\tsr->srio_tx_vboost_override = 0;\n+\t\t\t\tsr->srio_tx_vboost = true;\n+\t\t\t\tpcfg->agl_refclk_sel = 0;\n+\t\t\t\tpcfg->sfp_of_offset = -1;\n+\t\t\t\tpcfg->vsc7224_chan = NULL;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tport_cfg_data_initialized = true;\n+}\n+\n+int __cvmx_helper_init_port_config_data(int node)\n+{\n+\tint rv = 0;\n+\tint i, j, n;\n+\tint num_interfaces, interface;\n+\tint pknd = 0, bpid = 0;\n+\tconst int use_static_config = 1;\n+\n+\tif (dbg)\n+\t\tprintf(\"%s:\\n\", __func__);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\n+\tif (octeon_has_feature(OCTEON_FEATURE_CN78XX_WQE)) {\n+\t\t/* PKO3: only needs BPID, PKND to be setup,\n+\t\t * while the rest of PKO3 init is done in cvmx-helper-pko3.c\n+\t\t */\n+\t\tpknd = 0;\n+\t\tbpid = 0;\n+\t\tfor (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++) {\n+\t\t\tint xiface = cvmx_helper_node_interface_to_xiface(node, i);\n+\n+\t\t\tn = cvmx_helper_interface_enumerate(xiface);\n+\t\t\t/*\n+\t\t\t * Assign 8 pknds to ILK interface, these pknds will be\n+\t\t\t * distributed among the channels configured\n+\t\t\t */\n+\t\t\tif (cvmx_helper_interface_get_mode(xiface) ==\n+\t\t\t CVMX_HELPER_INTERFACE_MODE_ILK) {\n+\t\t\t\tif (n > 8)\n+\t\t\t\t\tn = 8;\n+\t\t\t}\n+\t\t\tif (cvmx_helper_interface_get_mode(xiface) !=\n+\t\t\t CVMX_HELPER_INTERFACE_MODE_NPI) {\n+\t\t\t\tfor (j = 0; j < n; j++) {\n+\t\t\t\t\tstruct cvmx_cfg_port_param *pcfg;\n+\n+\t\t\t\t\tpcfg = &cvmx_cfg_port[node][i][j];\n+\t\t\t\t\tpcfg->ccpp_pknd = pknd++;\n+\t\t\t\t\tpcfg->ccpp_bpid = bpid++;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tfor (j = 0; j < n; j++) {\n+\t\t\t\t\tif (j == n / cvmx_npi_max_pknds) {\n+\t\t\t\t\t\tpknd++;\n+\t\t\t\t\t\tbpid++;\n+\t\t\t\t\t}\n+\t\t\t\t\tcvmx_cfg_port[node][i][j].ccpp_pknd = pknd;\n+\t\t\t\t\tcvmx_cfg_port[node][i][j].ccpp_bpid = bpid;\n+\t\t\t\t}\n+\t\t\t\tpknd++;\n+\t\t\t\tbpid++;\n+\t\t\t}\n+\t\t} /* for i=0 */\n+\t\tcvmx_helper_cfg_assert(pknd <= CVMX_HELPER_CFG_MAX_PIP_PKND);\n+\t\tcvmx_helper_cfg_assert(bpid <= CVMX_HELPER_CFG_MAX_PIP_BPID);\n+\t} else if (octeon_has_feature(OCTEON_FEATURE_PKND)) {\n+\t\tif (use_static_config)\n+\t\t\tcvmx_helper_cfg_init_pko_iports_and_queues_using_static_config();\n+\n+\t\t/* Initialize pknd and bpid */\n+\t\tfor (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++) {\n+\t\t\tn = cvmx_helper_interface_enumerate(i);\n+\t\t\tfor (j = 0; j < n; j++) {\n+\t\t\t\tcvmx_cfg_port[0][i][j].ccpp_pknd = pknd++;\n+\t\t\t\tcvmx_cfg_port[0][i][j].ccpp_bpid = bpid++;\n+\t\t\t}\n+\t\t}\n+\t\tcvmx_helper_cfg_assert(pknd <= CVMX_HELPER_CFG_MAX_PIP_PKND);\n+\t\tcvmx_helper_cfg_assert(bpid <= CVMX_HELPER_CFG_MAX_PIP_BPID);\n+\t} else {\n+\t\tif (use_static_config)\n+\t\t\tcvmx_pko_queue_init_from_cvmx_config_non_pknd();\n+\t}\n+\n+\t/* Remainder not used for PKO3 */\n+\tif (octeon_has_feature(OCTEON_FEATURE_CN78XX_WQE))\n+\t\treturn 0;\n+\n+\t/* init ports, queues which are not initialized */\n+\tnum_interfaces = cvmx_helper_get_number_of_interfaces();\n+\tfor (interface = 0; interface < num_interfaces; interface++) {\n+\t\tint num_ports = __cvmx_helper_early_ports_on_interface(interface);\n+\t\tint port, port_base, queue;\n+\n+\t\tfor (port = 0; port < num_ports; port++) {\n+\t\t\tbool init_req = false;\n+\n+\t\t\tif (octeon_has_feature(OCTEON_FEATURE_PKND)) {\n+\t\t\t\tport_base = __cvmx_helper_cfg_pko_port_base(interface, port);\n+\t\t\t\tif (port_base == CVMX_HELPER_CFG_INVALID_VALUE)\n+\t\t\t\t\tinit_req = true;\n+\t\t\t} else {\n+\t\t\t\tport_base = cvmx_helper_get_ipd_port(interface, port);\n+\t\t\t\tqueue = __cvmx_helper_cfg_pko_queue_base(port_base);\n+\t\t\t\tif (queue == CVMX_HELPER_CFG_INVALID_VALUE)\n+\t\t\t\t\tinit_req = true;\n+\t\t\t}\n+\n+\t\t\tif (init_req) {\n+\t\t\t\trv = cvmx_pko_alloc_iport_and_queues(interface, port, 1, 1);\n+\t\t\t\tif (rv < 0) {\n+\t\t\t\t\tdebug(\"cvm_pko_alloc_iport_and_queues failed.\\n\");\n+\t\t\t\t\treturn rv;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (octeon_has_feature(OCTEON_FEATURE_PKND)) {\n+\t\tcvmx_helper_cfg_init_pko_port_map();\n+\t\t__cvmx_helper_cfg_init_ipd2pko_cache();\n+\t}\n+\n+\tif (dbg) {\n+\t\tcvmx_helper_cfg_show_cfg();\n+\t\tcvmx_pko_queue_show();\n+\t}\n+\treturn rv;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Store the FDT node offset in the device tree of a port\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @param node_offset\tnode offset to store\n+ */\n+void cvmx_helper_set_port_fdt_node_offset(int xiface, int index, int node_offset)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].port_fdt_node = node_offset;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Return the FDT node offset in the device tree of a port\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @return\t\tnode offset of port or -1 if invalid\n+ */\n+int cvmx_helper_get_port_fdt_node_offset(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].port_fdt_node;\n+}\n+\n+/**\n+ * Search for a port based on its FDT node offset\n+ *\n+ * @param\tof_offset\tNode offset of port to search for\n+ * @param[out]\txiface\t\txinterface of match\n+ * @param[out]\tindex\t\tport index of match\n+ *\n+ * @return\t0 if found, -1 if not found\n+ */\n+int cvmx_helper_cfg_get_xiface_index_by_fdt_node_offset(int of_offset, int *xiface, int *index)\n+{\n+\tint iface;\n+\tint i;\n+\tint node;\n+\tstruct cvmx_cfg_port_param *pcfg = NULL;\n+\t*xiface = -1;\n+\t*index = -1;\n+\n+\tfor (node = 0; node < CVMX_MAX_NODES; node++) {\n+\t\tfor (iface = 0; iface < CVMX_HELPER_MAX_IFACE; iface++) {\n+\t\t\tfor (i = 0; i < CVMX_HELPER_CFG_MAX_PORT_PER_IFACE; i++) {\n+\t\t\t\tpcfg = &cvmx_cfg_port[node][iface][i];\n+\t\t\t\tif (pcfg->valid && pcfg->port_fdt_node == of_offset) {\n+\t\t\t\t\t*xiface = cvmx_helper_node_interface_to_xiface(node, iface);\n+\t\t\t\t\t*index = i;\n+\t\t\t\t\treturn 0;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn -1;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Store the FDT node offset in the device tree of a phy\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @param node_offset\tnode offset to store\n+ */\n+void cvmx_helper_set_phy_fdt_node_offset(int xiface, int index, int node_offset)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].phy_fdt_node = node_offset;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Return the FDT node offset in the device tree of a phy\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @return\t\tnode offset of phy or -1 if invalid\n+ */\n+int cvmx_helper_get_phy_fdt_node_offset(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].phy_fdt_node;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Override default autonegotiation for a port\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @param enable\ttrue to enable autonegotiation, false to force full\n+ *\t\t\tduplex, full speed.\n+ */\n+void cvmx_helper_set_port_autonegotiation(int xiface, int index, bool enable)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].disable_an = !enable;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Returns if autonegotiation is enabled or not.\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ *\n+ * @return 0 if autonegotiation is disabled, 1 if enabled.\n+ */\n+bool cvmx_helper_get_port_autonegotiation(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn !cvmx_cfg_port[xi.node][xi.interface][index].disable_an;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Override default forward error correction for a port\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @param enable\ttrue to enable fec, false to disable it\n+ */\n+void cvmx_helper_set_port_fec(int xiface, int index, bool enable)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].enable_fec = enable;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Returns if forward error correction is enabled or not.\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ *\n+ * @return false if fec is disabled, true if enabled.\n+ */\n+bool cvmx_helper_get_port_fec(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].enable_fec;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Configure the SRIO RX interface AGC settings for host mode\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tlane\n+ * @param long_run\ttrue for long run, false for short run\n+ * @param agc_override\ttrue to put AGC in manual mode\n+ * @param ctle_zero\tRX equalizer peaking control (default 0x6)\n+ * @param agc_pre_ctle\tAGC pre-CTLE gain (default 0x5)\n+ * @param agc_post_ctle\tAGC post-CTLE gain (default 0x4)\n+ *\n+ * NOTE: This must be called before SRIO is initialized to take effect\n+ */\n+void cvmx_helper_set_srio_rx(int xiface, int index, bool long_run, bool ctle_zero_override,\n+\t\t\t u8 ctle_zero, bool agc_override, uint8_t agc_pre_ctle,\n+\t\t\t uint8_t agc_post_ctle)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\tstruct cvmx_cfg_port_param *pcfg = &cvmx_cfg_port[xi.node][xi.interface][index];\n+\tstruct cvmx_srio_port_param *sr = long_run ? &pcfg->srio_long : &pcfg->srio_short;\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tsr->srio_rx_ctle_zero_override = ctle_zero_override;\n+\tsr->srio_rx_ctle_zero = ctle_zero;\n+\tsr->srio_rx_ctle_agc_override = agc_override;\n+\tsr->srio_rx_agc_pre_ctle = agc_pre_ctle;\n+\tsr->srio_rx_agc_post_ctle = agc_post_ctle;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Get the SRIO RX interface AGC settings for host mode\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tlane\n+ * @param long_run\ttrue for long run, false for short run\n+ * @param[out] agc_override\ttrue to put AGC in manual mode\n+ * @param[out] ctle_zero\tRX equalizer peaking control (default 0x6)\n+ * @param[out] agc_pre_ctle\tAGC pre-CTLE gain (default 0x5)\n+ * @param[out] agc_post_ctle\tAGC post-CTLE gain (default 0x4)\n+ */\n+void cvmx_helper_get_srio_rx(int xiface, int index, bool long_run, bool *ctle_zero_override,\n+\t\t\t u8 *ctle_zero, bool *agc_override, uint8_t *agc_pre_ctle,\n+\t\t\t uint8_t *agc_post_ctle)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\tstruct cvmx_cfg_port_param *pcfg = &cvmx_cfg_port[xi.node][xi.interface][index];\n+\tstruct cvmx_srio_port_param *sr = long_run ? &pcfg->srio_long : &pcfg->srio_short;\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tif (ctle_zero_override)\n+\t\t*ctle_zero_override = sr->srio_rx_ctle_zero_override;\n+\tif (ctle_zero)\n+\t\t*ctle_zero = sr->srio_rx_ctle_zero;\n+\tif (agc_override)\n+\t\t*agc_override = sr->srio_rx_ctle_agc_override;\n+\tif (agc_pre_ctle)\n+\t\t*agc_pre_ctle = sr->srio_rx_agc_pre_ctle;\n+\tif (agc_post_ctle)\n+\t\t*agc_post_ctle = sr->srio_rx_agc_post_ctle;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Configure the SRIO TX interface for host mode\n+ *\n+ * @param xiface\t\tnode and interface\n+ * @param index\t\t\tlane\n+ * @param long_run\t\ttrue for long run, false for short run\n+ * @param tx_swing\t\ttx swing value to use (default 0x7), -1 to not\n+ *\t\t\t\toverride.\n+ * @param tx_gain\t\tPCS SDS TX gain (default 0x3), -1 to not\n+ *\t\t\t\toverride\n+ * @param tx_premptap_override\ttrue to override preemphasis control\n+ * @param tx_premptap_pre\tpreemphasis pre tap value (default 0x0)\n+ * @param tx_premptap_post\tpreemphasis post tap value (default 0xF)\n+ * @param tx_vboost\t\tvboost enable (1 = enable, -1 = don't override)\n+ *\t\t\t\thardware default is 1.\n+ *\n+ * NOTE: This must be called before SRIO is initialized to take effect\n+ */\n+void cvmx_helper_set_srio_tx(int xiface, int index, bool long_run, int tx_swing, int tx_gain,\n+\t\t\t bool tx_premptap_override, uint8_t tx_premptap_pre,\n+\t\t\t u8 tx_premptap_post, int tx_vboost)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\tstruct cvmx_cfg_port_param *pcfg = &cvmx_cfg_port[xi.node][xi.interface][index];\n+\tstruct cvmx_srio_port_param *sr = long_run ? &pcfg->srio_long : &pcfg->srio_short;\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\n+\tsr->srio_tx_swing_override = (tx_swing != -1);\n+\tsr->srio_tx_swing = tx_swing != -1 ? tx_swing : 0x7;\n+\tsr->srio_tx_gain_override = (tx_gain != -1);\n+\tsr->srio_tx_gain = tx_gain != -1 ? tx_gain : 0x3;\n+\tsr->srio_tx_premptap_override = tx_premptap_override;\n+\tsr->srio_tx_premptap_pre = tx_premptap_override ? tx_premptap_pre : 0;\n+\tsr->srio_tx_premptap_post = tx_premptap_override ? tx_premptap_post : 0xF;\n+\tsr->srio_tx_vboost_override = tx_vboost != -1;\n+\tsr->srio_tx_vboost = (tx_vboost != -1) ? tx_vboost : 1;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Get the SRIO TX interface settings for host mode\n+ *\n+ * @param xiface\t\t\tnode and interface\n+ * @param index\t\t\t\tlane\n+ * @param long_run\t\t\ttrue for long run, false for short run\n+ * @param[out] tx_swing_override\ttrue to override pcs_sds_txX_swing\n+ * @param[out] tx_swing\t\t\ttx swing value to use (default 0x7)\n+ * @param[out] tx_gain_override\t\ttrue to override default gain\n+ * @param[out] tx_gain\t\t\tPCS SDS TX gain (default 0x3)\n+ * @param[out] tx_premptap_override\ttrue to override preemphasis control\n+ * @param[out] tx_premptap_pre\t\tpreemphasis pre tap value (default 0x0)\n+ * @param[out] tx_premptap_post\t\tpreemphasis post tap value (default 0xF)\n+ * @param[out] tx_vboost_override\toverride vboost setting\n+ * @param[out] tx_vboost\t\tvboost enable (default true)\n+ */\n+void cvmx_helper_get_srio_tx(int xiface, int index, bool long_run, bool *tx_swing_override,\n+\t\t\t u8 *tx_swing, bool *tx_gain_override, uint8_t *tx_gain,\n+\t\t\t bool *tx_premptap_override, uint8_t *tx_premptap_pre,\n+\t\t\t u8 *tx_premptap_post, bool *tx_vboost_override, bool *tx_vboost)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\tstruct cvmx_cfg_port_param *pcfg = &cvmx_cfg_port[xi.node][xi.interface][index];\n+\tstruct cvmx_srio_port_param *sr = long_run ? &pcfg->srio_long : &pcfg->srio_short;\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\n+\tif (tx_swing_override)\n+\t\t*tx_swing_override = sr->srio_tx_swing_override;\n+\tif (tx_swing)\n+\t\t*tx_swing = sr->srio_tx_swing;\n+\tif (tx_gain_override)\n+\t\t*tx_gain_override = sr->srio_tx_gain_override;\n+\tif (tx_gain)\n+\t\t*tx_gain = sr->srio_tx_gain;\n+\tif (tx_premptap_override)\n+\t\t*tx_premptap_override = sr->srio_tx_premptap_override;\n+\tif (tx_premptap_pre)\n+\t\t*tx_premptap_pre = sr->srio_tx_premptap_pre;\n+\tif (tx_premptap_post)\n+\t\t*tx_premptap_post = sr->srio_tx_premptap_post;\n+\tif (tx_vboost_override)\n+\t\t*tx_vboost_override = sr->srio_tx_vboost_override;\n+\tif (tx_vboost)\n+\t\t*tx_vboost = sr->srio_tx_vboost;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Sets the PHY info data structure\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @param[in] phy_info\tphy information data structure pointer\n+ */\n+void cvmx_helper_set_port_phy_info(int xiface, int index, struct cvmx_phy_info *phy_info)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].phy_info = phy_info;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Returns the PHY information data structure for a port\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ *\n+ * @return pointer to PHY information data structure or NULL if not set\n+ */\n+struct cvmx_phy_info *cvmx_helper_get_port_phy_info(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].phy_info;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Returns a pointer to the PHY LED configuration (if local GPIOs drive them)\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tportindex\n+ *\n+ * @return pointer to the PHY LED information data structure or NULL if not\n+ *\t present\n+ */\n+struct cvmx_phy_gpio_leds *cvmx_helper_get_port_phy_leds(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].gpio_leds;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Sets a pointer to the PHY LED configuration (if local GPIOs drive them)\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tportindex\n+ * @param leds\t\tpointer to led data structure\n+ */\n+void cvmx_helper_set_port_phy_leds(int xiface, int index, struct cvmx_phy_gpio_leds *leds)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].gpio_leds = leds;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Disables RGMII TX clock bypass and sets delay value\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tportindex\n+ * @param bypass\tSet true to enable the clock bypass and false\n+ *\t\t\tto sync clock and data synchronously.\n+ *\t\t\tDefault is false.\n+ * @param clk_delay\tDelay value to skew TXC from TXD\n+ */\n+void cvmx_helper_cfg_set_rgmii_tx_clk_delay(int xiface, int index, bool bypass, int clk_delay)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].tx_clk_delay_bypass = bypass;\n+\tcvmx_cfg_port[xi.node][xi.interface][index].rgmii_tx_clk_delay = clk_delay;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Gets RGMII TX clock bypass and delay value\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tportindex\n+ * @param bypass\tSet true to enable the clock bypass and false\n+ *\t\t\tto sync clock and data synchronously.\n+ *\t\t\tDefault is false.\n+ * @param clk_delay\tDelay value to skew TXC from TXD, default is 0.\n+ */\n+void cvmx_helper_cfg_get_rgmii_tx_clk_delay(int xiface, int index, bool *bypass, int *clk_delay)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\t*bypass = cvmx_cfg_port[xi.node][xi.interface][index].tx_clk_delay_bypass;\n+\n+\t*clk_delay = cvmx_cfg_port[xi.node][xi.interface][index].rgmii_tx_clk_delay;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Retrieve the SFP node offset in the device tree\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ *\n+ * @return offset in device tree or -1 if error or not defined.\n+ */\n+int cvmx_helper_cfg_get_sfp_fdt_offset(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].sfp_of_offset;\n+}\n+\n+/**\n+ * @INTERNAL\n+ * Sets the SFP node offset\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ * @param sfp_of_offset\tOffset of SFP node in device tree\n+ */\n+void cvmx_helper_cfg_set_sfp_fdt_offset(int xiface, int index, int sfp_of_offset)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].sfp_of_offset = sfp_of_offset;\n+}\n+\n+/**\n+ * Get data structure defining the Microsemi VSC7224 channel info\n+ * or NULL if not present\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ *\n+ * @return pointer to vsc7224 data structure or NULL if not present\n+ */\n+struct cvmx_vsc7224_chan *cvmx_helper_cfg_get_vsc7224_chan_info(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].vsc7224_chan;\n+}\n+\n+/**\n+ * Sets the Microsemi VSC7224 channel info data structure\n+ *\n+ * @param\txiface\tnode and interface\n+ * @param\tindex\tport index\n+ * @param[in]\tvsc7224_info\tMicrosemi VSC7224 data structure\n+ */\n+void cvmx_helper_cfg_set_vsc7224_chan_info(int xiface, int index,\n+\t\t\t\t\t struct cvmx_vsc7224_chan *vsc7224_chan_info)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].vsc7224_chan = vsc7224_chan_info;\n+}\n+\n+/**\n+ * Get data structure defining the Avago AVSP5410 phy info\n+ * or NULL if not present\n+ *\n+ * @param xiface\tnode and interface\n+ * @param index\t\tport index\n+ *\n+ * @return pointer to avsp5410 data structure or NULL if not present\n+ */\n+struct cvmx_avsp5410 *cvmx_helper_cfg_get_avsp5410_info(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].avsp5410;\n+}\n+\n+/**\n+ * Sets the Avago AVSP5410 phy info data structure\n+ *\n+ * @param\txiface\tnode and interface\n+ * @param\tindex\tport index\n+ * @param[in]\tavsp5410_info\tAvago AVSP5410 data structure\n+ */\n+void cvmx_helper_cfg_set_avsp5410_info(int xiface, int index, struct cvmx_avsp5410 *avsp5410_info)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].avsp5410 = avsp5410_info;\n+}\n+\n+/**\n+ * Gets the SFP data associated with a port\n+ *\n+ * @param\txiface\tnode and interface\n+ * @param\tindex\tport index\n+ *\n+ * @return\tpointer to SFP data structure or NULL if none\n+ */\n+struct cvmx_fdt_sfp_info *cvmx_helper_cfg_get_sfp_info(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].sfp_info;\n+}\n+\n+/**\n+ * Sets the SFP data associated with a port\n+ *\n+ * @param\txiface\t\tnode and interface\n+ * @param\tindex\t\tport index\n+ * @param[in]\tsfp_info\tport SFP data or NULL for none\n+ */\n+void cvmx_helper_cfg_set_sfp_info(int xiface, int index, struct cvmx_fdt_sfp_info *sfp_info)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].sfp_info = sfp_info;\n+}\n+\n+/**\n+ * Returns a pointer to the phy device associated with a port\n+ *\n+ * @param\txiface\t\tnode and interface\n+ * @param\tindex\t\tport index\n+ *\n+ * return\tpointer to phy device or NULL if none\n+ */\n+struct phy_device *cvmx_helper_cfg_get_phy_device(int xiface, int index)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\treturn cvmx_cfg_port[xi.node][xi.interface][index].phydev;\n+}\n+\n+/**\n+ * Sets the phy device associated with a port\n+ *\n+ * @param\txiface\t\tnode and interface\n+ * @param\tindex\t\tport index\n+ * @param[in]\tphydev\t\tphy device to assiciate\n+ */\n+void cvmx_helper_cfg_set_phy_device(int xiface, int index, struct phy_device *phydev)\n+{\n+\tstruct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);\n+\n+\tif (!port_cfg_data_initialized)\n+\t\tcvmx_init_port_cfg();\n+\tcvmx_cfg_port[xi.node][xi.interface][index].phydev = phydev;\n+}\n", "prefixes": [ "v1", "36/50" ] }