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{
    "id": 1415011,
    "url": "http://patchwork.ozlabs.org/api/patches/1415011/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-33-sr@denx.de/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
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    },
    "msgid": "<20201211160612.1498780-33-sr@denx.de>",
    "list_archive_url": null,
    "date": "2020-12-11T16:05:54",
    "name": "[v1,32/50] mips: octeon: Add cvmx-sso-defs.h header file",
    "commit_ref": "78265141cb88ddd48d8bebef9ef9d985bc5939f9",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "fc34a7f3e8988caaf45588daab22a50ab0f1441e",
    "submitter": {
        "id": 13,
        "url": "http://patchwork.ozlabs.org/api/people/13/?format=api",
        "name": "Stefan Roese",
        "email": "sr@denx.de"
    },
    "delegate": {
        "id": 4307,
        "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api",
        "username": "danielschwierzeck",
        "first_name": "Daniel",
        "last_name": "Schwierzeck",
        "email": "daniel.schwierzeck@googlemail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-33-sr@denx.de/mbox/",
    "series": [
        {
            "id": 220054,
            "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054",
            "date": "2020-12-11T16:05:23",
            "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1415011/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1415011/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Stefan Roese <sr@denx.de>",
        "To": "u-boot@lists.denx.de",
        "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com",
        "Subject": "[PATCH v1 32/50] mips: octeon: Add cvmx-sso-defs.h header file",
        "Date": "Fri, 11 Dec 2020 17:05:54 +0100",
        "Message-Id": "<20201211160612.1498780-33-sr@denx.de>",
        "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>",
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    "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-sso-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-sso-defs.h  | 2904 +++++++++++++++++\n 1 file changed, 2904 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-sso-defs.h",
    "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-sso-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-sso-defs.h\nnew file mode 100644\nindex 0000000000..4fc69079ac\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-sso-defs.h\n@@ -0,0 +1,2904 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon sso.\n+ */\n+\n+#ifndef __CVMX_SSO_DEFS_H__\n+#define __CVMX_SSO_DEFS_H__\n+\n+#define CVMX_SSO_ACTIVE_CYCLES\t\t(0x00016700000010E8ull)\n+#define CVMX_SSO_ACTIVE_CYCLESX(offset) (0x0001670000001100ull + ((offset) & 3) * 8)\n+#define CVMX_SSO_AW_ADD\t\t\t(0x0001670000002080ull)\n+#define CVMX_SSO_AW_CFG\t\t\t(0x00016700000010F0ull)\n+#define CVMX_SSO_AW_ECO\t\t\t(0x0001670000001030ull)\n+#define CVMX_SSO_AW_READ_ARB\t\t(0x0001670000002090ull)\n+#define CVMX_SSO_AW_STATUS\t\t(0x00016700000010E0ull)\n+#define CVMX_SSO_AW_TAG_LATENCY_PC\t(0x00016700000020A8ull)\n+#define CVMX_SSO_AW_TAG_REQ_PC\t\t(0x00016700000020A0ull)\n+#define CVMX_SSO_AW_WE\t\t\t(0x0001670000001080ull)\n+#define CVMX_SSO_BIST_STAT\t\t(0x0001670000001078ull)\n+#define CVMX_SSO_BIST_STATUS0\t\t(0x0001670000001200ull)\n+#define CVMX_SSO_BIST_STATUS1\t\t(0x0001670000001208ull)\n+#define CVMX_SSO_BIST_STATUS2\t\t(0x0001670000001210ull)\n+#define CVMX_SSO_CFG\t\t\t(0x0001670000001088ull)\n+#define CVMX_SSO_DS_PC\t\t\t(0x0001670000001070ull)\n+#define CVMX_SSO_ECC_CTL0\t\t(0x0001670000001280ull)\n+#define CVMX_SSO_ECC_CTL1\t\t(0x0001670000001288ull)\n+#define CVMX_SSO_ECC_CTL2\t\t(0x0001670000001290ull)\n+#define CVMX_SSO_ERR\t\t\t(0x0001670000001038ull)\n+#define CVMX_SSO_ERR0\t\t\t(0x0001670000001240ull)\n+#define CVMX_SSO_ERR1\t\t\t(0x0001670000001248ull)\n+#define CVMX_SSO_ERR2\t\t\t(0x0001670000001250ull)\n+#define CVMX_SSO_ERR_ENB\t\t(0x0001670000001030ull)\n+#define CVMX_SSO_FIDX_ECC_CTL\t\t(0x00016700000010D0ull)\n+#define CVMX_SSO_FIDX_ECC_ST\t\t(0x00016700000010D8ull)\n+#define CVMX_SSO_FPAGE_CNT\t\t(0x0001670000001090ull)\n+#define CVMX_SSO_GRPX_AQ_CNT(offset)\t(0x0001670020000700ull + ((offset) & 255) * 0x10000ull)\n+#define CVMX_SSO_GRPX_AQ_THR(offset)\t(0x0001670020000800ull + ((offset) & 255) * 0x10000ull)\n+#define CVMX_SSO_GRPX_DS_PC(offset)\t(0x0001670020001400ull + ((offset) & 255) * 0x10000ull)\n+#define CVMX_SSO_GRPX_EXT_PC(offset)\t(0x0001670020001100ull + ((offset) & 255) * 0x10000ull)\n+#define CVMX_SSO_GRPX_IAQ_THR(offset)\t(0x0001670020000000ull + ((offset) & 255) * 0x10000ull)\n+#define CVMX_SSO_GRPX_INT(offset)\t(0x0001670020000400ull + ((offset) & 255) * 0x10000ull)\n+#define CVMX_SSO_GRPX_INT_CNT(offset)\t(0x0001670020000600ull + ((offset) & 255) * 0x10000ull)\n+#define CVMX_SSO_GRPX_INT_THR(offset)\t(0x0001670020000500ull + ((offset) & 255) * 0x10000ull)\n+#define CVMX_SSO_GRPX_PRI(offset)\t(0x0001670020000200ull + ((offset) & 255) * 0x10000ull)\n+#define CVMX_SSO_GRPX_TAQ_THR(offset)\t(0x0001670020000100ull + ((offset) & 255) * 0x10000ull)\n+#define CVMX_SSO_GRPX_TS_PC(offset)\t(0x0001670020001300ull + ((offset) & 255) * 0x10000ull)\n+#define CVMX_SSO_GRPX_WA_PC(offset)\t(0x0001670020001200ull + ((offset) & 255) * 0x10000ull)\n+#define CVMX_SSO_GRPX_WS_PC(offset)\t(0x0001670020001000ull + ((offset) & 255) * 0x10000ull)\n+#define CVMX_SSO_GWE_CFG\t\t(0x0001670000001098ull)\n+#define CVMX_SSO_GWE_RANDOM\t\t(0x00016700000010B0ull)\n+#define CVMX_SSO_GW_ECO\t\t\t(0x0001670000001038ull)\n+#define CVMX_SSO_IDX_ECC_CTL\t\t(0x00016700000010C0ull)\n+#define CVMX_SSO_IDX_ECC_ST\t\t(0x00016700000010C8ull)\n+#define CVMX_SSO_IENTX_LINKS(offset)\t(0x00016700A0060000ull + ((offset) & 4095) * 8)\n+#define CVMX_SSO_IENTX_PENDTAG(offset)\t(0x00016700A0040000ull + ((offset) & 4095) * 8)\n+#define CVMX_SSO_IENTX_QLINKS(offset)\t(0x00016700A0080000ull + ((offset) & 4095) * 8)\n+#define CVMX_SSO_IENTX_TAG(offset)\t(0x00016700A0000000ull + ((offset) & 4095) * 8)\n+#define CVMX_SSO_IENTX_WQPGRP(offset)\t(0x00016700A0020000ull + ((offset) & 4095) * 8)\n+#define CVMX_SSO_IPL_CONFX(offset)\t(0x0001670080080000ull + ((offset) & 255) * 8)\n+#define CVMX_SSO_IPL_DESCHEDX(offset)\t(0x0001670080060000ull + ((offset) & 255) * 8)\n+#define CVMX_SSO_IPL_FREEX(offset)\t(0x0001670080000000ull + ((offset) & 7) * 8)\n+#define CVMX_SSO_IPL_IAQX(offset)\t(0x0001670080040000ull + ((offset) & 255) * 8)\n+#define CVMX_SSO_IQ_CNTX(offset)\t(0x0001670000009000ull + ((offset) & 7) * 8)\n+#define CVMX_SSO_IQ_COM_CNT\t\t(0x0001670000001058ull)\n+#define CVMX_SSO_IQ_INT\t\t\t(0x0001670000001048ull)\n+#define CVMX_SSO_IQ_INT_EN\t\t(0x0001670000001050ull)\n+#define CVMX_SSO_IQ_THRX(offset)\t(0x000167000000A000ull + ((offset) & 7) * 8)\n+#define CVMX_SSO_NOS_CNT\t\t(0x0001670000001040ull)\n+#define CVMX_SSO_NW_TIM\t\t\t(0x0001670000001028ull)\n+#define CVMX_SSO_OTH_ECC_CTL\t\t(0x00016700000010B0ull)\n+#define CVMX_SSO_OTH_ECC_ST\t\t(0x00016700000010B8ull)\n+#define CVMX_SSO_PAGE_CNT\t\t(0x0001670000001090ull)\n+#define CVMX_SSO_PND_ECC_CTL\t\t(0x00016700000010A0ull)\n+#define CVMX_SSO_PND_ECC_ST\t\t(0x00016700000010A8ull)\n+#define CVMX_SSO_PPX_ARB(offset)\t(0x0001670040000000ull + ((offset) & 63) * 0x10000ull)\n+#define CVMX_SSO_PPX_GRP_MSK(offset)\t(0x0001670000006000ull + ((offset) & 31) * 8)\n+#define CVMX_SSO_PPX_QOS_PRI(offset)\t(0x0001670000003000ull + ((offset) & 31) * 8)\n+#define CVMX_SSO_PPX_SX_GRPMSKX(a, b, c)                                                           \\\n+\t(0x0001670040001000ull + ((a) << 16) + ((b) << 5) + ((c) << 3))\n+#define CVMX_SSO_PP_STRICT\t  (0x00016700000010E0ull)\n+#define CVMX_SSO_QOSX_RND(offset) (0x0001670000002000ull + ((offset) & 7) * 8)\n+#define CVMX_SSO_QOS_THRX(offset) (0x000167000000B000ull + ((offset) & 7) * 8)\n+#define CVMX_SSO_QOS_WE\t\t  (0x0001670000001080ull)\n+#define CVMX_SSO_RESET\t\t  CVMX_SSO_RESET_FUNC()\n+static inline u64 CVMX_SSO_RESET_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00016700000010F8ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00016700000010F8ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00016700000010F8ull;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00016700000010F0ull;\n+\t}\n+\treturn 0x00016700000010F8ull;\n+}\n+\n+#define CVMX_SSO_RWQ_HEAD_PTRX(offset)\t(0x000167000000C000ull + ((offset) & 7) * 8)\n+#define CVMX_SSO_RWQ_POP_FPTR\t\t(0x000167000000C408ull)\n+#define CVMX_SSO_RWQ_PSH_FPTR\t\t(0x000167000000C400ull)\n+#define CVMX_SSO_RWQ_TAIL_PTRX(offset)\t(0x000167000000C200ull + ((offset) & 7) * 8)\n+#define CVMX_SSO_SL_PPX_LINKS(offset)\t(0x0001670060000040ull + ((offset) & 63) * 0x10000ull)\n+#define CVMX_SSO_SL_PPX_PENDTAG(offset) (0x0001670060000000ull + ((offset) & 63) * 0x10000ull)\n+#define CVMX_SSO_SL_PPX_PENDWQP(offset) (0x0001670060000010ull + ((offset) & 63) * 0x10000ull)\n+#define CVMX_SSO_SL_PPX_TAG(offset)\t(0x0001670060000020ull + ((offset) & 63) * 0x10000ull)\n+#define CVMX_SSO_SL_PPX_WQP(offset)\t(0x0001670060000030ull + ((offset) & 63) * 0x10000ull)\n+#define CVMX_SSO_TAQX_LINK(offset)\t(0x00016700C0000000ull + ((offset) & 2047) * 4096)\n+#define CVMX_SSO_TAQX_WAEX_TAG(offset, block_id)                                                   \\\n+\t(0x00016700D0000000ull + (((offset) & 15) + ((block_id) & 2047) * 0x100ull) * 16)\n+#define CVMX_SSO_TAQX_WAEX_WQP(offset, block_id)                                                   \\\n+\t(0x00016700D0000008ull + (((offset) & 15) + ((block_id) & 2047) * 0x100ull) * 16)\n+#define CVMX_SSO_TAQ_ADD\t\t(0x00016700000020E0ull)\n+#define CVMX_SSO_TAQ_CNT\t\t(0x00016700000020C0ull)\n+#define CVMX_SSO_TIAQX_STATUS(offset)\t(0x00016700000C0000ull + ((offset) & 255) * 8)\n+#define CVMX_SSO_TOAQX_STATUS(offset)\t(0x00016700000D0000ull + ((offset) & 255) * 8)\n+#define CVMX_SSO_TS_PC\t\t\t(0x0001670000001068ull)\n+#define CVMX_SSO_WA_COM_PC\t\t(0x0001670000001060ull)\n+#define CVMX_SSO_WA_PCX(offset)\t\t(0x0001670000005000ull + ((offset) & 7) * 8)\n+#define CVMX_SSO_WQ_INT\t\t\t(0x0001670000001000ull)\n+#define CVMX_SSO_WQ_INT_CNTX(offset)\t(0x0001670000008000ull + ((offset) & 63) * 8)\n+#define CVMX_SSO_WQ_INT_PC\t\t(0x0001670000001020ull)\n+#define CVMX_SSO_WQ_INT_THRX(offset)\t(0x0001670000007000ull + ((offset) & 63) * 8)\n+#define CVMX_SSO_WQ_IQ_DIS\t\t(0x0001670000001010ull)\n+#define CVMX_SSO_WS_CFG\t\t\t(0x0001670000001088ull)\n+#define CVMX_SSO_WS_ECO\t\t\t(0x0001670000001048ull)\n+#define CVMX_SSO_WS_PCX(offset)\t\t(0x0001670000004000ull + ((offset) & 63) * 8)\n+#define CVMX_SSO_XAQX_HEAD_NEXT(offset) (0x00016700000A0000ull + ((offset) & 255) * 8)\n+#define CVMX_SSO_XAQX_HEAD_PTR(offset)\t(0x0001670000080000ull + ((offset) & 255) * 8)\n+#define CVMX_SSO_XAQX_TAIL_NEXT(offset) (0x00016700000B0000ull + ((offset) & 255) * 8)\n+#define CVMX_SSO_XAQX_TAIL_PTR(offset)\t(0x0001670000090000ull + ((offset) & 255) * 8)\n+#define CVMX_SSO_XAQ_AURA\t\t(0x0001670000002100ull)\n+#define CVMX_SSO_XAQ_LATENCY_PC\t\t(0x00016700000020B8ull)\n+#define CVMX_SSO_XAQ_REQ_PC\t\t(0x00016700000020B0ull)\n+\n+/**\n+ * cvmx_sso_active_cycles\n+ *\n+ * SSO_ACTIVE_CYCLES = SSO cycles SSO active\n+ *\n+ * This register counts every sclk cycle that the SSO clocks are active.\n+ * **NOTE: Added in pass 2.0\n+ */\n+union cvmx_sso_active_cycles {\n+\tu64 u64;\n+\tstruct cvmx_sso_active_cycles_s {\n+\t\tu64 act_cyc : 64;\n+\t} s;\n+\tstruct cvmx_sso_active_cycles_s cn68xx;\n+};\n+\n+typedef union cvmx_sso_active_cycles cvmx_sso_active_cycles_t;\n+\n+/**\n+ * cvmx_sso_active_cycles#\n+ *\n+ * This register counts every coprocessor clock (SCLK) cycle that the SSO clocks are active.\n+ *\n+ */\n+union cvmx_sso_active_cyclesx {\n+\tu64 u64;\n+\tstruct cvmx_sso_active_cyclesx_s {\n+\t\tu64 act_cyc : 64;\n+\t} s;\n+\tstruct cvmx_sso_active_cyclesx_s cn73xx;\n+\tstruct cvmx_sso_active_cyclesx_s cn78xx;\n+\tstruct cvmx_sso_active_cyclesx_s cn78xxp1;\n+\tstruct cvmx_sso_active_cyclesx_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_active_cyclesx cvmx_sso_active_cyclesx_t;\n+\n+/**\n+ * cvmx_sso_aw_add\n+ */\n+union cvmx_sso_aw_add {\n+\tu64 u64;\n+\tstruct cvmx_sso_aw_add_s {\n+\t\tu64 reserved_30_63 : 34;\n+\t\tu64 rsvd_free : 14;\n+\t\tu64 reserved_0_15 : 16;\n+\t} s;\n+\tstruct cvmx_sso_aw_add_s cn73xx;\n+\tstruct cvmx_sso_aw_add_s cn78xx;\n+\tstruct cvmx_sso_aw_add_s cn78xxp1;\n+\tstruct cvmx_sso_aw_add_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_aw_add cvmx_sso_aw_add_t;\n+\n+/**\n+ * cvmx_sso_aw_cfg\n+ *\n+ * This register controls the operation of the add-work block (AW).\n+ *\n+ */\n+union cvmx_sso_aw_cfg {\n+\tu64 u64;\n+\tstruct cvmx_sso_aw_cfg_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 ldt_short : 1;\n+\t\tu64 lol : 1;\n+\t\tu64 xaq_alloc_dis : 1;\n+\t\tu64 ocla_bp : 1;\n+\t\tu64 xaq_byp_dis : 1;\n+\t\tu64 stt : 1;\n+\t\tu64 ldt : 1;\n+\t\tu64 ldwb : 1;\n+\t\tu64 rwen : 1;\n+\t} s;\n+\tstruct cvmx_sso_aw_cfg_s cn73xx;\n+\tstruct cvmx_sso_aw_cfg_s cn78xx;\n+\tstruct cvmx_sso_aw_cfg_s cn78xxp1;\n+\tstruct cvmx_sso_aw_cfg_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_aw_cfg cvmx_sso_aw_cfg_t;\n+\n+/**\n+ * cvmx_sso_aw_eco\n+ */\n+union cvmx_sso_aw_eco {\n+\tu64 u64;\n+\tstruct cvmx_sso_aw_eco_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 eco_rw : 8;\n+\t} s;\n+\tstruct cvmx_sso_aw_eco_s cn73xx;\n+\tstruct cvmx_sso_aw_eco_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_aw_eco cvmx_sso_aw_eco_t;\n+\n+/**\n+ * cvmx_sso_aw_read_arb\n+ *\n+ * This register fine tunes the AW read arbiter and is for diagnostic use.\n+ *\n+ */\n+union cvmx_sso_aw_read_arb {\n+\tu64 u64;\n+\tstruct cvmx_sso_aw_read_arb_s {\n+\t\tu64 reserved_30_63 : 34;\n+\t\tu64 xaq_lev : 6;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 xaq_min : 5;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 aw_tag_lev : 6;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 aw_tag_min : 5;\n+\t} s;\n+\tstruct cvmx_sso_aw_read_arb_s cn73xx;\n+\tstruct cvmx_sso_aw_read_arb_s cn78xx;\n+\tstruct cvmx_sso_aw_read_arb_s cn78xxp1;\n+\tstruct cvmx_sso_aw_read_arb_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_aw_read_arb cvmx_sso_aw_read_arb_t;\n+\n+/**\n+ * cvmx_sso_aw_status\n+ *\n+ * This register indicates the status of the add-work block (AW).\n+ *\n+ */\n+union cvmx_sso_aw_status {\n+\tu64 u64;\n+\tstruct cvmx_sso_aw_status_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 xaq_buf_cached : 6;\n+\t} s;\n+\tstruct cvmx_sso_aw_status_s cn73xx;\n+\tstruct cvmx_sso_aw_status_s cn78xx;\n+\tstruct cvmx_sso_aw_status_s cn78xxp1;\n+\tstruct cvmx_sso_aw_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_aw_status cvmx_sso_aw_status_t;\n+\n+/**\n+ * cvmx_sso_aw_tag_latency_pc\n+ */\n+union cvmx_sso_aw_tag_latency_pc {\n+\tu64 u64;\n+\tstruct cvmx_sso_aw_tag_latency_pc_s {\n+\t\tu64 count : 64;\n+\t} s;\n+\tstruct cvmx_sso_aw_tag_latency_pc_s cn73xx;\n+\tstruct cvmx_sso_aw_tag_latency_pc_s cn78xx;\n+\tstruct cvmx_sso_aw_tag_latency_pc_s cn78xxp1;\n+\tstruct cvmx_sso_aw_tag_latency_pc_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_aw_tag_latency_pc cvmx_sso_aw_tag_latency_pc_t;\n+\n+/**\n+ * cvmx_sso_aw_tag_req_pc\n+ */\n+union cvmx_sso_aw_tag_req_pc {\n+\tu64 u64;\n+\tstruct cvmx_sso_aw_tag_req_pc_s {\n+\t\tu64 count : 64;\n+\t} s;\n+\tstruct cvmx_sso_aw_tag_req_pc_s cn73xx;\n+\tstruct cvmx_sso_aw_tag_req_pc_s cn78xx;\n+\tstruct cvmx_sso_aw_tag_req_pc_s cn78xxp1;\n+\tstruct cvmx_sso_aw_tag_req_pc_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_aw_tag_req_pc cvmx_sso_aw_tag_req_pc_t;\n+\n+/**\n+ * cvmx_sso_aw_we\n+ */\n+union cvmx_sso_aw_we {\n+\tu64 u64;\n+\tstruct cvmx_sso_aw_we_s {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 rsvd_free : 13;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 free_cnt : 13;\n+\t} s;\n+\tstruct cvmx_sso_aw_we_s cn73xx;\n+\tstruct cvmx_sso_aw_we_s cn78xx;\n+\tstruct cvmx_sso_aw_we_s cn78xxp1;\n+\tstruct cvmx_sso_aw_we_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_aw_we cvmx_sso_aw_we_t;\n+\n+/**\n+ * cvmx_sso_bist_stat\n+ *\n+ * SSO_BIST_STAT = SSO BIST Status Register\n+ *\n+ * Contains the BIST status for the SSO memories ('0' = pass, '1' = fail).\n+ * Note that PP BIST status is not reported here as it was in previous designs.\n+ *\n+ *   There may be more for DDR interface buffers.\n+ *   It's possible that a RAM will be used for SSO_PP_QOS_RND.\n+ */\n+union cvmx_sso_bist_stat {\n+\tu64 u64;\n+\tstruct cvmx_sso_bist_stat_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 odu_pref : 2;\n+\t\tu64 reserved_54_59 : 6;\n+\t\tu64 fptr : 2;\n+\t\tu64 reserved_45_51 : 7;\n+\t\tu64 rwo_dat : 1;\n+\t\tu64 rwo : 2;\n+\t\tu64 reserved_35_41 : 7;\n+\t\tu64 rwi_dat : 1;\n+\t\tu64 reserved_32_33 : 2;\n+\t\tu64 soc : 1;\n+\t\tu64 reserved_28_30 : 3;\n+\t\tu64 ncbo : 4;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 index : 1;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 fidx : 1;\n+\t\tu64 reserved_10_15 : 6;\n+\t\tu64 pend : 2;\n+\t\tu64 reserved_2_7 : 6;\n+\t\tu64 oth : 2;\n+\t} s;\n+\tstruct cvmx_sso_bist_stat_s cn68xx;\n+\tstruct cvmx_sso_bist_stat_cn68xxp1 {\n+\t\tu64 reserved_54_63 : 10;\n+\t\tu64 fptr : 2;\n+\t\tu64 reserved_45_51 : 7;\n+\t\tu64 rwo_dat : 1;\n+\t\tu64 rwo : 2;\n+\t\tu64 reserved_35_41 : 7;\n+\t\tu64 rwi_dat : 1;\n+\t\tu64 reserved_32_33 : 2;\n+\t\tu64 soc : 1;\n+\t\tu64 reserved_28_30 : 3;\n+\t\tu64 ncbo : 4;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 index : 1;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 fidx : 1;\n+\t\tu64 reserved_10_15 : 6;\n+\t\tu64 pend : 2;\n+\t\tu64 reserved_2_7 : 6;\n+\t\tu64 oth : 2;\n+\t} cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_bist_stat cvmx_sso_bist_stat_t;\n+\n+/**\n+ * cvmx_sso_bist_status0\n+ *\n+ * Contains the BIST status for the SSO memories.\n+ *\n+ */\n+union cvmx_sso_bist_status0 {\n+\tu64 u64;\n+\tstruct cvmx_sso_bist_status0_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 bist : 10;\n+\t} s;\n+\tstruct cvmx_sso_bist_status0_s cn73xx;\n+\tstruct cvmx_sso_bist_status0_s cn78xx;\n+\tstruct cvmx_sso_bist_status0_s cn78xxp1;\n+\tstruct cvmx_sso_bist_status0_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_bist_status0 cvmx_sso_bist_status0_t;\n+\n+/**\n+ * cvmx_sso_bist_status1\n+ *\n+ * Contains the BIST status for the SSO memories.\n+ *\n+ */\n+union cvmx_sso_bist_status1 {\n+\tu64 u64;\n+\tstruct cvmx_sso_bist_status1_s {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 bist : 7;\n+\t} s;\n+\tstruct cvmx_sso_bist_status1_s cn73xx;\n+\tstruct cvmx_sso_bist_status1_s cn78xx;\n+\tstruct cvmx_sso_bist_status1_s cn78xxp1;\n+\tstruct cvmx_sso_bist_status1_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_bist_status1 cvmx_sso_bist_status1_t;\n+\n+/**\n+ * cvmx_sso_bist_status2\n+ *\n+ * Contains the BIST status for the SSO memories.\n+ *\n+ */\n+union cvmx_sso_bist_status2 {\n+\tu64 u64;\n+\tstruct cvmx_sso_bist_status2_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 bist : 9;\n+\t} s;\n+\tstruct cvmx_sso_bist_status2_s cn73xx;\n+\tstruct cvmx_sso_bist_status2_s cn78xx;\n+\tstruct cvmx_sso_bist_status2_s cn78xxp1;\n+\tstruct cvmx_sso_bist_status2_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_bist_status2 cvmx_sso_bist_status2_t;\n+\n+/**\n+ * cvmx_sso_cfg\n+ *\n+ * SSO_CFG = SSO Config\n+ *\n+ * This register is an assortment of various SSO configuration bits.\n+ */\n+union cvmx_sso_cfg {\n+\tu64 u64;\n+\tstruct cvmx_sso_cfg_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 qck_gw_rsp_adj : 3;\n+\t\tu64 qck_gw_rsp_dis : 1;\n+\t\tu64 qck_sw_dis : 1;\n+\t\tu64 rwq_alloc_dis : 1;\n+\t\tu64 soc_ccam_dis : 1;\n+\t\tu64 sso_cclk_dis : 1;\n+\t\tu64 rwo_flush : 1;\n+\t\tu64 wfe_thr : 1;\n+\t\tu64 rwio_byp_dis : 1;\n+\t\tu64 rwq_byp_dis : 1;\n+\t\tu64 stt : 1;\n+\t\tu64 ldt : 1;\n+\t\tu64 dwb : 1;\n+\t\tu64 rwen : 1;\n+\t} s;\n+\tstruct cvmx_sso_cfg_s cn68xx;\n+\tstruct cvmx_sso_cfg_cn68xxp1 {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 rwo_flush : 1;\n+\t\tu64 wfe_thr : 1;\n+\t\tu64 rwio_byp_dis : 1;\n+\t\tu64 rwq_byp_dis : 1;\n+\t\tu64 stt : 1;\n+\t\tu64 ldt : 1;\n+\t\tu64 dwb : 1;\n+\t\tu64 rwen : 1;\n+\t} cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_cfg cvmx_sso_cfg_t;\n+\n+/**\n+ * cvmx_sso_ds_pc\n+ *\n+ * SSO_DS_PC = SSO De-Schedule Performance Counter\n+ *\n+ * Counts the number of de-schedule requests.\n+ * Counter rolls over through zero when max value exceeded.\n+ */\n+union cvmx_sso_ds_pc {\n+\tu64 u64;\n+\tstruct cvmx_sso_ds_pc_s {\n+\t\tu64 ds_pc : 64;\n+\t} s;\n+\tstruct cvmx_sso_ds_pc_s cn68xx;\n+\tstruct cvmx_sso_ds_pc_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_ds_pc cvmx_sso_ds_pc_t;\n+\n+/**\n+ * cvmx_sso_ecc_ctl0\n+ */\n+union cvmx_sso_ecc_ctl0 {\n+\tu64 u64;\n+\tstruct cvmx_sso_ecc_ctl0_s {\n+\t\tu64 reserved_30_63 : 34;\n+\t\tu64 toaqt_flip : 2;\n+\t\tu64 toaqt_cdis : 1;\n+\t\tu64 toaqh_flip : 2;\n+\t\tu64 toaqh_cdis : 1;\n+\t\tu64 tiaqt_flip : 2;\n+\t\tu64 tiaqt_cdis : 1;\n+\t\tu64 tiaqh_flip : 2;\n+\t\tu64 tiaqh_cdis : 1;\n+\t\tu64 llm_flip : 2;\n+\t\tu64 llm_cdis : 1;\n+\t\tu64 inp_flip : 2;\n+\t\tu64 inp_cdis : 1;\n+\t\tu64 qtc_flip : 2;\n+\t\tu64 qtc_cdis : 1;\n+\t\tu64 xaq_flip : 2;\n+\t\tu64 xaq_cdis : 1;\n+\t\tu64 fff_flip : 2;\n+\t\tu64 fff_cdis : 1;\n+\t\tu64 wes_flip : 2;\n+\t\tu64 wes_cdis : 1;\n+\t} s;\n+\tstruct cvmx_sso_ecc_ctl0_s cn73xx;\n+\tstruct cvmx_sso_ecc_ctl0_s cn78xx;\n+\tstruct cvmx_sso_ecc_ctl0_s cn78xxp1;\n+\tstruct cvmx_sso_ecc_ctl0_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ecc_ctl0 cvmx_sso_ecc_ctl0_t;\n+\n+/**\n+ * cvmx_sso_ecc_ctl1\n+ */\n+union cvmx_sso_ecc_ctl1 {\n+\tu64 u64;\n+\tstruct cvmx_sso_ecc_ctl1_s {\n+\t\tu64 reserved_21_63 : 43;\n+\t\tu64 thrint_flip : 2;\n+\t\tu64 thrint_cdis : 1;\n+\t\tu64 mask_flip : 2;\n+\t\tu64 mask_cdis : 1;\n+\t\tu64 gdw_flip : 2;\n+\t\tu64 gdw_cdis : 1;\n+\t\tu64 qidx_flip : 2;\n+\t\tu64 qidx_cdis : 1;\n+\t\tu64 tptr_flip : 2;\n+\t\tu64 tptr_cdis : 1;\n+\t\tu64 hptr_flip : 2;\n+\t\tu64 hptr_cdis : 1;\n+\t\tu64 cntr_flip : 2;\n+\t\tu64 cntr_cdis : 1;\n+\t} s;\n+\tstruct cvmx_sso_ecc_ctl1_s cn73xx;\n+\tstruct cvmx_sso_ecc_ctl1_s cn78xx;\n+\tstruct cvmx_sso_ecc_ctl1_s cn78xxp1;\n+\tstruct cvmx_sso_ecc_ctl1_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ecc_ctl1 cvmx_sso_ecc_ctl1_t;\n+\n+/**\n+ * cvmx_sso_ecc_ctl2\n+ */\n+union cvmx_sso_ecc_ctl2 {\n+\tu64 u64;\n+\tstruct cvmx_sso_ecc_ctl2_s {\n+\t\tu64 reserved_15_63 : 49;\n+\t\tu64 ncbo_flip : 2;\n+\t\tu64 ncbo_cdis : 1;\n+\t\tu64 pnd_flip : 2;\n+\t\tu64 pnd_cdis : 1;\n+\t\tu64 oth_flip : 2;\n+\t\tu64 oth_cdis : 1;\n+\t\tu64 nidx_flip : 2;\n+\t\tu64 nidx_cdis : 1;\n+\t\tu64 pidx_flip : 2;\n+\t\tu64 pidx_cdis : 1;\n+\t} s;\n+\tstruct cvmx_sso_ecc_ctl2_s cn73xx;\n+\tstruct cvmx_sso_ecc_ctl2_s cn78xx;\n+\tstruct cvmx_sso_ecc_ctl2_s cn78xxp1;\n+\tstruct cvmx_sso_ecc_ctl2_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ecc_ctl2 cvmx_sso_ecc_ctl2_t;\n+\n+/**\n+ * cvmx_sso_err\n+ *\n+ * SSO_ERR = SSO Error Register\n+ *\n+ * Contains ECC and other misc error bits.\n+ *\n+ * <45> The free page error bit will assert when SSO_FPAGE_CNT <= 16 and\n+ *      SSO_CFG[RWEN] is 1.  Software will want to disable the interrupt\n+ *      associated with this error when recovering SSO pointers from the\n+ *      FPA and SSO.\n+ *\n+ * This register also contains the illegal operation error bits:\n+ *\n+ * <42> Received ADDWQ with tag specified as EMPTY\n+ * <41> Received illegal opcode\n+ * <40> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/ALLOC_WE\n+ *      from WS with CLR_NSCHED pending\n+ * <39> Received CLR_NSCHED\n+ *      from WS with SWTAG_DESCH/DESCH/CLR_NSCHED pending\n+ * <38> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/ALLOC_WE\n+ *      from WS with ALLOC_WE pending\n+ * <37> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/ALLOC_WE/CLR_NSCHED\n+ *      from WS with GET_WORK pending\n+ * <36> Received SWTAG_FULL/SWTAG_DESCH\n+ *      with tag specified as UNSCHEDULED\n+ * <35> Received SWTAG/SWTAG_FULL/SWTAG_DESCH\n+ *      with tag specified as EMPTY\n+ * <34> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK\n+ *      from WS with pending tag switch to ORDERED or ATOMIC\n+ * <33> Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP\n+ *      from WS in UNSCHEDULED state\n+ * <32> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP\n+ *      from WS in EMPTY state\n+ */\n+union cvmx_sso_err {\n+\tu64 u64;\n+\tstruct cvmx_sso_err_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 bfp : 1;\n+\t\tu64 awe : 1;\n+\t\tu64 fpe : 1;\n+\t\tu64 reserved_43_44 : 2;\n+\t\tu64 iop : 11;\n+\t\tu64 reserved_12_31 : 20;\n+\t\tu64 pnd_dbe0 : 1;\n+\t\tu64 pnd_sbe0 : 1;\n+\t\tu64 pnd_dbe1 : 1;\n+\t\tu64 pnd_sbe1 : 1;\n+\t\tu64 oth_dbe0 : 1;\n+\t\tu64 oth_sbe0 : 1;\n+\t\tu64 oth_dbe1 : 1;\n+\t\tu64 oth_sbe1 : 1;\n+\t\tu64 idx_dbe : 1;\n+\t\tu64 idx_sbe : 1;\n+\t\tu64 fidx_dbe : 1;\n+\t\tu64 fidx_sbe : 1;\n+\t} s;\n+\tstruct cvmx_sso_err_s cn68xx;\n+\tstruct cvmx_sso_err_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_err cvmx_sso_err_t;\n+\n+/**\n+ * cvmx_sso_err0\n+ *\n+ * This register contains ECC and other miscellaneous error bits.\n+ *\n+ */\n+union cvmx_sso_err0 {\n+\tu64 u64;\n+\tstruct cvmx_sso_err0_s {\n+\t\tu64 reserved_52_63 : 12;\n+\t\tu64 toaqt_dbe : 1;\n+\t\tu64 toaqt_sbe : 1;\n+\t\tu64 toaqh_dbe : 1;\n+\t\tu64 toaqh_sbe : 1;\n+\t\tu64 tiaqt_dbe : 1;\n+\t\tu64 tiaqt_sbe : 1;\n+\t\tu64 tiaqh_dbe : 1;\n+\t\tu64 tiaqh_sbe : 1;\n+\t\tu64 llm_dbe : 1;\n+\t\tu64 llm_sbe : 1;\n+\t\tu64 inp_dbe : 1;\n+\t\tu64 inp_sbe : 1;\n+\t\tu64 qtc_dbe : 1;\n+\t\tu64 qtc_sbe : 1;\n+\t\tu64 xaq_dbe : 1;\n+\t\tu64 xaq_sbe : 1;\n+\t\tu64 fff_dbe : 1;\n+\t\tu64 fff_sbe : 1;\n+\t\tu64 wes_dbe : 1;\n+\t\tu64 wes_sbe : 1;\n+\t\tu64 reserved_6_31 : 26;\n+\t\tu64 addwq_dropped : 1;\n+\t\tu64 awempty : 1;\n+\t\tu64 grpdis : 1;\n+\t\tu64 bfp : 1;\n+\t\tu64 awe : 1;\n+\t\tu64 fpe : 1;\n+\t} s;\n+\tstruct cvmx_sso_err0_s cn73xx;\n+\tstruct cvmx_sso_err0_s cn78xx;\n+\tstruct cvmx_sso_err0_s cn78xxp1;\n+\tstruct cvmx_sso_err0_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_err0 cvmx_sso_err0_t;\n+\n+/**\n+ * cvmx_sso_err1\n+ *\n+ * This register contains ECC and other miscellaneous error bits.\n+ *\n+ */\n+union cvmx_sso_err1 {\n+\tu64 u64;\n+\tstruct cvmx_sso_err1_s {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 thrint_dbe : 1;\n+\t\tu64 thrint_sbe : 1;\n+\t\tu64 mask_dbe : 1;\n+\t\tu64 mask_sbe : 1;\n+\t\tu64 gdw_dbe : 1;\n+\t\tu64 gdw_sbe : 1;\n+\t\tu64 qidx_dbe : 1;\n+\t\tu64 qidx_sbe : 1;\n+\t\tu64 tptr_dbe : 1;\n+\t\tu64 tptr_sbe : 1;\n+\t\tu64 hptr_dbe : 1;\n+\t\tu64 hptr_sbe : 1;\n+\t\tu64 cntr_dbe : 1;\n+\t\tu64 cntr_sbe : 1;\n+\t} s;\n+\tstruct cvmx_sso_err1_s cn73xx;\n+\tstruct cvmx_sso_err1_s cn78xx;\n+\tstruct cvmx_sso_err1_s cn78xxp1;\n+\tstruct cvmx_sso_err1_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_err1 cvmx_sso_err1_t;\n+\n+/**\n+ * cvmx_sso_err2\n+ *\n+ * This register contains ECC and other miscellaneous error bits.\n+ *\n+ */\n+union cvmx_sso_err2 {\n+\tu64 u64;\n+\tstruct cvmx_sso_err2_s {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 ncbo_dbe : 1;\n+\t\tu64 ncbo_sbe : 1;\n+\t\tu64 pnd_dbe : 1;\n+\t\tu64 pnd_sbe : 1;\n+\t\tu64 oth_dbe : 1;\n+\t\tu64 oth_sbe : 1;\n+\t\tu64 nidx_dbe : 1;\n+\t\tu64 nidx_sbe : 1;\n+\t\tu64 pidx_dbe : 1;\n+\t\tu64 pidx_sbe : 1;\n+\t\tu64 reserved_13_31 : 19;\n+\t\tu64 iop : 13;\n+\t} s;\n+\tstruct cvmx_sso_err2_s cn73xx;\n+\tstruct cvmx_sso_err2_s cn78xx;\n+\tstruct cvmx_sso_err2_s cn78xxp1;\n+\tstruct cvmx_sso_err2_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_err2 cvmx_sso_err2_t;\n+\n+/**\n+ * cvmx_sso_err_enb\n+ *\n+ * SSO_ERR_ENB = SSO Error Enable Register\n+ *\n+ * Contains the interrupt enables corresponding to SSO_ERR.\n+ */\n+union cvmx_sso_err_enb {\n+\tu64 u64;\n+\tstruct cvmx_sso_err_enb_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 bfp_ie : 1;\n+\t\tu64 awe_ie : 1;\n+\t\tu64 fpe_ie : 1;\n+\t\tu64 reserved_43_44 : 2;\n+\t\tu64 iop_ie : 11;\n+\t\tu64 reserved_12_31 : 20;\n+\t\tu64 pnd_dbe0_ie : 1;\n+\t\tu64 pnd_sbe0_ie : 1;\n+\t\tu64 pnd_dbe1_ie : 1;\n+\t\tu64 pnd_sbe1_ie : 1;\n+\t\tu64 oth_dbe0_ie : 1;\n+\t\tu64 oth_sbe0_ie : 1;\n+\t\tu64 oth_dbe1_ie : 1;\n+\t\tu64 oth_sbe1_ie : 1;\n+\t\tu64 idx_dbe_ie : 1;\n+\t\tu64 idx_sbe_ie : 1;\n+\t\tu64 fidx_dbe_ie : 1;\n+\t\tu64 fidx_sbe_ie : 1;\n+\t} s;\n+\tstruct cvmx_sso_err_enb_s cn68xx;\n+\tstruct cvmx_sso_err_enb_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_err_enb cvmx_sso_err_enb_t;\n+\n+/**\n+ * cvmx_sso_fidx_ecc_ctl\n+ *\n+ * SSO_FIDX_ECC_CTL = SSO FIDX ECC Control\n+ *\n+ */\n+union cvmx_sso_fidx_ecc_ctl {\n+\tu64 u64;\n+\tstruct cvmx_sso_fidx_ecc_ctl_s {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 flip_synd : 2;\n+\t\tu64 ecc_ena : 1;\n+\t} s;\n+\tstruct cvmx_sso_fidx_ecc_ctl_s cn68xx;\n+\tstruct cvmx_sso_fidx_ecc_ctl_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_fidx_ecc_ctl cvmx_sso_fidx_ecc_ctl_t;\n+\n+/**\n+ * cvmx_sso_fidx_ecc_st\n+ *\n+ * SSO_FIDX_ECC_ST = SSO FIDX ECC Status\n+ *\n+ */\n+union cvmx_sso_fidx_ecc_st {\n+\tu64 u64;\n+\tstruct cvmx_sso_fidx_ecc_st_s {\n+\t\tu64 reserved_27_63 : 37;\n+\t\tu64 addr : 11;\n+\t\tu64 reserved_9_15 : 7;\n+\t\tu64 syndrom : 5;\n+\t\tu64 reserved_0_3 : 4;\n+\t} s;\n+\tstruct cvmx_sso_fidx_ecc_st_s cn68xx;\n+\tstruct cvmx_sso_fidx_ecc_st_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_fidx_ecc_st cvmx_sso_fidx_ecc_st_t;\n+\n+/**\n+ * cvmx_sso_fpage_cnt\n+ *\n+ * SSO_FPAGE_CNT = SSO Free Page Cnt\n+ *\n+ * This register keeps track of the number of free pages pointers available for use in external memory.\n+ */\n+union cvmx_sso_fpage_cnt {\n+\tu64 u64;\n+\tstruct cvmx_sso_fpage_cnt_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 fpage_cnt : 32;\n+\t} s;\n+\tstruct cvmx_sso_fpage_cnt_s cn68xx;\n+\tstruct cvmx_sso_fpage_cnt_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_fpage_cnt cvmx_sso_fpage_cnt_t;\n+\n+/**\n+ * cvmx_sso_grp#_aq_cnt\n+ */\n+union cvmx_sso_grpx_aq_cnt {\n+\tu64 u64;\n+\tstruct cvmx_sso_grpx_aq_cnt_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 aq_cnt : 33;\n+\t} s;\n+\tstruct cvmx_sso_grpx_aq_cnt_s cn73xx;\n+\tstruct cvmx_sso_grpx_aq_cnt_s cn78xx;\n+\tstruct cvmx_sso_grpx_aq_cnt_s cn78xxp1;\n+\tstruct cvmx_sso_grpx_aq_cnt_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_grpx_aq_cnt cvmx_sso_grpx_aq_cnt_t;\n+\n+/**\n+ * cvmx_sso_grp#_aq_thr\n+ */\n+union cvmx_sso_grpx_aq_thr {\n+\tu64 u64;\n+\tstruct cvmx_sso_grpx_aq_thr_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 aq_thr : 33;\n+\t} s;\n+\tstruct cvmx_sso_grpx_aq_thr_s cn73xx;\n+\tstruct cvmx_sso_grpx_aq_thr_s cn78xx;\n+\tstruct cvmx_sso_grpx_aq_thr_s cn78xxp1;\n+\tstruct cvmx_sso_grpx_aq_thr_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_grpx_aq_thr cvmx_sso_grpx_aq_thr_t;\n+\n+/**\n+ * cvmx_sso_grp#_ds_pc\n+ *\n+ * Counts the number of deschedule requests for each group. Counter rolls over through zero when\n+ * max value exceeded.\n+ */\n+union cvmx_sso_grpx_ds_pc {\n+\tu64 u64;\n+\tstruct cvmx_sso_grpx_ds_pc_s {\n+\t\tu64 cnt : 64;\n+\t} s;\n+\tstruct cvmx_sso_grpx_ds_pc_s cn73xx;\n+\tstruct cvmx_sso_grpx_ds_pc_s cn78xx;\n+\tstruct cvmx_sso_grpx_ds_pc_s cn78xxp1;\n+\tstruct cvmx_sso_grpx_ds_pc_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_grpx_ds_pc cvmx_sso_grpx_ds_pc_t;\n+\n+/**\n+ * cvmx_sso_grp#_ext_pc\n+ *\n+ * Counts the number of cache lines of WAEs sent to L2/DDR. Counter rolls over through zero when\n+ * max value exceeded.\n+ */\n+union cvmx_sso_grpx_ext_pc {\n+\tu64 u64;\n+\tstruct cvmx_sso_grpx_ext_pc_s {\n+\t\tu64 cnt : 64;\n+\t} s;\n+\tstruct cvmx_sso_grpx_ext_pc_s cn73xx;\n+\tstruct cvmx_sso_grpx_ext_pc_s cn78xx;\n+\tstruct cvmx_sso_grpx_ext_pc_s cn78xxp1;\n+\tstruct cvmx_sso_grpx_ext_pc_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_grpx_ext_pc cvmx_sso_grpx_ext_pc_t;\n+\n+/**\n+ * cvmx_sso_grp#_iaq_thr\n+ *\n+ * These registers contain the thresholds for allocating SSO in-unit admission queue entries, see\n+ * In-Unit Thresholds.\n+ */\n+union cvmx_sso_grpx_iaq_thr {\n+\tu64 u64;\n+\tstruct cvmx_sso_grpx_iaq_thr_s {\n+\t\tu64 reserved_61_63 : 3;\n+\t\tu64 grp_cnt : 13;\n+\t\tu64 reserved_45_47 : 3;\n+\t\tu64 max_thr : 13;\n+\t\tu64 reserved_13_31 : 19;\n+\t\tu64 rsvd_thr : 13;\n+\t} s;\n+\tstruct cvmx_sso_grpx_iaq_thr_s cn73xx;\n+\tstruct cvmx_sso_grpx_iaq_thr_s cn78xx;\n+\tstruct cvmx_sso_grpx_iaq_thr_s cn78xxp1;\n+\tstruct cvmx_sso_grpx_iaq_thr_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_grpx_iaq_thr cvmx_sso_grpx_iaq_thr_t;\n+\n+/**\n+ * cvmx_sso_grp#_int\n+ *\n+ * Contains the per-group interrupts and are used to clear these interrupts. For more information\n+ * on this register, refer to Interrupts.\n+ */\n+union cvmx_sso_grpx_int {\n+\tu64 u64;\n+\tstruct cvmx_sso_grpx_int_s {\n+\t\tu64 exe_dis : 1;\n+\t\tu64 reserved_2_62 : 61;\n+\t\tu64 exe_int : 1;\n+\t\tu64 aq_int : 1;\n+\t} s;\n+\tstruct cvmx_sso_grpx_int_s cn73xx;\n+\tstruct cvmx_sso_grpx_int_s cn78xx;\n+\tstruct cvmx_sso_grpx_int_s cn78xxp1;\n+\tstruct cvmx_sso_grpx_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_grpx_int cvmx_sso_grpx_int_t;\n+\n+/**\n+ * cvmx_sso_grp#_int_cnt\n+ *\n+ * These registers contain a read-only copy of the counts used to trigger work-queue interrupts\n+ * (one per group). For more information on this register, refer to Interrupts.\n+ */\n+union cvmx_sso_grpx_int_cnt {\n+\tu64 u64;\n+\tstruct cvmx_sso_grpx_int_cnt_s {\n+\t\tu64 reserved_61_63 : 3;\n+\t\tu64 tc_cnt : 13;\n+\t\tu64 reserved_45_47 : 3;\n+\t\tu64 cq_cnt : 13;\n+\t\tu64 reserved_29_31 : 3;\n+\t\tu64 ds_cnt : 13;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 iaq_cnt : 13;\n+\t} s;\n+\tstruct cvmx_sso_grpx_int_cnt_s cn73xx;\n+\tstruct cvmx_sso_grpx_int_cnt_s cn78xx;\n+\tstruct cvmx_sso_grpx_int_cnt_s cn78xxp1;\n+\tstruct cvmx_sso_grpx_int_cnt_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_grpx_int_cnt cvmx_sso_grpx_int_cnt_t;\n+\n+/**\n+ * cvmx_sso_grp#_int_thr\n+ *\n+ * These registers contain the thresholds for enabling and setting work-queue interrupts (one per\n+ * group). For more information on this register, refer to Interrupts.\n+ */\n+union cvmx_sso_grpx_int_thr {\n+\tu64 u64;\n+\tstruct cvmx_sso_grpx_int_thr_s {\n+\t\tu64 tc_en : 1;\n+\t\tu64 reserved_61_62 : 2;\n+\t\tu64 tc_thr : 13;\n+\t\tu64 reserved_45_47 : 3;\n+\t\tu64 cq_thr : 13;\n+\t\tu64 reserved_29_31 : 3;\n+\t\tu64 ds_thr : 13;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 iaq_thr : 13;\n+\t} s;\n+\tstruct cvmx_sso_grpx_int_thr_s cn73xx;\n+\tstruct cvmx_sso_grpx_int_thr_s cn78xx;\n+\tstruct cvmx_sso_grpx_int_thr_s cn78xxp1;\n+\tstruct cvmx_sso_grpx_int_thr_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_grpx_int_thr cvmx_sso_grpx_int_thr_t;\n+\n+/**\n+ * cvmx_sso_grp#_pri\n+ *\n+ * Controls the priority and group affinity arbitration for each group.\n+ *\n+ */\n+union cvmx_sso_grpx_pri {\n+\tu64 u64;\n+\tstruct cvmx_sso_grpx_pri_s {\n+\t\tu64 reserved_30_63 : 34;\n+\t\tu64 wgt_left : 6;\n+\t\tu64 reserved_22_23 : 2;\n+\t\tu64 weight : 6;\n+\t\tu64 reserved_12_15 : 4;\n+\t\tu64 affinity : 4;\n+\t\tu64 reserved_3_7 : 5;\n+\t\tu64 pri : 3;\n+\t} s;\n+\tstruct cvmx_sso_grpx_pri_s cn73xx;\n+\tstruct cvmx_sso_grpx_pri_s cn78xx;\n+\tstruct cvmx_sso_grpx_pri_s cn78xxp1;\n+\tstruct cvmx_sso_grpx_pri_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_grpx_pri cvmx_sso_grpx_pri_t;\n+\n+/**\n+ * cvmx_sso_grp#_taq_thr\n+ *\n+ * These registers contain the thresholds for allocating SSO transitory admission queue storage\n+ * buffers, see Transitory-Admission Thresholds.\n+ */\n+union cvmx_sso_grpx_taq_thr {\n+\tu64 u64;\n+\tstruct cvmx_sso_grpx_taq_thr_s {\n+\t\tu64 reserved_59_63 : 5;\n+\t\tu64 grp_cnt : 11;\n+\t\tu64 reserved_43_47 : 5;\n+\t\tu64 max_thr : 11;\n+\t\tu64 reserved_11_31 : 21;\n+\t\tu64 rsvd_thr : 11;\n+\t} s;\n+\tstruct cvmx_sso_grpx_taq_thr_s cn73xx;\n+\tstruct cvmx_sso_grpx_taq_thr_s cn78xx;\n+\tstruct cvmx_sso_grpx_taq_thr_s cn78xxp1;\n+\tstruct cvmx_sso_grpx_taq_thr_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_grpx_taq_thr cvmx_sso_grpx_taq_thr_t;\n+\n+/**\n+ * cvmx_sso_grp#_ts_pc\n+ *\n+ * Counts the number of tag switch requests for each group being switched to. Counter rolls over\n+ * through zero when max value exceeded.\n+ */\n+union cvmx_sso_grpx_ts_pc {\n+\tu64 u64;\n+\tstruct cvmx_sso_grpx_ts_pc_s {\n+\t\tu64 cnt : 64;\n+\t} s;\n+\tstruct cvmx_sso_grpx_ts_pc_s cn73xx;\n+\tstruct cvmx_sso_grpx_ts_pc_s cn78xx;\n+\tstruct cvmx_sso_grpx_ts_pc_s cn78xxp1;\n+\tstruct cvmx_sso_grpx_ts_pc_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_grpx_ts_pc cvmx_sso_grpx_ts_pc_t;\n+\n+/**\n+ * cvmx_sso_grp#_wa_pc\n+ *\n+ * Counts the number of add new work requests for each group. The counter rolls over through zero\n+ * when the max value exceeded.\n+ */\n+union cvmx_sso_grpx_wa_pc {\n+\tu64 u64;\n+\tstruct cvmx_sso_grpx_wa_pc_s {\n+\t\tu64 cnt : 64;\n+\t} s;\n+\tstruct cvmx_sso_grpx_wa_pc_s cn73xx;\n+\tstruct cvmx_sso_grpx_wa_pc_s cn78xx;\n+\tstruct cvmx_sso_grpx_wa_pc_s cn78xxp1;\n+\tstruct cvmx_sso_grpx_wa_pc_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_grpx_wa_pc cvmx_sso_grpx_wa_pc_t;\n+\n+/**\n+ * cvmx_sso_grp#_ws_pc\n+ *\n+ * Counts the number of work schedules for each group. The counter rolls over through zero when\n+ * the maximum value is exceeded.\n+ */\n+union cvmx_sso_grpx_ws_pc {\n+\tu64 u64;\n+\tstruct cvmx_sso_grpx_ws_pc_s {\n+\t\tu64 cnt : 64;\n+\t} s;\n+\tstruct cvmx_sso_grpx_ws_pc_s cn73xx;\n+\tstruct cvmx_sso_grpx_ws_pc_s cn78xx;\n+\tstruct cvmx_sso_grpx_ws_pc_s cn78xxp1;\n+\tstruct cvmx_sso_grpx_ws_pc_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_grpx_ws_pc cvmx_sso_grpx_ws_pc_t;\n+\n+/**\n+ * cvmx_sso_gw_eco\n+ */\n+union cvmx_sso_gw_eco {\n+\tu64 u64;\n+\tstruct cvmx_sso_gw_eco_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 eco_rw : 8;\n+\t} s;\n+\tstruct cvmx_sso_gw_eco_s cn73xx;\n+\tstruct cvmx_sso_gw_eco_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_gw_eco cvmx_sso_gw_eco_t;\n+\n+/**\n+ * cvmx_sso_gwe_cfg\n+ *\n+ * This register controls the operation of the get-work examiner (GWE).\n+ *\n+ */\n+union cvmx_sso_gwe_cfg {\n+\tu64 u64;\n+\tstruct cvmx_sso_gwe_cfg_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 odu_ffpgw_dis : 1;\n+\t\tu64 gwe_rfpgw_dis : 1;\n+\t\tu64 odu_prf_dis : 1;\n+\t\tu64 reserved_0_8 : 9;\n+\t} s;\n+\tstruct cvmx_sso_gwe_cfg_cn68xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 odu_ffpgw_dis : 1;\n+\t\tu64 gwe_rfpgw_dis : 1;\n+\t\tu64 odu_prf_dis : 1;\n+\t\tu64 odu_bmp_dis : 1;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 gwe_hvy_dis : 1;\n+\t\tu64 gwe_poe : 1;\n+\t\tu64 gwe_fpor : 1;\n+\t\tu64 gwe_rah : 1;\n+\t\tu64 gwe_dis : 1;\n+\t} cn68xx;\n+\tstruct cvmx_sso_gwe_cfg_cn68xxp1 {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 gwe_poe : 1;\n+\t\tu64 gwe_fpor : 1;\n+\t\tu64 gwe_rah : 1;\n+\t\tu64 gwe_dis : 1;\n+\t} cn68xxp1;\n+\tstruct cvmx_sso_gwe_cfg_cn73xx {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 dis_wgt_credit : 1;\n+\t\tu64 ws_retries : 8;\n+\t} cn73xx;\n+\tstruct cvmx_sso_gwe_cfg_cn73xx cn78xx;\n+\tstruct cvmx_sso_gwe_cfg_cn73xx cn78xxp1;\n+\tstruct cvmx_sso_gwe_cfg_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sso_gwe_cfg cvmx_sso_gwe_cfg_t;\n+\n+/**\n+ * cvmx_sso_gwe_random\n+ *\n+ * This register contains the random search start position for the get-work examiner (GWE).\n+ *\n+ */\n+union cvmx_sso_gwe_random {\n+\tu64 u64;\n+\tstruct cvmx_sso_gwe_random_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 rnd : 16;\n+\t} s;\n+\tstruct cvmx_sso_gwe_random_s cn73xx;\n+\tstruct cvmx_sso_gwe_random_s cn78xx;\n+\tstruct cvmx_sso_gwe_random_s cn78xxp1;\n+\tstruct cvmx_sso_gwe_random_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_gwe_random cvmx_sso_gwe_random_t;\n+\n+/**\n+ * cvmx_sso_idx_ecc_ctl\n+ *\n+ * SSO_IDX_ECC_CTL = SSO IDX ECC Control\n+ *\n+ */\n+union cvmx_sso_idx_ecc_ctl {\n+\tu64 u64;\n+\tstruct cvmx_sso_idx_ecc_ctl_s {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 flip_synd : 2;\n+\t\tu64 ecc_ena : 1;\n+\t} s;\n+\tstruct cvmx_sso_idx_ecc_ctl_s cn68xx;\n+\tstruct cvmx_sso_idx_ecc_ctl_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_idx_ecc_ctl cvmx_sso_idx_ecc_ctl_t;\n+\n+/**\n+ * cvmx_sso_idx_ecc_st\n+ *\n+ * SSO_IDX_ECC_ST = SSO IDX ECC Status\n+ *\n+ */\n+union cvmx_sso_idx_ecc_st {\n+\tu64 u64;\n+\tstruct cvmx_sso_idx_ecc_st_s {\n+\t\tu64 reserved_27_63 : 37;\n+\t\tu64 addr : 11;\n+\t\tu64 reserved_9_15 : 7;\n+\t\tu64 syndrom : 5;\n+\t\tu64 reserved_0_3 : 4;\n+\t} s;\n+\tstruct cvmx_sso_idx_ecc_st_s cn68xx;\n+\tstruct cvmx_sso_idx_ecc_st_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_idx_ecc_st cvmx_sso_idx_ecc_st_t;\n+\n+/**\n+ * cvmx_sso_ient#_links\n+ *\n+ * Returns unit memory status for an index.\n+ *\n+ */\n+union cvmx_sso_ientx_links {\n+\tu64 u64;\n+\tstruct cvmx_sso_ientx_links_s {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 prev_index : 12;\n+\t\tu64 reserved_0_15 : 16;\n+\t} s;\n+\tstruct cvmx_sso_ientx_links_cn73xx {\n+\t\tu64 reserved_26_63 : 38;\n+\t\tu64 prev_index : 10;\n+\t\tu64 reserved_11_15 : 5;\n+\t\tu64 next_index_vld : 1;\n+\t\tu64 next_index : 10;\n+\t} cn73xx;\n+\tstruct cvmx_sso_ientx_links_cn78xx {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 prev_index : 12;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 next_index_vld : 1;\n+\t\tu64 next_index : 12;\n+\t} cn78xx;\n+\tstruct cvmx_sso_ientx_links_cn78xx cn78xxp1;\n+\tstruct cvmx_sso_ientx_links_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ientx_links cvmx_sso_ientx_links_t;\n+\n+/**\n+ * cvmx_sso_ient#_pendtag\n+ *\n+ * Returns unit memory status for an index.\n+ *\n+ */\n+union cvmx_sso_ientx_pendtag {\n+\tu64 u64;\n+\tstruct cvmx_sso_ientx_pendtag_s {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 pend_switch : 1;\n+\t\tu64 reserved_34_36 : 3;\n+\t\tu64 pend_tt : 2;\n+\t\tu64 pend_tag : 32;\n+\t} s;\n+\tstruct cvmx_sso_ientx_pendtag_s cn73xx;\n+\tstruct cvmx_sso_ientx_pendtag_s cn78xx;\n+\tstruct cvmx_sso_ientx_pendtag_s cn78xxp1;\n+\tstruct cvmx_sso_ientx_pendtag_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ientx_pendtag cvmx_sso_ientx_pendtag_t;\n+\n+/**\n+ * cvmx_sso_ient#_qlinks\n+ *\n+ * Returns unit memory status for an index.\n+ *\n+ */\n+union cvmx_sso_ientx_qlinks {\n+\tu64 u64;\n+\tstruct cvmx_sso_ientx_qlinks_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 next_index : 12;\n+\t} s;\n+\tstruct cvmx_sso_ientx_qlinks_s cn73xx;\n+\tstruct cvmx_sso_ientx_qlinks_s cn78xx;\n+\tstruct cvmx_sso_ientx_qlinks_s cn78xxp1;\n+\tstruct cvmx_sso_ientx_qlinks_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ientx_qlinks cvmx_sso_ientx_qlinks_t;\n+\n+/**\n+ * cvmx_sso_ient#_tag\n+ *\n+ * Returns unit memory status for an index.\n+ *\n+ */\n+union cvmx_sso_ientx_tag {\n+\tu64 u64;\n+\tstruct cvmx_sso_ientx_tag_s {\n+\t\tu64 reserved_39_63 : 25;\n+\t\tu64 tailc : 1;\n+\t\tu64 tail : 1;\n+\t\tu64 reserved_34_36 : 3;\n+\t\tu64 tt : 2;\n+\t\tu64 tag : 32;\n+\t} s;\n+\tstruct cvmx_sso_ientx_tag_s cn73xx;\n+\tstruct cvmx_sso_ientx_tag_s cn78xx;\n+\tstruct cvmx_sso_ientx_tag_s cn78xxp1;\n+\tstruct cvmx_sso_ientx_tag_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ientx_tag cvmx_sso_ientx_tag_t;\n+\n+/**\n+ * cvmx_sso_ient#_wqpgrp\n+ *\n+ * Returns unit memory status for an index.\n+ *\n+ */\n+union cvmx_sso_ientx_wqpgrp {\n+\tu64 u64;\n+\tstruct cvmx_sso_ientx_wqpgrp_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 head : 1;\n+\t\tu64 nosched : 1;\n+\t\tu64 reserved_58_59 : 2;\n+\t\tu64 grp : 10;\n+\t\tu64 reserved_42_47 : 6;\n+\t\tu64 wqp : 42;\n+\t} s;\n+\tstruct cvmx_sso_ientx_wqpgrp_cn73xx {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 head : 1;\n+\t\tu64 nosched : 1;\n+\t\tu64 reserved_56_59 : 4;\n+\t\tu64 grp : 8;\n+\t\tu64 reserved_42_47 : 6;\n+\t\tu64 wqp : 42;\n+\t} cn73xx;\n+\tstruct cvmx_sso_ientx_wqpgrp_s cn78xx;\n+\tstruct cvmx_sso_ientx_wqpgrp_s cn78xxp1;\n+\tstruct cvmx_sso_ientx_wqpgrp_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ientx_wqpgrp cvmx_sso_ientx_wqpgrp_t;\n+\n+/**\n+ * cvmx_sso_ipl_conf#\n+ *\n+ * Returns list status for the conflicted list indexed by group.  Register\n+ * fields are identical to those in SSO_IPL_IAQ() above.\n+ */\n+union cvmx_sso_ipl_confx {\n+\tu64 u64;\n+\tstruct cvmx_sso_ipl_confx_s {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 queue_val : 1;\n+\t\tu64 queue_one : 1;\n+\t\tu64 reserved_25_25 : 1;\n+\t\tu64 queue_head : 12;\n+\t\tu64 reserved_12_12 : 1;\n+\t\tu64 queue_tail : 12;\n+\t} s;\n+\tstruct cvmx_sso_ipl_confx_s cn73xx;\n+\tstruct cvmx_sso_ipl_confx_s cn78xx;\n+\tstruct cvmx_sso_ipl_confx_s cn78xxp1;\n+\tstruct cvmx_sso_ipl_confx_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ipl_confx cvmx_sso_ipl_confx_t;\n+\n+/**\n+ * cvmx_sso_ipl_desched#\n+ *\n+ * Returns list status for the deschedule list indexed by group.  Register\n+ * fields are identical to those in SSO_IPL_IAQ() above.\n+ */\n+union cvmx_sso_ipl_deschedx {\n+\tu64 u64;\n+\tstruct cvmx_sso_ipl_deschedx_s {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 queue_val : 1;\n+\t\tu64 queue_one : 1;\n+\t\tu64 reserved_25_25 : 1;\n+\t\tu64 queue_head : 12;\n+\t\tu64 reserved_12_12 : 1;\n+\t\tu64 queue_tail : 12;\n+\t} s;\n+\tstruct cvmx_sso_ipl_deschedx_s cn73xx;\n+\tstruct cvmx_sso_ipl_deschedx_s cn78xx;\n+\tstruct cvmx_sso_ipl_deschedx_s cn78xxp1;\n+\tstruct cvmx_sso_ipl_deschedx_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ipl_deschedx cvmx_sso_ipl_deschedx_t;\n+\n+/**\n+ * cvmx_sso_ipl_free#\n+ *\n+ * Returns list status.\n+ *\n+ */\n+union cvmx_sso_ipl_freex {\n+\tu64 u64;\n+\tstruct cvmx_sso_ipl_freex_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 qnum_head : 3;\n+\t\tu64 qnum_tail : 3;\n+\t\tu64 reserved_28_55 : 28;\n+\t\tu64 queue_val : 1;\n+\t\tu64 reserved_25_26 : 2;\n+\t\tu64 queue_head : 12;\n+\t\tu64 reserved_12_12 : 1;\n+\t\tu64 queue_tail : 12;\n+\t} s;\n+\tstruct cvmx_sso_ipl_freex_cn73xx {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 qnum_head : 3;\n+\t\tu64 qnum_tail : 3;\n+\t\tu64 reserved_28_55 : 28;\n+\t\tu64 queue_val : 1;\n+\t\tu64 reserved_23_26 : 4;\n+\t\tu64 queue_head : 10;\n+\t\tu64 reserved_10_12 : 3;\n+\t\tu64 queue_tail : 10;\n+\t} cn73xx;\n+\tstruct cvmx_sso_ipl_freex_s cn78xx;\n+\tstruct cvmx_sso_ipl_freex_s cn78xxp1;\n+\tstruct cvmx_sso_ipl_freex_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ipl_freex cvmx_sso_ipl_freex_t;\n+\n+/**\n+ * cvmx_sso_ipl_iaq#\n+ *\n+ * Returns list status for the internal admission queue indexed by group.\n+ *\n+ */\n+union cvmx_sso_ipl_iaqx {\n+\tu64 u64;\n+\tstruct cvmx_sso_ipl_iaqx_s {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 queue_val : 1;\n+\t\tu64 queue_one : 1;\n+\t\tu64 reserved_25_25 : 1;\n+\t\tu64 queue_head : 12;\n+\t\tu64 reserved_12_12 : 1;\n+\t\tu64 queue_tail : 12;\n+\t} s;\n+\tstruct cvmx_sso_ipl_iaqx_s cn73xx;\n+\tstruct cvmx_sso_ipl_iaqx_s cn78xx;\n+\tstruct cvmx_sso_ipl_iaqx_s cn78xxp1;\n+\tstruct cvmx_sso_ipl_iaqx_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ipl_iaqx cvmx_sso_ipl_iaqx_t;\n+\n+/**\n+ * cvmx_sso_iq_cnt#\n+ *\n+ * CSR reserved addresses: (64): 0x8200..0x83f8\n+ * CSR align addresses: ===========================================================================================================\n+ * SSO_IQ_CNTX = SSO Input Queue Count Register\n+ *               (one per QOS level)\n+ *\n+ * Contains a read-only count of the number of work queue entries for each QOS\n+ * level. Counts both in-unit and in-memory entries.\n+ */\n+union cvmx_sso_iq_cntx {\n+\tu64 u64;\n+\tstruct cvmx_sso_iq_cntx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 iq_cnt : 32;\n+\t} s;\n+\tstruct cvmx_sso_iq_cntx_s cn68xx;\n+\tstruct cvmx_sso_iq_cntx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_iq_cntx cvmx_sso_iq_cntx_t;\n+\n+/**\n+ * cvmx_sso_iq_com_cnt\n+ *\n+ * SSO_IQ_COM_CNT = SSO Input Queue Combined Count Register\n+ *\n+ * Contains a read-only count of the total number of work queue entries in all\n+ * QOS levels.  Counts both in-unit and in-memory entries.\n+ */\n+union cvmx_sso_iq_com_cnt {\n+\tu64 u64;\n+\tstruct cvmx_sso_iq_com_cnt_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 iq_cnt : 32;\n+\t} s;\n+\tstruct cvmx_sso_iq_com_cnt_s cn68xx;\n+\tstruct cvmx_sso_iq_com_cnt_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_iq_com_cnt cvmx_sso_iq_com_cnt_t;\n+\n+/**\n+ * cvmx_sso_iq_int\n+ *\n+ * SSO_IQ_INT = SSO Input Queue Interrupt Register\n+ *\n+ * Contains the bits (one per QOS level) that can trigger the input queue\n+ * interrupt.  An IQ_INT bit will be set if SSO_IQ_CNT#QOS# changes and the\n+ * resulting value is equal to SSO_IQ_THR#QOS#.\n+ */\n+union cvmx_sso_iq_int {\n+\tu64 u64;\n+\tstruct cvmx_sso_iq_int_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 iq_int : 8;\n+\t} s;\n+\tstruct cvmx_sso_iq_int_s cn68xx;\n+\tstruct cvmx_sso_iq_int_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_iq_int cvmx_sso_iq_int_t;\n+\n+/**\n+ * cvmx_sso_iq_int_en\n+ *\n+ * SSO_IQ_INT_EN = SSO Input Queue Interrupt Enable Register\n+ *\n+ * Contains the bits (one per QOS level) that enable the input queue interrupt.\n+ */\n+union cvmx_sso_iq_int_en {\n+\tu64 u64;\n+\tstruct cvmx_sso_iq_int_en_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 int_en : 8;\n+\t} s;\n+\tstruct cvmx_sso_iq_int_en_s cn68xx;\n+\tstruct cvmx_sso_iq_int_en_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_iq_int_en cvmx_sso_iq_int_en_t;\n+\n+/**\n+ * cvmx_sso_iq_thr#\n+ *\n+ * CSR reserved addresses: (24): 0x9040..0x90f8\n+ * CSR align addresses: ===========================================================================================================\n+ * SSO_IQ_THRX = SSO Input Queue Threshold Register\n+ *               (one per QOS level)\n+ *\n+ * Threshold value for triggering input queue interrupts.\n+ */\n+union cvmx_sso_iq_thrx {\n+\tu64 u64;\n+\tstruct cvmx_sso_iq_thrx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 iq_thr : 32;\n+\t} s;\n+\tstruct cvmx_sso_iq_thrx_s cn68xx;\n+\tstruct cvmx_sso_iq_thrx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_iq_thrx cvmx_sso_iq_thrx_t;\n+\n+/**\n+ * cvmx_sso_nos_cnt\n+ *\n+ * Contains the number of work-queue entries on the no-schedule list.\n+ *\n+ */\n+union cvmx_sso_nos_cnt {\n+\tu64 u64;\n+\tstruct cvmx_sso_nos_cnt_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 nos_cnt : 13;\n+\t} s;\n+\tstruct cvmx_sso_nos_cnt_cn68xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 nos_cnt : 12;\n+\t} cn68xx;\n+\tstruct cvmx_sso_nos_cnt_cn68xx cn68xxp1;\n+\tstruct cvmx_sso_nos_cnt_s cn73xx;\n+\tstruct cvmx_sso_nos_cnt_s cn78xx;\n+\tstruct cvmx_sso_nos_cnt_s cn78xxp1;\n+\tstruct cvmx_sso_nos_cnt_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_nos_cnt cvmx_sso_nos_cnt_t;\n+\n+/**\n+ * cvmx_sso_nw_tim\n+ *\n+ * Sets the minimum period for a new-work-request timeout. The period is specified in n-1\n+ * notation, with the increment value of 1024 clock cycles. Thus, a value of 0x0 in this register\n+ * translates to 1024 cycles, 0x1 translates to 2048 cycles, 0x2 translates to 3072 cycles, etc.\n+ */\n+union cvmx_sso_nw_tim {\n+\tu64 u64;\n+\tstruct cvmx_sso_nw_tim_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 nw_tim : 10;\n+\t} s;\n+\tstruct cvmx_sso_nw_tim_s cn68xx;\n+\tstruct cvmx_sso_nw_tim_s cn68xxp1;\n+\tstruct cvmx_sso_nw_tim_s cn73xx;\n+\tstruct cvmx_sso_nw_tim_s cn78xx;\n+\tstruct cvmx_sso_nw_tim_s cn78xxp1;\n+\tstruct cvmx_sso_nw_tim_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_nw_tim cvmx_sso_nw_tim_t;\n+\n+/**\n+ * cvmx_sso_oth_ecc_ctl\n+ *\n+ * SSO_OTH_ECC_CTL = SSO OTH ECC Control\n+ *\n+ */\n+union cvmx_sso_oth_ecc_ctl {\n+\tu64 u64;\n+\tstruct cvmx_sso_oth_ecc_ctl_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 flip_synd1 : 2;\n+\t\tu64 ecc_ena1 : 1;\n+\t\tu64 flip_synd0 : 2;\n+\t\tu64 ecc_ena0 : 1;\n+\t} s;\n+\tstruct cvmx_sso_oth_ecc_ctl_s cn68xx;\n+\tstruct cvmx_sso_oth_ecc_ctl_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_oth_ecc_ctl cvmx_sso_oth_ecc_ctl_t;\n+\n+/**\n+ * cvmx_sso_oth_ecc_st\n+ *\n+ * SSO_OTH_ECC_ST = SSO OTH ECC Status\n+ *\n+ */\n+union cvmx_sso_oth_ecc_st {\n+\tu64 u64;\n+\tstruct cvmx_sso_oth_ecc_st_s {\n+\t\tu64 reserved_59_63 : 5;\n+\t\tu64 addr1 : 11;\n+\t\tu64 reserved_43_47 : 5;\n+\t\tu64 syndrom1 : 7;\n+\t\tu64 reserved_27_35 : 9;\n+\t\tu64 addr0 : 11;\n+\t\tu64 reserved_11_15 : 5;\n+\t\tu64 syndrom0 : 7;\n+\t\tu64 reserved_0_3 : 4;\n+\t} s;\n+\tstruct cvmx_sso_oth_ecc_st_s cn68xx;\n+\tstruct cvmx_sso_oth_ecc_st_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_oth_ecc_st cvmx_sso_oth_ecc_st_t;\n+\n+/**\n+ * cvmx_sso_page_cnt\n+ */\n+union cvmx_sso_page_cnt {\n+\tu64 u64;\n+\tstruct cvmx_sso_page_cnt_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_sso_page_cnt_s cn73xx;\n+\tstruct cvmx_sso_page_cnt_s cn78xx;\n+\tstruct cvmx_sso_page_cnt_s cn78xxp1;\n+\tstruct cvmx_sso_page_cnt_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_page_cnt cvmx_sso_page_cnt_t;\n+\n+/**\n+ * cvmx_sso_pnd_ecc_ctl\n+ *\n+ * SSO_PND_ECC_CTL = SSO PND ECC Control\n+ *\n+ */\n+union cvmx_sso_pnd_ecc_ctl {\n+\tu64 u64;\n+\tstruct cvmx_sso_pnd_ecc_ctl_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 flip_synd1 : 2;\n+\t\tu64 ecc_ena1 : 1;\n+\t\tu64 flip_synd0 : 2;\n+\t\tu64 ecc_ena0 : 1;\n+\t} s;\n+\tstruct cvmx_sso_pnd_ecc_ctl_s cn68xx;\n+\tstruct cvmx_sso_pnd_ecc_ctl_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_pnd_ecc_ctl cvmx_sso_pnd_ecc_ctl_t;\n+\n+/**\n+ * cvmx_sso_pnd_ecc_st\n+ *\n+ * SSO_PND_ECC_ST = SSO PND ECC Status\n+ *\n+ */\n+union cvmx_sso_pnd_ecc_st {\n+\tu64 u64;\n+\tstruct cvmx_sso_pnd_ecc_st_s {\n+\t\tu64 reserved_59_63 : 5;\n+\t\tu64 addr1 : 11;\n+\t\tu64 reserved_43_47 : 5;\n+\t\tu64 syndrom1 : 7;\n+\t\tu64 reserved_27_35 : 9;\n+\t\tu64 addr0 : 11;\n+\t\tu64 reserved_11_15 : 5;\n+\t\tu64 syndrom0 : 7;\n+\t\tu64 reserved_0_3 : 4;\n+\t} s;\n+\tstruct cvmx_sso_pnd_ecc_st_s cn68xx;\n+\tstruct cvmx_sso_pnd_ecc_st_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_pnd_ecc_st cvmx_sso_pnd_ecc_st_t;\n+\n+/**\n+ * cvmx_sso_pp#_arb\n+ *\n+ * For diagnostic use, returns the group affinity arbitration state for each core.\n+ *\n+ */\n+union cvmx_sso_ppx_arb {\n+\tu64 u64;\n+\tstruct cvmx_sso_ppx_arb_s {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 aff_left : 4;\n+\t\tu64 reserved_8_15 : 8;\n+\t\tu64 last_grp : 8;\n+\t} s;\n+\tstruct cvmx_sso_ppx_arb_s cn73xx;\n+\tstruct cvmx_sso_ppx_arb_s cn78xx;\n+\tstruct cvmx_sso_ppx_arb_s cn78xxp1;\n+\tstruct cvmx_sso_ppx_arb_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ppx_arb cvmx_sso_ppx_arb_t;\n+\n+/**\n+ * cvmx_sso_pp#_grp_msk\n+ *\n+ * CSR reserved addresses: (24): 0x5040..0x50f8\n+ * CSR align addresses: ===========================================================================================================\n+ * SSO_PPX_GRP_MSK = SSO PP Group Mask Register\n+ *                   (one bit per group per PP)\n+ *\n+ * Selects which group(s) a PP belongs to.  A '1' in any bit position sets the\n+ * PP's membership in the corresponding group.  A value of 0x0 will prevent the\n+ * PP from receiving new work.\n+ *\n+ * Note that these do not contain QOS level priorities for each PP.  This is a\n+ * change from previous POW designs.\n+ */\n+union cvmx_sso_ppx_grp_msk {\n+\tu64 u64;\n+\tstruct cvmx_sso_ppx_grp_msk_s {\n+\t\tu64 grp_msk : 64;\n+\t} s;\n+\tstruct cvmx_sso_ppx_grp_msk_s cn68xx;\n+\tstruct cvmx_sso_ppx_grp_msk_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_ppx_grp_msk cvmx_sso_ppx_grp_msk_t;\n+\n+/**\n+ * cvmx_sso_pp#_qos_pri\n+ *\n+ * CSR reserved addresses: (56): 0x2040..0x21f8\n+ * CSR align addresses: ===========================================================================================================\n+ * SSO_PP(0..31)_QOS_PRI = SSO PP QOS Priority Register\n+ *                                (one field per IQ per PP)\n+ *\n+ * Contains the QOS level priorities for each PP.\n+ *      0x0       is the highest priority\n+ *      0x7       is the lowest priority\n+ *      0xf       prevents the PP from receiving work from that QOS level\n+ *      0x8-0xe   Reserved\n+ *\n+ * For a given PP, priorities should begin at 0x0, and remain contiguous\n+ * throughout the range.  Failure to do so may result in severe\n+ * performance degradation.\n+ *\n+ *\n+ * Priorities for IQs 0..7\n+ */\n+union cvmx_sso_ppx_qos_pri {\n+\tu64 u64;\n+\tstruct cvmx_sso_ppx_qos_pri_s {\n+\t\tu64 reserved_60_63 : 4;\n+\t\tu64 qos7_pri : 4;\n+\t\tu64 reserved_52_55 : 4;\n+\t\tu64 qos6_pri : 4;\n+\t\tu64 reserved_44_47 : 4;\n+\t\tu64 qos5_pri : 4;\n+\t\tu64 reserved_36_39 : 4;\n+\t\tu64 qos4_pri : 4;\n+\t\tu64 reserved_28_31 : 4;\n+\t\tu64 qos3_pri : 4;\n+\t\tu64 reserved_20_23 : 4;\n+\t\tu64 qos2_pri : 4;\n+\t\tu64 reserved_12_15 : 4;\n+\t\tu64 qos1_pri : 4;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 qos0_pri : 4;\n+\t} s;\n+\tstruct cvmx_sso_ppx_qos_pri_s cn68xx;\n+\tstruct cvmx_sso_ppx_qos_pri_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_ppx_qos_pri cvmx_sso_ppx_qos_pri_t;\n+\n+/**\n+ * cvmx_sso_pp#_s#_grpmsk#\n+ *\n+ * These registers select which group or groups a core belongs to. There are 2 sets of masks per\n+ * core, each with 1 register corresponding to 64 groups.\n+ */\n+union cvmx_sso_ppx_sx_grpmskx {\n+\tu64 u64;\n+\tstruct cvmx_sso_ppx_sx_grpmskx_s {\n+\t\tu64 grp_msk : 64;\n+\t} s;\n+\tstruct cvmx_sso_ppx_sx_grpmskx_s cn73xx;\n+\tstruct cvmx_sso_ppx_sx_grpmskx_s cn78xx;\n+\tstruct cvmx_sso_ppx_sx_grpmskx_s cn78xxp1;\n+\tstruct cvmx_sso_ppx_sx_grpmskx_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ppx_sx_grpmskx cvmx_sso_ppx_sx_grpmskx_t;\n+\n+/**\n+ * cvmx_sso_pp_strict\n+ *\n+ * SSO_PP_STRICT = SSO Strict Priority\n+ *\n+ * This register controls getting work from the input queues.  If the bit\n+ * corresponding to a PP is set, that PP will not take work off the input\n+ * queues until it is known that there is no higher-priority work available.\n+ *\n+ * Setting SSO_PP_STRICT may incur a performance penalty if highest-priority\n+ * work is not found early.\n+ *\n+ * It is possible to starve a PP of work with SSO_PP_STRICT.  If the\n+ * SSO_PPX_GRP_MSK for a PP masks-out much of the work added to the input\n+ * queues that are higher-priority for that PP, and if there is a constant\n+ * stream of work through one or more of those higher-priority input queues,\n+ * then that PP may not accept work from lower-priority input queues.  This can\n+ * be alleviated by ensuring that most or all the work added to the\n+ * higher-priority input queues for a PP with SSO_PP_STRICT set are in a group\n+ * acceptable to that PP.\n+ *\n+ * It is also possible to neglect work in an input queue if SSO_PP_STRICT is\n+ * used.  If an input queue is a lower-priority queue for all PPs, and if all\n+ * the PPs have their corresponding bit in SSO_PP_STRICT set, then work may\n+ * never be taken (or be seldom taken) from that queue.  This can be alleviated\n+ * by ensuring that work in all input queues can be serviced by one or more PPs\n+ * that do not have SSO_PP_STRICT set, or that the input queue is the\n+ * highest-priority input queue for one or more PPs that do have SSO_PP_STRICT\n+ * set.\n+ */\n+union cvmx_sso_pp_strict {\n+\tu64 u64;\n+\tstruct cvmx_sso_pp_strict_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 pp_strict : 32;\n+\t} s;\n+\tstruct cvmx_sso_pp_strict_s cn68xx;\n+\tstruct cvmx_sso_pp_strict_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_pp_strict cvmx_sso_pp_strict_t;\n+\n+/**\n+ * cvmx_sso_qos#_rnd\n+ *\n+ * CSR align addresses: ===========================================================================================================\n+ * SSO_QOS(0..7)_RND = SSO QOS Issue Round Register\n+ *                (one per IQ)\n+ *\n+ * The number of arbitration rounds each QOS level participates in.\n+ */\n+union cvmx_sso_qosx_rnd {\n+\tu64 u64;\n+\tstruct cvmx_sso_qosx_rnd_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 rnds_qos : 8;\n+\t} s;\n+\tstruct cvmx_sso_qosx_rnd_s cn68xx;\n+\tstruct cvmx_sso_qosx_rnd_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_qosx_rnd cvmx_sso_qosx_rnd_t;\n+\n+/**\n+ * cvmx_sso_qos_thr#\n+ *\n+ * CSR reserved addresses: (24): 0xa040..0xa0f8\n+ * CSR align addresses: ===========================================================================================================\n+ * SSO_QOS_THRX = SSO QOS Threshold Register\n+ *                (one per QOS level)\n+ *\n+ * Contains the thresholds for allocating SSO internal storage buffers.  If the\n+ * number of remaining free buffers drops below the minimum threshold (MIN_THR)\n+ * or the number of allocated buffers for this QOS level rises above the\n+ * maximum threshold (MAX_THR), future incoming work queue entries will be\n+ * buffered externally rather than internally.  This register also contains the\n+ * number of internal buffers currently allocated to this QOS level (BUF_CNT).\n+ */\n+union cvmx_sso_qos_thrx {\n+\tu64 u64;\n+\tstruct cvmx_sso_qos_thrx_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 buf_cnt : 12;\n+\t\tu64 reserved_26_27 : 2;\n+\t\tu64 max_thr : 12;\n+\t\tu64 reserved_12_13 : 2;\n+\t\tu64 min_thr : 12;\n+\t} s;\n+\tstruct cvmx_sso_qos_thrx_s cn68xx;\n+\tstruct cvmx_sso_qos_thrx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_qos_thrx cvmx_sso_qos_thrx_t;\n+\n+/**\n+ * cvmx_sso_qos_we\n+ *\n+ * SSO_QOS_WE = SSO WE Buffers\n+ *\n+ * This register contains a read-only count of the current number of free\n+ * buffers (FREE_CNT) and the total number of tag chain heads on the de-schedule list\n+ * (DES_CNT) (which is not the same as the total number of entries on all of the descheduled\n+ * tag chains.)\n+ */\n+union cvmx_sso_qos_we {\n+\tu64 u64;\n+\tstruct cvmx_sso_qos_we_s {\n+\t\tu64 reserved_26_63 : 38;\n+\t\tu64 des_cnt : 12;\n+\t\tu64 reserved_12_13 : 2;\n+\t\tu64 free_cnt : 12;\n+\t} s;\n+\tstruct cvmx_sso_qos_we_s cn68xx;\n+\tstruct cvmx_sso_qos_we_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_qos_we cvmx_sso_qos_we_t;\n+\n+/**\n+ * cvmx_sso_reset\n+ *\n+ * Writing a 1 to SSO_RESET[RESET] resets the SSO. After receiving a store to this CSR, the SSO\n+ * must not be sent any other operations for 2500 coprocessor (SCLK) cycles. Note that the\n+ * contents of this register are reset along with the rest of the SSO.\n+ */\n+union cvmx_sso_reset {\n+\tu64 u64;\n+\tstruct cvmx_sso_reset_s {\n+\t\tu64 busy : 1;\n+\t\tu64 reserved_1_62 : 62;\n+\t\tu64 reset : 1;\n+\t} s;\n+\tstruct cvmx_sso_reset_cn68xx {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 reset : 1;\n+\t} cn68xx;\n+\tstruct cvmx_sso_reset_s cn73xx;\n+\tstruct cvmx_sso_reset_s cn78xx;\n+\tstruct cvmx_sso_reset_s cn78xxp1;\n+\tstruct cvmx_sso_reset_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_reset cvmx_sso_reset_t;\n+\n+/**\n+ * cvmx_sso_rwq_head_ptr#\n+ *\n+ * CSR reserved addresses: (24): 0xb040..0xb0f8\n+ * CSR align addresses: ===========================================================================================================\n+ * SSO_RWQ_HEAD_PTRX = SSO Remote Queue Head Register\n+ *                (one per QOS level)\n+ * Contains the ptr to the first entry of the remote linked list(s) for a particular\n+ * QoS level. SW should initialize the remote linked list(s) by programming\n+ * SSO_RWQ_HEAD_PTRX and SSO_RWQ_TAIL_PTRX to identical values.\n+ */\n+union cvmx_sso_rwq_head_ptrx {\n+\tu64 u64;\n+\tstruct cvmx_sso_rwq_head_ptrx_s {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 ptr : 31;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 rctr : 5;\n+\t} s;\n+\tstruct cvmx_sso_rwq_head_ptrx_s cn68xx;\n+\tstruct cvmx_sso_rwq_head_ptrx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_rwq_head_ptrx cvmx_sso_rwq_head_ptrx_t;\n+\n+/**\n+ * cvmx_sso_rwq_pop_fptr\n+ *\n+ * SSO_RWQ_POP_FPTR = SSO Pop Free Pointer\n+ *\n+ * This register is used by SW to remove pointers for buffer-reallocation and diagnostics, and\n+ * should only be used when SSO is idle.\n+ *\n+ * To remove ALL pointers, software must insure that there are modulus 16\n+ * pointers in the FPA.  To do this, SSO_CFG.RWQ_BYP_DIS must be set, the FPA\n+ * pointer count read, and enough fake buffers pushed via SSO_RWQ_PSH_FPTR to\n+ * bring the FPA pointer count up to mod 16.\n+ */\n+union cvmx_sso_rwq_pop_fptr {\n+\tu64 u64;\n+\tstruct cvmx_sso_rwq_pop_fptr_s {\n+\t\tu64 val : 1;\n+\t\tu64 reserved_38_62 : 25;\n+\t\tu64 fptr : 31;\n+\t\tu64 reserved_0_6 : 7;\n+\t} s;\n+\tstruct cvmx_sso_rwq_pop_fptr_s cn68xx;\n+\tstruct cvmx_sso_rwq_pop_fptr_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_rwq_pop_fptr cvmx_sso_rwq_pop_fptr_t;\n+\n+/**\n+ * cvmx_sso_rwq_psh_fptr\n+ *\n+ * CSR reserved addresses: (56): 0xc240..0xc3f8\n+ * SSO_RWQ_PSH_FPTR = SSO Free Pointer FIFO\n+ *\n+ * This register is used by SW to initialize the SSO with a pool of free\n+ * pointers by writing the FPTR field whenever FULL = 0. Free pointers are\n+ * fetched/released from/to the pool when accessing WQE entries stored remotely\n+ * (in remote linked lists).  Free pointers should be 128 byte aligned, each of\n+ * 256 bytes. This register should only be used when SSO is idle.\n+ *\n+ * Software needs to set aside buffering for\n+ *      8 + 48 + ROUNDUP(N/26)\n+ *\n+ * where as many as N DRAM work queue entries may be used.  The first 8 buffers\n+ * are used to setup the SSO_RWQ_HEAD_PTR and SSO_RWQ_TAIL_PTRs, and the\n+ * remainder are pushed via this register.\n+ *\n+ * IMPLEMENTATION NOTES--NOT FOR SPEC:\n+ *      48 avoids false out of buffer error due to (16) FPA and in-sso FPA buffering (32)\n+ *      26 is number of WAE's per 256B buffer\n+ */\n+union cvmx_sso_rwq_psh_fptr {\n+\tu64 u64;\n+\tstruct cvmx_sso_rwq_psh_fptr_s {\n+\t\tu64 full : 1;\n+\t\tu64 reserved_38_62 : 25;\n+\t\tu64 fptr : 31;\n+\t\tu64 reserved_0_6 : 7;\n+\t} s;\n+\tstruct cvmx_sso_rwq_psh_fptr_s cn68xx;\n+\tstruct cvmx_sso_rwq_psh_fptr_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_rwq_psh_fptr cvmx_sso_rwq_psh_fptr_t;\n+\n+/**\n+ * cvmx_sso_rwq_tail_ptr#\n+ *\n+ * CSR reserved addresses: (56): 0xc040..0xc1f8\n+ * SSO_RWQ_TAIL_PTRX = SSO Remote Queue Tail Register\n+ *                (one per QOS level)\n+ * Contains the ptr to the last entry of the remote linked list(s) for a particular\n+ * QoS level. SW must initialize the remote linked list(s) by programming\n+ * SSO_RWQ_HEAD_PTRX and SSO_RWQ_TAIL_PTRX to identical values.\n+ */\n+union cvmx_sso_rwq_tail_ptrx {\n+\tu64 u64;\n+\tstruct cvmx_sso_rwq_tail_ptrx_s {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 ptr : 31;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 rctr : 5;\n+\t} s;\n+\tstruct cvmx_sso_rwq_tail_ptrx_s cn68xx;\n+\tstruct cvmx_sso_rwq_tail_ptrx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_rwq_tail_ptrx cvmx_sso_rwq_tail_ptrx_t;\n+\n+/**\n+ * cvmx_sso_sl_pp#_links\n+ *\n+ * Returns status of each core.\n+ *\n+ */\n+union cvmx_sso_sl_ppx_links {\n+\tu64 u64;\n+\tstruct cvmx_sso_sl_ppx_links_s {\n+\t\tu64 tailc : 1;\n+\t\tu64 reserved_60_62 : 3;\n+\t\tu64 index : 12;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 grp : 10;\n+\t\tu64 head : 1;\n+\t\tu64 tail : 1;\n+\t\tu64 reserved_0_25 : 26;\n+\t} s;\n+\tstruct cvmx_sso_sl_ppx_links_cn73xx {\n+\t\tu64 tailc : 1;\n+\t\tu64 reserved_58_62 : 5;\n+\t\tu64 index : 10;\n+\t\tu64 reserved_36_47 : 12;\n+\t\tu64 grp : 8;\n+\t\tu64 head : 1;\n+\t\tu64 tail : 1;\n+\t\tu64 reserved_21_25 : 5;\n+\t\tu64 revlink_index : 10;\n+\t\tu64 link_index_vld : 1;\n+\t\tu64 link_index : 10;\n+\t} cn73xx;\n+\tstruct cvmx_sso_sl_ppx_links_cn78xx {\n+\t\tu64 tailc : 1;\n+\t\tu64 reserved_60_62 : 3;\n+\t\tu64 index : 12;\n+\t\tu64 reserved_38_47 : 10;\n+\t\tu64 grp : 10;\n+\t\tu64 head : 1;\n+\t\tu64 tail : 1;\n+\t\tu64 reserved_25_25 : 1;\n+\t\tu64 revlink_index : 12;\n+\t\tu64 link_index_vld : 1;\n+\t\tu64 link_index : 12;\n+\t} cn78xx;\n+\tstruct cvmx_sso_sl_ppx_links_cn78xx cn78xxp1;\n+\tstruct cvmx_sso_sl_ppx_links_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sso_sl_ppx_links cvmx_sso_sl_ppx_links_t;\n+\n+/**\n+ * cvmx_sso_sl_pp#_pendtag\n+ *\n+ * Returns status of each core.\n+ *\n+ */\n+union cvmx_sso_sl_ppx_pendtag {\n+\tu64 u64;\n+\tstruct cvmx_sso_sl_ppx_pendtag_s {\n+\t\tu64 pend_switch : 1;\n+\t\tu64 pend_get_work : 1;\n+\t\tu64 pend_get_work_wait : 1;\n+\t\tu64 pend_nosched : 1;\n+\t\tu64 pend_nosched_clr : 1;\n+\t\tu64 pend_desched : 1;\n+\t\tu64 pend_alloc_we : 1;\n+\t\tu64 pend_gw_insert : 1;\n+\t\tu64 reserved_34_55 : 22;\n+\t\tu64 pend_tt : 2;\n+\t\tu64 pend_tag : 32;\n+\t} s;\n+\tstruct cvmx_sso_sl_ppx_pendtag_s cn73xx;\n+\tstruct cvmx_sso_sl_ppx_pendtag_s cn78xx;\n+\tstruct cvmx_sso_sl_ppx_pendtag_s cn78xxp1;\n+\tstruct cvmx_sso_sl_ppx_pendtag_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_sl_ppx_pendtag cvmx_sso_sl_ppx_pendtag_t;\n+\n+/**\n+ * cvmx_sso_sl_pp#_pendwqp\n+ *\n+ * Returns status of each core.\n+ *\n+ */\n+union cvmx_sso_sl_ppx_pendwqp {\n+\tu64 u64;\n+\tstruct cvmx_sso_sl_ppx_pendwqp_s {\n+\t\tu64 pend_switch : 1;\n+\t\tu64 pend_get_work : 1;\n+\t\tu64 pend_get_work_wait : 1;\n+\t\tu64 pend_nosched : 1;\n+\t\tu64 pend_nosched_clr : 1;\n+\t\tu64 pend_desched : 1;\n+\t\tu64 pend_alloc_we : 1;\n+\t\tu64 reserved_56_56 : 1;\n+\t\tu64 pend_index : 12;\n+\t\tu64 reserved_42_43 : 2;\n+\t\tu64 pend_wqp : 42;\n+\t} s;\n+\tstruct cvmx_sso_sl_ppx_pendwqp_cn73xx {\n+\t\tu64 pend_switch : 1;\n+\t\tu64 pend_get_work : 1;\n+\t\tu64 pend_get_work_wait : 1;\n+\t\tu64 pend_nosched : 1;\n+\t\tu64 pend_nosched_clr : 1;\n+\t\tu64 pend_desched : 1;\n+\t\tu64 pend_alloc_we : 1;\n+\t\tu64 reserved_54_56 : 3;\n+\t\tu64 pend_index : 10;\n+\t\tu64 reserved_42_43 : 2;\n+\t\tu64 pend_wqp : 42;\n+\t} cn73xx;\n+\tstruct cvmx_sso_sl_ppx_pendwqp_s cn78xx;\n+\tstruct cvmx_sso_sl_ppx_pendwqp_s cn78xxp1;\n+\tstruct cvmx_sso_sl_ppx_pendwqp_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sso_sl_ppx_pendwqp cvmx_sso_sl_ppx_pendwqp_t;\n+\n+/**\n+ * cvmx_sso_sl_pp#_tag\n+ *\n+ * Returns status of each core.\n+ *\n+ */\n+union cvmx_sso_sl_ppx_tag {\n+\tu64 u64;\n+\tstruct cvmx_sso_sl_ppx_tag_s {\n+\t\tu64 tailc : 1;\n+\t\tu64 reserved_60_62 : 3;\n+\t\tu64 index : 12;\n+\t\tu64 reserved_46_47 : 2;\n+\t\tu64 grp : 10;\n+\t\tu64 head : 1;\n+\t\tu64 tail : 1;\n+\t\tu64 tt : 2;\n+\t\tu64 tag : 32;\n+\t} s;\n+\tstruct cvmx_sso_sl_ppx_tag_cn73xx {\n+\t\tu64 tailc : 1;\n+\t\tu64 reserved_58_62 : 5;\n+\t\tu64 index : 10;\n+\t\tu64 reserved_44_47 : 4;\n+\t\tu64 grp : 8;\n+\t\tu64 head : 1;\n+\t\tu64 tail : 1;\n+\t\tu64 tt : 2;\n+\t\tu64 tag : 32;\n+\t} cn73xx;\n+\tstruct cvmx_sso_sl_ppx_tag_s cn78xx;\n+\tstruct cvmx_sso_sl_ppx_tag_s cn78xxp1;\n+\tstruct cvmx_sso_sl_ppx_tag_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sso_sl_ppx_tag cvmx_sso_sl_ppx_tag_t;\n+\n+/**\n+ * cvmx_sso_sl_pp#_wqp\n+ *\n+ * Returns status of each core.\n+ *\n+ */\n+union cvmx_sso_sl_ppx_wqp {\n+\tu64 u64;\n+\tstruct cvmx_sso_sl_ppx_wqp_s {\n+\t\tu64 reserved_58_63 : 6;\n+\t\tu64 grp : 10;\n+\t\tu64 reserved_42_47 : 6;\n+\t\tu64 wqp : 42;\n+\t} s;\n+\tstruct cvmx_sso_sl_ppx_wqp_cn73xx {\n+\t\tu64 reserved_56_63 : 8;\n+\t\tu64 grp : 8;\n+\t\tu64 reserved_42_47 : 6;\n+\t\tu64 wqp : 42;\n+\t} cn73xx;\n+\tstruct cvmx_sso_sl_ppx_wqp_s cn78xx;\n+\tstruct cvmx_sso_sl_ppx_wqp_s cn78xxp1;\n+\tstruct cvmx_sso_sl_ppx_wqp_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_sso_sl_ppx_wqp cvmx_sso_sl_ppx_wqp_t;\n+\n+/**\n+ * cvmx_sso_taq#_link\n+ *\n+ * Returns TAQ status for a given line.\n+ *\n+ */\n+union cvmx_sso_taqx_link {\n+\tu64 u64;\n+\tstruct cvmx_sso_taqx_link_s {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 next : 11;\n+\t} s;\n+\tstruct cvmx_sso_taqx_link_s cn73xx;\n+\tstruct cvmx_sso_taqx_link_s cn78xx;\n+\tstruct cvmx_sso_taqx_link_s cn78xxp1;\n+\tstruct cvmx_sso_taqx_link_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_taqx_link cvmx_sso_taqx_link_t;\n+\n+/**\n+ * cvmx_sso_taq#_wae#_tag\n+ *\n+ * Returns TAQ status for a given line and WAE within that line.\n+ *\n+ */\n+union cvmx_sso_taqx_waex_tag {\n+\tu64 u64;\n+\tstruct cvmx_sso_taqx_waex_tag_s {\n+\t\tu64 reserved_34_63 : 30;\n+\t\tu64 tt : 2;\n+\t\tu64 tag : 32;\n+\t} s;\n+\tstruct cvmx_sso_taqx_waex_tag_s cn73xx;\n+\tstruct cvmx_sso_taqx_waex_tag_s cn78xx;\n+\tstruct cvmx_sso_taqx_waex_tag_s cn78xxp1;\n+\tstruct cvmx_sso_taqx_waex_tag_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_taqx_waex_tag cvmx_sso_taqx_waex_tag_t;\n+\n+/**\n+ * cvmx_sso_taq#_wae#_wqp\n+ *\n+ * Returns TAQ status for a given line and WAE within that line.\n+ *\n+ */\n+union cvmx_sso_taqx_waex_wqp {\n+\tu64 u64;\n+\tstruct cvmx_sso_taqx_waex_wqp_s {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 wqp : 42;\n+\t} s;\n+\tstruct cvmx_sso_taqx_waex_wqp_s cn73xx;\n+\tstruct cvmx_sso_taqx_waex_wqp_s cn78xx;\n+\tstruct cvmx_sso_taqx_waex_wqp_s cn78xxp1;\n+\tstruct cvmx_sso_taqx_waex_wqp_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_taqx_waex_wqp cvmx_sso_taqx_waex_wqp_t;\n+\n+/**\n+ * cvmx_sso_taq_add\n+ */\n+union cvmx_sso_taq_add {\n+\tu64 u64;\n+\tstruct cvmx_sso_taq_add_s {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 rsvd_free : 13;\n+\t\tu64 reserved_0_15 : 16;\n+\t} s;\n+\tstruct cvmx_sso_taq_add_s cn73xx;\n+\tstruct cvmx_sso_taq_add_s cn78xx;\n+\tstruct cvmx_sso_taq_add_s cn78xxp1;\n+\tstruct cvmx_sso_taq_add_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_taq_add cvmx_sso_taq_add_t;\n+\n+/**\n+ * cvmx_sso_taq_cnt\n+ */\n+union cvmx_sso_taq_cnt {\n+\tu64 u64;\n+\tstruct cvmx_sso_taq_cnt_s {\n+\t\tu64 reserved_27_63 : 37;\n+\t\tu64 rsvd_free : 11;\n+\t\tu64 reserved_11_15 : 5;\n+\t\tu64 free_cnt : 11;\n+\t} s;\n+\tstruct cvmx_sso_taq_cnt_s cn73xx;\n+\tstruct cvmx_sso_taq_cnt_s cn78xx;\n+\tstruct cvmx_sso_taq_cnt_s cn78xxp1;\n+\tstruct cvmx_sso_taq_cnt_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_taq_cnt cvmx_sso_taq_cnt_t;\n+\n+/**\n+ * cvmx_sso_tiaq#_status\n+ *\n+ * Returns TAQ inbound status indexed by group.\n+ *\n+ */\n+union cvmx_sso_tiaqx_status {\n+\tu64 u64;\n+\tstruct cvmx_sso_tiaqx_status_s {\n+\t\tu64 wae_head : 4;\n+\t\tu64 wae_tail : 4;\n+\t\tu64 reserved_47_55 : 9;\n+\t\tu64 wae_used : 15;\n+\t\tu64 reserved_23_31 : 9;\n+\t\tu64 ent_head : 11;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 ent_tail : 11;\n+\t} s;\n+\tstruct cvmx_sso_tiaqx_status_s cn73xx;\n+\tstruct cvmx_sso_tiaqx_status_s cn78xx;\n+\tstruct cvmx_sso_tiaqx_status_s cn78xxp1;\n+\tstruct cvmx_sso_tiaqx_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_tiaqx_status cvmx_sso_tiaqx_status_t;\n+\n+/**\n+ * cvmx_sso_toaq#_status\n+ *\n+ * Returns TAQ outbound status indexed by group.\n+ *\n+ */\n+union cvmx_sso_toaqx_status {\n+\tu64 u64;\n+\tstruct cvmx_sso_toaqx_status_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 ext_vld : 1;\n+\t\tu64 partial : 1;\n+\t\tu64 wae_tail : 4;\n+\t\tu64 reserved_43_55 : 13;\n+\t\tu64 cl_used : 11;\n+\t\tu64 reserved_23_31 : 9;\n+\t\tu64 ent_head : 11;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 ent_tail : 11;\n+\t} s;\n+\tstruct cvmx_sso_toaqx_status_s cn73xx;\n+\tstruct cvmx_sso_toaqx_status_s cn78xx;\n+\tstruct cvmx_sso_toaqx_status_s cn78xxp1;\n+\tstruct cvmx_sso_toaqx_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_toaqx_status cvmx_sso_toaqx_status_t;\n+\n+/**\n+ * cvmx_sso_ts_pc\n+ *\n+ * SSO_TS_PC = SSO Tag Switch Performance Counter\n+ *\n+ * Counts the number of tag switch requests.\n+ * Counter rolls over through zero when max value exceeded.\n+ */\n+union cvmx_sso_ts_pc {\n+\tu64 u64;\n+\tstruct cvmx_sso_ts_pc_s {\n+\t\tu64 ts_pc : 64;\n+\t} s;\n+\tstruct cvmx_sso_ts_pc_s cn68xx;\n+\tstruct cvmx_sso_ts_pc_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_ts_pc cvmx_sso_ts_pc_t;\n+\n+/**\n+ * cvmx_sso_wa_com_pc\n+ *\n+ * SSO_WA_COM_PC = SSO Work Add Combined Performance Counter\n+ *\n+ * Counts the number of add new work requests for all QOS levels.\n+ * Counter rolls over through zero when max value exceeded.\n+ */\n+union cvmx_sso_wa_com_pc {\n+\tu64 u64;\n+\tstruct cvmx_sso_wa_com_pc_s {\n+\t\tu64 wa_pc : 64;\n+\t} s;\n+\tstruct cvmx_sso_wa_com_pc_s cn68xx;\n+\tstruct cvmx_sso_wa_com_pc_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_wa_com_pc cvmx_sso_wa_com_pc_t;\n+\n+/**\n+ * cvmx_sso_wa_pc#\n+ *\n+ * CSR reserved addresses: (64): 0x4200..0x43f8\n+ * CSR align addresses: ===========================================================================================================\n+ * SSO_WA_PCX = SSO Work Add Performance Counter\n+ *             (one per QOS level)\n+ *\n+ * Counts the number of add new work requests for each QOS level.\n+ * Counter rolls over through zero when max value exceeded.\n+ */\n+union cvmx_sso_wa_pcx {\n+\tu64 u64;\n+\tstruct cvmx_sso_wa_pcx_s {\n+\t\tu64 wa_pc : 64;\n+\t} s;\n+\tstruct cvmx_sso_wa_pcx_s cn68xx;\n+\tstruct cvmx_sso_wa_pcx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_wa_pcx cvmx_sso_wa_pcx_t;\n+\n+/**\n+ * cvmx_sso_wq_int\n+ *\n+ * Note, the old POW offsets ran from 0x0 to 0x3f8, leaving the next available slot at 0x400.\n+ * To ensure no overlap, start on 4k boundary: 0x1000.\n+ * SSO_WQ_INT = SSO Work Queue Interrupt Register\n+ *\n+ * Contains the bits (one per group) that set work queue interrupts and are\n+ * used to clear these interrupts.  For more information regarding this\n+ * register, see the interrupt section of the SSO spec.\n+ */\n+union cvmx_sso_wq_int {\n+\tu64 u64;\n+\tstruct cvmx_sso_wq_int_s {\n+\t\tu64 wq_int : 64;\n+\t} s;\n+\tstruct cvmx_sso_wq_int_s cn68xx;\n+\tstruct cvmx_sso_wq_int_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_wq_int cvmx_sso_wq_int_t;\n+\n+/**\n+ * cvmx_sso_wq_int_cnt#\n+ *\n+ * CSR reserved addresses: (64): 0x7200..0x73f8\n+ * CSR align addresses: ===========================================================================================================\n+ * SSO_WQ_INT_CNTX = SSO Work Queue Interrupt Count Register\n+ *                   (one per group)\n+ *\n+ * Contains a read-only copy of the counts used to trigger work queue\n+ * interrupts.  For more information regarding this register, see the interrupt\n+ * section.\n+ */\n+union cvmx_sso_wq_int_cntx {\n+\tu64 u64;\n+\tstruct cvmx_sso_wq_int_cntx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 tc_cnt : 4;\n+\t\tu64 reserved_26_27 : 2;\n+\t\tu64 ds_cnt : 12;\n+\t\tu64 reserved_12_13 : 2;\n+\t\tu64 iq_cnt : 12;\n+\t} s;\n+\tstruct cvmx_sso_wq_int_cntx_s cn68xx;\n+\tstruct cvmx_sso_wq_int_cntx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_wq_int_cntx cvmx_sso_wq_int_cntx_t;\n+\n+/**\n+ * cvmx_sso_wq_int_pc\n+ *\n+ * Contains the threshold value for the work-executable interrupt periodic counter and also a\n+ * read-only copy of the periodic counter. For more information on this register, refer to\n+ * Interrupts.\n+ */\n+union cvmx_sso_wq_int_pc {\n+\tu64 u64;\n+\tstruct cvmx_sso_wq_int_pc_s {\n+\t\tu64 reserved_60_63 : 4;\n+\t\tu64 pc : 28;\n+\t\tu64 reserved_28_31 : 4;\n+\t\tu64 pc_thr : 20;\n+\t\tu64 reserved_0_7 : 8;\n+\t} s;\n+\tstruct cvmx_sso_wq_int_pc_s cn68xx;\n+\tstruct cvmx_sso_wq_int_pc_s cn68xxp1;\n+\tstruct cvmx_sso_wq_int_pc_s cn73xx;\n+\tstruct cvmx_sso_wq_int_pc_s cn78xx;\n+\tstruct cvmx_sso_wq_int_pc_s cn78xxp1;\n+\tstruct cvmx_sso_wq_int_pc_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_wq_int_pc cvmx_sso_wq_int_pc_t;\n+\n+/**\n+ * cvmx_sso_wq_int_thr#\n+ *\n+ * CSR reserved addresses: (96): 0x6100..0x63f8\n+ * CSR align addresses: ===========================================================================================================\n+ * SSO_WQ_INT_THR(0..63) = SSO Work Queue Interrupt Threshold Registers\n+ *                         (one per group)\n+ *\n+ * Contains the thresholds for enabling and setting work queue interrupts.  For\n+ * more information, see the interrupt section.\n+ *\n+ * Note: Up to 16 of the SSO's internal storage buffers can be allocated\n+ * for hardware use and are therefore not available for incoming work queue\n+ * entries.  Additionally, any WS that is not in the EMPTY state consumes a\n+ * buffer.  Thus in a 32 PP system, it is not advisable to set either IQ_THR or\n+ * DS_THR to greater than 2048 - 16 - 32*2 = 1968.  Doing so may prevent the\n+ * interrupt from ever triggering.\n+ *\n+ * Priorities for QOS levels 0..7\n+ */\n+union cvmx_sso_wq_int_thrx {\n+\tu64 u64;\n+\tstruct cvmx_sso_wq_int_thrx_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 tc_en : 1;\n+\t\tu64 tc_thr : 4;\n+\t\tu64 reserved_26_27 : 2;\n+\t\tu64 ds_thr : 12;\n+\t\tu64 reserved_12_13 : 2;\n+\t\tu64 iq_thr : 12;\n+\t} s;\n+\tstruct cvmx_sso_wq_int_thrx_s cn68xx;\n+\tstruct cvmx_sso_wq_int_thrx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_wq_int_thrx cvmx_sso_wq_int_thrx_t;\n+\n+/**\n+ * cvmx_sso_wq_iq_dis\n+ *\n+ * CSR reserved addresses: (1): 0x1008..0x1008\n+ * SSO_WQ_IQ_DIS = SSO Input Queue Interrupt Temporary Disable Mask\n+ *\n+ * Contains the input queue interrupt temporary disable bits (one per group).\n+ * For more information regarding this register, see the interrupt section.\n+ */\n+union cvmx_sso_wq_iq_dis {\n+\tu64 u64;\n+\tstruct cvmx_sso_wq_iq_dis_s {\n+\t\tu64 iq_dis : 64;\n+\t} s;\n+\tstruct cvmx_sso_wq_iq_dis_s cn68xx;\n+\tstruct cvmx_sso_wq_iq_dis_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_wq_iq_dis cvmx_sso_wq_iq_dis_t;\n+\n+/**\n+ * cvmx_sso_ws_cfg\n+ *\n+ * This register contains various SSO work-slot configuration bits.\n+ *\n+ */\n+union cvmx_sso_ws_cfg {\n+\tu64 u64;\n+\tstruct cvmx_sso_ws_cfg_s {\n+\t\tu64 reserved_56_63 : 8;\n+\t\tu64 ocla_bp : 8;\n+\t\tu64 reserved_7_47 : 41;\n+\t\tu64 aw_clk_dis : 1;\n+\t\tu64 gw_clk_dis : 1;\n+\t\tu64 disable_pw : 1;\n+\t\tu64 arbc_step_en : 1;\n+\t\tu64 ncbo_step_en : 1;\n+\t\tu64 soc_ccam_dis : 1;\n+\t\tu64 sso_cclk_dis : 1;\n+\t} s;\n+\tstruct cvmx_sso_ws_cfg_s cn73xx;\n+\tstruct cvmx_sso_ws_cfg_cn78xx {\n+\t\tu64 reserved_56_63 : 8;\n+\t\tu64 ocla_bp : 8;\n+\t\tu64 reserved_5_47 : 43;\n+\t\tu64 disable_pw : 1;\n+\t\tu64 arbc_step_en : 1;\n+\t\tu64 ncbo_step_en : 1;\n+\t\tu64 soc_ccam_dis : 1;\n+\t\tu64 sso_cclk_dis : 1;\n+\t} cn78xx;\n+\tstruct cvmx_sso_ws_cfg_cn78xx cn78xxp1;\n+\tstruct cvmx_sso_ws_cfg_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ws_cfg cvmx_sso_ws_cfg_t;\n+\n+/**\n+ * cvmx_sso_ws_eco\n+ */\n+union cvmx_sso_ws_eco {\n+\tu64 u64;\n+\tstruct cvmx_sso_ws_eco_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 eco_rw : 8;\n+\t} s;\n+\tstruct cvmx_sso_ws_eco_s cn73xx;\n+\tstruct cvmx_sso_ws_eco_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_ws_eco cvmx_sso_ws_eco_t;\n+\n+/**\n+ * cvmx_sso_ws_pc#\n+ *\n+ * CSR reserved addresses: (225): 0x3100..0x3800\n+ * CSR align addresses: ===========================================================================================================\n+ * SSO_WS_PCX = SSO Work Schedule Performance Counter\n+ *              (one per group)\n+ *\n+ * Counts the number of work schedules for each group.\n+ * Counter rolls over through zero when max value exceeded.\n+ */\n+union cvmx_sso_ws_pcx {\n+\tu64 u64;\n+\tstruct cvmx_sso_ws_pcx_s {\n+\t\tu64 ws_pc : 64;\n+\t} s;\n+\tstruct cvmx_sso_ws_pcx_s cn68xx;\n+\tstruct cvmx_sso_ws_pcx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_sso_ws_pcx cvmx_sso_ws_pcx_t;\n+\n+/**\n+ * cvmx_sso_xaq#_head_next\n+ *\n+ * These registers contain the pointer to the next buffer to become the head when the final cache\n+ * line in this buffer is read.\n+ */\n+union cvmx_sso_xaqx_head_next {\n+\tu64 u64;\n+\tstruct cvmx_sso_xaqx_head_next_s {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 ptr : 35;\n+\t\tu64 reserved_0_6 : 7;\n+\t} s;\n+\tstruct cvmx_sso_xaqx_head_next_s cn73xx;\n+\tstruct cvmx_sso_xaqx_head_next_s cn78xx;\n+\tstruct cvmx_sso_xaqx_head_next_s cn78xxp1;\n+\tstruct cvmx_sso_xaqx_head_next_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_xaqx_head_next cvmx_sso_xaqx_head_next_t;\n+\n+/**\n+ * cvmx_sso_xaq#_head_ptr\n+ *\n+ * These registers contain the pointer to the first entry of the external linked list(s) for a\n+ * particular group. Software must initialize the external linked list(s) by programming\n+ * SSO_XAQ()_HEAD_PTR, SSO_XAQ()_HEAD_NEXT, SSO_XAQ()_TAIL_PTR and\n+ * SSO_XAQ()_TAIL_NEXT to identical values.\n+ */\n+union cvmx_sso_xaqx_head_ptr {\n+\tu64 u64;\n+\tstruct cvmx_sso_xaqx_head_ptr_s {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 ptr : 35;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 cl : 5;\n+\t} s;\n+\tstruct cvmx_sso_xaqx_head_ptr_s cn73xx;\n+\tstruct cvmx_sso_xaqx_head_ptr_s cn78xx;\n+\tstruct cvmx_sso_xaqx_head_ptr_s cn78xxp1;\n+\tstruct cvmx_sso_xaqx_head_ptr_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_xaqx_head_ptr cvmx_sso_xaqx_head_ptr_t;\n+\n+/**\n+ * cvmx_sso_xaq#_tail_next\n+ *\n+ * These registers contain the pointer to the next buffer to become the tail when the final cache\n+ * line in this buffer is written.  Register fields are identical to those in\n+ * SSO_XAQ()_HEAD_NEXT above.\n+ */\n+union cvmx_sso_xaqx_tail_next {\n+\tu64 u64;\n+\tstruct cvmx_sso_xaqx_tail_next_s {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 ptr : 35;\n+\t\tu64 reserved_0_6 : 7;\n+\t} s;\n+\tstruct cvmx_sso_xaqx_tail_next_s cn73xx;\n+\tstruct cvmx_sso_xaqx_tail_next_s cn78xx;\n+\tstruct cvmx_sso_xaqx_tail_next_s cn78xxp1;\n+\tstruct cvmx_sso_xaqx_tail_next_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_xaqx_tail_next cvmx_sso_xaqx_tail_next_t;\n+\n+/**\n+ * cvmx_sso_xaq#_tail_ptr\n+ *\n+ * These registers contain the pointer to the last entry of the external linked list(s) for a\n+ * particular group.  Register fields are identical to those in SSO_XAQ()_HEAD_PTR above.\n+ * Software must initialize the external linked list(s) by programming\n+ * SSO_XAQ()_HEAD_PTR, SSO_XAQ()_HEAD_NEXT, SSO_XAQ()_TAIL_PTR and\n+ * SSO_XAQ()_TAIL_NEXT to identical values.\n+ */\n+union cvmx_sso_xaqx_tail_ptr {\n+\tu64 u64;\n+\tstruct cvmx_sso_xaqx_tail_ptr_s {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 ptr : 35;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 cl : 5;\n+\t} s;\n+\tstruct cvmx_sso_xaqx_tail_ptr_s cn73xx;\n+\tstruct cvmx_sso_xaqx_tail_ptr_s cn78xx;\n+\tstruct cvmx_sso_xaqx_tail_ptr_s cn78xxp1;\n+\tstruct cvmx_sso_xaqx_tail_ptr_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_xaqx_tail_ptr cvmx_sso_xaqx_tail_ptr_t;\n+\n+/**\n+ * cvmx_sso_xaq_aura\n+ */\n+union cvmx_sso_xaq_aura {\n+\tu64 u64;\n+\tstruct cvmx_sso_xaq_aura_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 node : 2;\n+\t\tu64 laura : 10;\n+\t} s;\n+\tstruct cvmx_sso_xaq_aura_s cn73xx;\n+\tstruct cvmx_sso_xaq_aura_s cn78xx;\n+\tstruct cvmx_sso_xaq_aura_s cn78xxp1;\n+\tstruct cvmx_sso_xaq_aura_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_xaq_aura cvmx_sso_xaq_aura_t;\n+\n+/**\n+ * cvmx_sso_xaq_latency_pc\n+ */\n+union cvmx_sso_xaq_latency_pc {\n+\tu64 u64;\n+\tstruct cvmx_sso_xaq_latency_pc_s {\n+\t\tu64 count : 64;\n+\t} s;\n+\tstruct cvmx_sso_xaq_latency_pc_s cn73xx;\n+\tstruct cvmx_sso_xaq_latency_pc_s cn78xx;\n+\tstruct cvmx_sso_xaq_latency_pc_s cn78xxp1;\n+\tstruct cvmx_sso_xaq_latency_pc_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_xaq_latency_pc cvmx_sso_xaq_latency_pc_t;\n+\n+/**\n+ * cvmx_sso_xaq_req_pc\n+ */\n+union cvmx_sso_xaq_req_pc {\n+\tu64 u64;\n+\tstruct cvmx_sso_xaq_req_pc_s {\n+\t\tu64 count : 64;\n+\t} s;\n+\tstruct cvmx_sso_xaq_req_pc_s cn73xx;\n+\tstruct cvmx_sso_xaq_req_pc_s cn78xx;\n+\tstruct cvmx_sso_xaq_req_pc_s cn78xxp1;\n+\tstruct cvmx_sso_xaq_req_pc_s cnf75xx;\n+};\n+\n+typedef union cvmx_sso_xaq_req_pc cvmx_sso_xaq_req_pc_t;\n+\n+#endif\n",
    "prefixes": [
        "v1",
        "32/50"
    ]
}