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{
    "id": 1415008,
    "url": "http://patchwork.ozlabs.org/api/patches/1415008/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-24-sr@denx.de/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20201211160612.1498780-24-sr@denx.de>",
    "list_archive_url": null,
    "date": "2020-12-11T16:05:45",
    "name": "[v1,23/50] mips: octeon: Add cvmx-pki-defs.h header file",
    "commit_ref": "8ba9b0a24cbc9dfa5bcd110a1d838ff1d9904397",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "6857dce57a24fe55ada444620426dcf315aa6355",
    "submitter": {
        "id": 13,
        "url": "http://patchwork.ozlabs.org/api/people/13/?format=api",
        "name": "Stefan Roese",
        "email": "sr@denx.de"
    },
    "delegate": {
        "id": 4307,
        "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api",
        "username": "danielschwierzeck",
        "first_name": "Daniel",
        "last_name": "Schwierzeck",
        "email": "daniel.schwierzeck@googlemail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-24-sr@denx.de/mbox/",
    "series": [
        {
            "id": 220054,
            "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054",
            "date": "2020-12-11T16:05:23",
            "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1415008/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1415008/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Stefan Roese <sr@denx.de>",
        "To": "u-boot@lists.denx.de",
        "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com",
        "Subject": "[PATCH v1 23/50] mips: octeon: Add cvmx-pki-defs.h header file",
        "Date": "Fri, 11 Dec 2020 17:05:45 +0100",
        "Message-Id": "<20201211160612.1498780-24-sr@denx.de>",
        "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>",
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    "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-pki-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-pki-defs.h  | 2353 +++++++++++++++++\n 1 file changed, 2353 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pki-defs.h",
    "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pki-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-pki-defs.h\nnew file mode 100644\nindex 0000000000..4465872e87\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-pki-defs.h\n@@ -0,0 +1,2353 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon pki.\n+ */\n+\n+#ifndef __CVMX_PKI_DEFS_H__\n+#define __CVMX_PKI_DEFS_H__\n+\n+#define CVMX_PKI_ACTIVE0\t     (0x0001180044000220ull)\n+#define CVMX_PKI_ACTIVE1\t     (0x0001180044000230ull)\n+#define CVMX_PKI_ACTIVE2\t     (0x0001180044000240ull)\n+#define CVMX_PKI_AURAX_CFG(offset)   (0x0001180044900000ull + ((offset) & 1023) * 8)\n+#define CVMX_PKI_BIST_STATUS0\t     (0x0001180044000080ull)\n+#define CVMX_PKI_BIST_STATUS1\t     (0x0001180044000088ull)\n+#define CVMX_PKI_BIST_STATUS2\t     (0x0001180044000090ull)\n+#define CVMX_PKI_BPIDX_STATE(offset) (0x0001180044B00000ull + ((offset) & 1023) * 8)\n+#define CVMX_PKI_BUF_CTL\t     (0x0001180044000100ull)\n+#define CVMX_PKI_CHANX_CFG(offset)   (0x0001180044A00000ull + ((offset) & 4095) * 8)\n+#define CVMX_PKI_CLKEN\t\t     (0x0001180044000410ull)\n+#define CVMX_PKI_CLX_ECC_CTL(offset) (0x000118004400C020ull + ((offset) & 3) * 0x10000ull)\n+#define CVMX_PKI_CLX_ECC_INT(offset) (0x000118004400C010ull + ((offset) & 3) * 0x10000ull)\n+#define CVMX_PKI_CLX_INT(offset)     (0x000118004400C000ull + ((offset) & 3) * 0x10000ull)\n+#define CVMX_PKI_CLX_PCAMX_ACTIONX(a, b, c)                                                        \\\n+\t(0x0001180044708000ull + ((a) << 16) + ((b) << 12) + ((c) << 3))\n+#define CVMX_PKI_CLX_PCAMX_MATCHX(a, b, c)                                                         \\\n+\t(0x0001180044704000ull + ((a) << 16) + ((b) << 12) + ((c) << 3))\n+#define CVMX_PKI_CLX_PCAMX_TERMX(a, b, c)                                                          \\\n+\t(0x0001180044700000ull + ((a) << 16) + ((b) << 12) + ((c) << 3))\n+#define CVMX_PKI_CLX_PKINDX_CFG(offset, block_id)                                                  \\\n+\t(0x0001180044300040ull + (((offset) & 63) + ((block_id) & 3) * 0x100ull) * 256)\n+#define CVMX_PKI_CLX_PKINDX_KMEMX(a, b, c)                                                         \\\n+\t(0x0001180044200000ull + ((a) << 16) + ((b) << 8) + ((c) << 3))\n+#define CVMX_PKI_CLX_PKINDX_L2_CUSTOM(offset, block_id)                                            \\\n+\t(0x0001180044300058ull + (((offset) & 63) + ((block_id) & 3) * 0x100ull) * 256)\n+#define CVMX_PKI_CLX_PKINDX_LG_CUSTOM(offset, block_id)                                            \\\n+\t(0x0001180044300060ull + (((offset) & 63) + ((block_id) & 3) * 0x100ull) * 256)\n+#define CVMX_PKI_CLX_PKINDX_SKIP(offset, block_id)                                                 \\\n+\t(0x0001180044300050ull + (((offset) & 63) + ((block_id) & 3) * 0x100ull) * 256)\n+#define CVMX_PKI_CLX_PKINDX_STYLE(offset, block_id)                                                \\\n+\t(0x0001180044300048ull + (((offset) & 63) + ((block_id) & 3) * 0x100ull) * 256)\n+#define CVMX_PKI_CLX_SMEMX(offset, block_id)                                                       \\\n+\t(0x0001180044400000ull + (((offset) & 2047) + ((block_id) & 3) * 0x2000ull) * 8)\n+#define CVMX_PKI_CLX_START(offset) (0x000118004400C030ull + ((offset) & 3) * 0x10000ull)\n+#define CVMX_PKI_CLX_STYLEX_ALG(offset, block_id)                                                  \\\n+\t(0x0001180044501000ull + (((offset) & 63) + ((block_id) & 3) * 0x2000ull) * 8)\n+#define CVMX_PKI_CLX_STYLEX_CFG(offset, block_id)                                                  \\\n+\t(0x0001180044500000ull + (((offset) & 63) + ((block_id) & 3) * 0x2000ull) * 8)\n+#define CVMX_PKI_CLX_STYLEX_CFG2(offset, block_id)                                                 \\\n+\t(0x0001180044500800ull + (((offset) & 63) + ((block_id) & 3) * 0x2000ull) * 8)\n+#define CVMX_PKI_DSTATX_STAT0(offset)\t (0x0001180044C00000ull + ((offset) & 1023) * 64)\n+#define CVMX_PKI_DSTATX_STAT1(offset)\t (0x0001180044C00008ull + ((offset) & 1023) * 64)\n+#define CVMX_PKI_DSTATX_STAT2(offset)\t (0x0001180044C00010ull + ((offset) & 1023) * 64)\n+#define CVMX_PKI_DSTATX_STAT3(offset)\t (0x0001180044C00018ull + ((offset) & 1023) * 64)\n+#define CVMX_PKI_DSTATX_STAT4(offset)\t (0x0001180044C00020ull + ((offset) & 1023) * 64)\n+#define CVMX_PKI_ECC_CTL0\t\t (0x0001180044000060ull)\n+#define CVMX_PKI_ECC_CTL1\t\t (0x0001180044000068ull)\n+#define CVMX_PKI_ECC_CTL2\t\t (0x0001180044000070ull)\n+#define CVMX_PKI_ECC_INT0\t\t (0x0001180044000040ull)\n+#define CVMX_PKI_ECC_INT1\t\t (0x0001180044000048ull)\n+#define CVMX_PKI_ECC_INT2\t\t (0x0001180044000050ull)\n+#define CVMX_PKI_FRM_LEN_CHKX(offset)\t (0x0001180044004000ull + ((offset) & 1) * 8)\n+#define CVMX_PKI_GBL_PEN\t\t (0x0001180044000200ull)\n+#define CVMX_PKI_GEN_INT\t\t (0x0001180044000020ull)\n+#define CVMX_PKI_ICGX_CFG(offset)\t (0x000118004400A000ull)\n+#define CVMX_PKI_IMEMX(offset)\t\t (0x0001180044100000ull + ((offset) & 2047) * 8)\n+#define CVMX_PKI_LTYPEX_MAP(offset)\t (0x0001180044005000ull + ((offset) & 31) * 8)\n+#define CVMX_PKI_PBE_ECO\t\t (0x0001180044000710ull)\n+#define CVMX_PKI_PCAM_LOOKUP\t\t (0x0001180044000500ull)\n+#define CVMX_PKI_PCAM_RESULT\t\t (0x0001180044000510ull)\n+#define CVMX_PKI_PFE_DIAG\t\t (0x0001180044000560ull)\n+#define CVMX_PKI_PFE_ECO\t\t (0x0001180044000720ull)\n+#define CVMX_PKI_PIX_CLKEN\t\t (0x0001180044000600ull)\n+#define CVMX_PKI_PIX_DIAG\t\t (0x0001180044000580ull)\n+#define CVMX_PKI_PIX_ECO\t\t (0x0001180044000700ull)\n+#define CVMX_PKI_PKINDX_ICGSEL(offset)\t (0x0001180044010000ull + ((offset) & 63) * 8)\n+#define CVMX_PKI_PKNDX_INB_STAT0(offset) (0x0001180044F00000ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_PKNDX_INB_STAT1(offset) (0x0001180044F00008ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_PKNDX_INB_STAT2(offset) (0x0001180044F00010ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_PKT_ERR\t\t (0x0001180044000030ull)\n+#define CVMX_PKI_PTAG_AVAIL\t\t (0x0001180044000130ull)\n+#define CVMX_PKI_QPG_TBLBX(offset)\t (0x0001180044820000ull + ((offset) & 2047) * 8)\n+#define CVMX_PKI_QPG_TBLX(offset)\t (0x0001180044800000ull + ((offset) & 2047) * 8)\n+#define CVMX_PKI_REASM_SOPX(offset)\t (0x0001180044006000ull + ((offset) & 1) * 8)\n+#define CVMX_PKI_REQ_WGT\t\t (0x0001180044000120ull)\n+#define CVMX_PKI_SFT_RST\t\t (0x0001180044000010ull)\n+#define CVMX_PKI_STATX_HIST0(offset)\t (0x0001180044E00000ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_HIST1(offset)\t (0x0001180044E00008ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_HIST2(offset)\t (0x0001180044E00010ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_HIST3(offset)\t (0x0001180044E00018ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_HIST4(offset)\t (0x0001180044E00020ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_HIST5(offset)\t (0x0001180044E00028ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_HIST6(offset)\t (0x0001180044E00030ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT0(offset)\t (0x0001180044E00038ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT1(offset)\t (0x0001180044E00040ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT10(offset)\t (0x0001180044E00088ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT11(offset)\t (0x0001180044E00090ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT12(offset)\t (0x0001180044E00098ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT13(offset)\t (0x0001180044E000A0ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT14(offset)\t (0x0001180044E000A8ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT15(offset)\t (0x0001180044E000B0ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT16(offset)\t (0x0001180044E000B8ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT17(offset)\t (0x0001180044E000C0ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT18(offset)\t (0x0001180044E000C8ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT2(offset)\t (0x0001180044E00048ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT3(offset)\t (0x0001180044E00050ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT4(offset)\t (0x0001180044E00058ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT5(offset)\t (0x0001180044E00060ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT6(offset)\t (0x0001180044E00068ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT7(offset)\t (0x0001180044E00070ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT8(offset)\t (0x0001180044E00078ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STATX_STAT9(offset)\t (0x0001180044E00080ull + ((offset) & 63) * 256)\n+#define CVMX_PKI_STAT_CTL\t\t (0x0001180044000110ull)\n+#define CVMX_PKI_STYLEX_BUF(offset)\t (0x0001180044024000ull + ((offset) & 63) * 8)\n+#define CVMX_PKI_STYLEX_TAG_MASK(offset) (0x0001180044021000ull + ((offset) & 63) * 8)\n+#define CVMX_PKI_STYLEX_TAG_SEL(offset)\t (0x0001180044020000ull + ((offset) & 63) * 8)\n+#define CVMX_PKI_STYLEX_WQ2(offset)\t (0x0001180044022000ull + ((offset) & 63) * 8)\n+#define CVMX_PKI_STYLEX_WQ4(offset)\t (0x0001180044023000ull + ((offset) & 63) * 8)\n+#define CVMX_PKI_TAG_INCX_CTL(offset)\t (0x0001180044007000ull + ((offset) & 31) * 8)\n+#define CVMX_PKI_TAG_INCX_MASK(offset)\t (0x0001180044008000ull + ((offset) & 31) * 8)\n+#define CVMX_PKI_TAG_SECRET\t\t (0x0001180044000430ull)\n+#define CVMX_PKI_X2P_REQ_OFL\t\t (0x0001180044000038ull)\n+\n+/**\n+ * cvmx_pki_active0\n+ */\n+union cvmx_pki_active0 {\n+\tu64 u64;\n+\tstruct cvmx_pki_active0_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 pfe_active : 1;\n+\t} s;\n+\tstruct cvmx_pki_active0_s cn73xx;\n+\tstruct cvmx_pki_active0_s cn78xx;\n+\tstruct cvmx_pki_active0_s cn78xxp1;\n+\tstruct cvmx_pki_active0_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_active0 cvmx_pki_active0_t;\n+\n+/**\n+ * cvmx_pki_active1\n+ */\n+union cvmx_pki_active1 {\n+\tu64 u64;\n+\tstruct cvmx_pki_active1_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 fpc_active : 1;\n+\t\tu64 iobp_active : 1;\n+\t\tu64 sws_active : 1;\n+\t\tu64 pbtag_active : 1;\n+\t} s;\n+\tstruct cvmx_pki_active1_s cn73xx;\n+\tstruct cvmx_pki_active1_s cn78xx;\n+\tstruct cvmx_pki_active1_s cn78xxp1;\n+\tstruct cvmx_pki_active1_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_active1 cvmx_pki_active1_t;\n+\n+/**\n+ * cvmx_pki_active2\n+ */\n+union cvmx_pki_active2 {\n+\tu64 u64;\n+\tstruct cvmx_pki_active2_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 pix_active : 5;\n+\t} s;\n+\tstruct cvmx_pki_active2_s cn73xx;\n+\tstruct cvmx_pki_active2_s cn78xx;\n+\tstruct cvmx_pki_active2_s cn78xxp1;\n+\tstruct cvmx_pki_active2_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_active2 cvmx_pki_active2_t;\n+\n+/**\n+ * cvmx_pki_aura#_cfg\n+ *\n+ * This register configures aura backpressure, etc.\n+ *\n+ */\n+union cvmx_pki_aurax_cfg {\n+\tu64 u64;\n+\tstruct cvmx_pki_aurax_cfg_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 pkt_add : 2;\n+\t\tu64 reserved_19_29 : 11;\n+\t\tu64 ena_red : 1;\n+\t\tu64 ena_drop : 1;\n+\t\tu64 ena_bp : 1;\n+\t\tu64 reserved_10_15 : 6;\n+\t\tu64 bpid : 10;\n+\t} s;\n+\tstruct cvmx_pki_aurax_cfg_s cn73xx;\n+\tstruct cvmx_pki_aurax_cfg_s cn78xx;\n+\tstruct cvmx_pki_aurax_cfg_s cn78xxp1;\n+\tstruct cvmx_pki_aurax_cfg_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_aurax_cfg cvmx_pki_aurax_cfg_t;\n+\n+/**\n+ * cvmx_pki_bist_status0\n+ *\n+ * This register indicates BIST status.\n+ *\n+ */\n+union cvmx_pki_bist_status0 {\n+\tu64 u64;\n+\tstruct cvmx_pki_bist_status0_s {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 bist : 31;\n+\t} s;\n+\tstruct cvmx_pki_bist_status0_s cn73xx;\n+\tstruct cvmx_pki_bist_status0_s cn78xx;\n+\tstruct cvmx_pki_bist_status0_s cn78xxp1;\n+\tstruct cvmx_pki_bist_status0_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_bist_status0 cvmx_pki_bist_status0_t;\n+\n+/**\n+ * cvmx_pki_bist_status1\n+ *\n+ * This register indicates BIST status.\n+ *\n+ */\n+union cvmx_pki_bist_status1 {\n+\tu64 u64;\n+\tstruct cvmx_pki_bist_status1_s {\n+\t\tu64 reserved_26_63 : 38;\n+\t\tu64 bist : 26;\n+\t} s;\n+\tstruct cvmx_pki_bist_status1_s cn73xx;\n+\tstruct cvmx_pki_bist_status1_s cn78xx;\n+\tstruct cvmx_pki_bist_status1_cn78xxp1 {\n+\t\tu64 reserved_21_63 : 43;\n+\t\tu64 bist : 21;\n+\t} cn78xxp1;\n+\tstruct cvmx_pki_bist_status1_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_bist_status1 cvmx_pki_bist_status1_t;\n+\n+/**\n+ * cvmx_pki_bist_status2\n+ *\n+ * This register indicates BIST status.\n+ *\n+ */\n+union cvmx_pki_bist_status2 {\n+\tu64 u64;\n+\tstruct cvmx_pki_bist_status2_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 bist : 25;\n+\t} s;\n+\tstruct cvmx_pki_bist_status2_s cn73xx;\n+\tstruct cvmx_pki_bist_status2_s cn78xx;\n+\tstruct cvmx_pki_bist_status2_s cn78xxp1;\n+\tstruct cvmx_pki_bist_status2_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_bist_status2 cvmx_pki_bist_status2_t;\n+\n+/**\n+ * cvmx_pki_bpid#_state\n+ *\n+ * This register shows the current bpid state for diagnostics.\n+ *\n+ */\n+union cvmx_pki_bpidx_state {\n+\tu64 u64;\n+\tstruct cvmx_pki_bpidx_state_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 xoff : 1;\n+\t} s;\n+\tstruct cvmx_pki_bpidx_state_s cn73xx;\n+\tstruct cvmx_pki_bpidx_state_s cn78xx;\n+\tstruct cvmx_pki_bpidx_state_s cn78xxp1;\n+\tstruct cvmx_pki_bpidx_state_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_bpidx_state cvmx_pki_bpidx_state_t;\n+\n+/**\n+ * cvmx_pki_buf_ctl\n+ */\n+union cvmx_pki_buf_ctl {\n+\tu64 u64;\n+\tstruct cvmx_pki_buf_ctl_s {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 fpa_wait : 1;\n+\t\tu64 fpa_cac_dis : 1;\n+\t\tu64 reserved_6_8 : 3;\n+\t\tu64 pkt_off : 1;\n+\t\tu64 reserved_3_4 : 2;\n+\t\tu64 pbp_en : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pki_en : 1;\n+\t} s;\n+\tstruct cvmx_pki_buf_ctl_s cn73xx;\n+\tstruct cvmx_pki_buf_ctl_s cn78xx;\n+\tstruct cvmx_pki_buf_ctl_s cn78xxp1;\n+\tstruct cvmx_pki_buf_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_buf_ctl cvmx_pki_buf_ctl_t;\n+\n+/**\n+ * cvmx_pki_chan#_cfg\n+ *\n+ * This register configures each channel.\n+ *\n+ */\n+union cvmx_pki_chanx_cfg {\n+\tu64 u64;\n+\tstruct cvmx_pki_chanx_cfg_s {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 imp : 1;\n+\t\tu64 reserved_10_15 : 6;\n+\t\tu64 bpid : 10;\n+\t} s;\n+\tstruct cvmx_pki_chanx_cfg_s cn73xx;\n+\tstruct cvmx_pki_chanx_cfg_s cn78xx;\n+\tstruct cvmx_pki_chanx_cfg_s cn78xxp1;\n+\tstruct cvmx_pki_chanx_cfg_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_chanx_cfg cvmx_pki_chanx_cfg_t;\n+\n+/**\n+ * cvmx_pki_cl#_ecc_ctl\n+ *\n+ * This register configures ECC. All of PKI_CL()_ECC_CTL must be configured identically.\n+ *\n+ */\n+union cvmx_pki_clx_ecc_ctl {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_ecc_ctl_s {\n+\t\tu64 pcam_en : 1;\n+\t\tu64 reserved_24_62 : 39;\n+\t\tu64 pcam1_flip : 2;\n+\t\tu64 pcam0_flip : 2;\n+\t\tu64 smem_flip : 2;\n+\t\tu64 dmem_flip : 1;\n+\t\tu64 rf_flip : 1;\n+\t\tu64 reserved_5_15 : 11;\n+\t\tu64 pcam1_cdis : 1;\n+\t\tu64 pcam0_cdis : 1;\n+\t\tu64 smem_cdis : 1;\n+\t\tu64 dmem_cdis : 1;\n+\t\tu64 rf_cdis : 1;\n+\t} s;\n+\tstruct cvmx_pki_clx_ecc_ctl_s cn73xx;\n+\tstruct cvmx_pki_clx_ecc_ctl_s cn78xx;\n+\tstruct cvmx_pki_clx_ecc_ctl_s cn78xxp1;\n+\tstruct cvmx_pki_clx_ecc_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_ecc_ctl cvmx_pki_clx_ecc_ctl_t;\n+\n+/**\n+ * cvmx_pki_cl#_ecc_int\n+ */\n+union cvmx_pki_clx_ecc_int {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_ecc_int_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 pcam1_dbe : 1;\n+\t\tu64 pcam1_sbe : 1;\n+\t\tu64 pcam0_dbe : 1;\n+\t\tu64 pcam0_sbe : 1;\n+\t\tu64 smem_dbe : 1;\n+\t\tu64 smem_sbe : 1;\n+\t\tu64 dmem_perr : 1;\n+\t\tu64 rf_perr : 1;\n+\t} s;\n+\tstruct cvmx_pki_clx_ecc_int_s cn73xx;\n+\tstruct cvmx_pki_clx_ecc_int_s cn78xx;\n+\tstruct cvmx_pki_clx_ecc_int_s cn78xxp1;\n+\tstruct cvmx_pki_clx_ecc_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_ecc_int cvmx_pki_clx_ecc_int_t;\n+\n+/**\n+ * cvmx_pki_cl#_int\n+ */\n+union cvmx_pki_clx_int {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_int_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 iptint : 1;\n+\t\tu64 sched_conf : 1;\n+\t\tu64 pcam_conf : 2;\n+\t} s;\n+\tstruct cvmx_pki_clx_int_s cn73xx;\n+\tstruct cvmx_pki_clx_int_s cn78xx;\n+\tstruct cvmx_pki_clx_int_s cn78xxp1;\n+\tstruct cvmx_pki_clx_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_int cvmx_pki_clx_int_t;\n+\n+/**\n+ * cvmx_pki_cl#_pcam#_action#\n+ *\n+ * This register configures the result side of the PCAM. PKI hardware is opaque as to the use\n+ * of the 32 bits of CAM result.\n+ *\n+ * For each legal j and k, PKI_CL(i)_PCAM(j)_ACTION(k) must be configured identically for i=0..1.\n+ *\n+ * With the current parse engine code:\n+ *\n+ * Action performed based on PCAM lookup using the PKI_CL()_PCAM()_TERM() and\n+ * PKI_CL()_PCAM()_MATCH() registers.\n+ *\n+ * If lookup data matches no PCAM entries, then no action takes place. No matches indicates\n+ * normal parsing will continue.\n+ *\n+ * If data matches multiple PCAM entries, PKI_WQE_S[ERRLEV,OPCODE] of the processed packet may\n+ * be set to PKI_ERRLEV_E::RE,PKI_OPCODE_E::RE_PKIPCAM and the PKI_CL()_INT[PCAM_CONF] error\n+ * interrupt is signaled.  Once a conflict is detected, the PCAM state is unpredictable and is\n+ * required to be fully reconfigured before further valid processing can take place.\n+ */\n+union cvmx_pki_clx_pcamx_actionx {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_pcamx_actionx_s {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 pmc : 7;\n+\t\tu64 style_add : 8;\n+\t\tu64 pf : 3;\n+\t\tu64 setty : 5;\n+\t\tu64 advance : 8;\n+\t} s;\n+\tstruct cvmx_pki_clx_pcamx_actionx_s cn73xx;\n+\tstruct cvmx_pki_clx_pcamx_actionx_s cn78xx;\n+\tstruct cvmx_pki_clx_pcamx_actionx_s cn78xxp1;\n+\tstruct cvmx_pki_clx_pcamx_actionx_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_pcamx_actionx cvmx_pki_clx_pcamx_actionx_t;\n+\n+/**\n+ * cvmx_pki_cl#_pcam#_match#\n+ *\n+ * This register configures the match side of the PCAM. PKI hardware is opaque as to the use\n+ * of the 32 bits of CAM data.\n+ *\n+ * For each legal j and k, PKI_CL(i)_PCAM(j)_MATCH(k) must be configured identically for i=0..1.\n+ */\n+union cvmx_pki_clx_pcamx_matchx {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_pcamx_matchx_s {\n+\t\tu64 data1 : 32;\n+\t\tu64 data0 : 32;\n+\t} s;\n+\tstruct cvmx_pki_clx_pcamx_matchx_s cn73xx;\n+\tstruct cvmx_pki_clx_pcamx_matchx_s cn78xx;\n+\tstruct cvmx_pki_clx_pcamx_matchx_s cn78xxp1;\n+\tstruct cvmx_pki_clx_pcamx_matchx_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_pcamx_matchx cvmx_pki_clx_pcamx_matchx_t;\n+\n+/**\n+ * cvmx_pki_cl#_pcam#_term#\n+ *\n+ * This register configures the match side of the PCAM. PKI hardware is opaque as to the use\n+ * of the 16 bits of CAM data; the split between TERM and STYLE is defined by the\n+ * parse engine.\n+ *\n+ * For each legal j and k, PKI_CL(i)_PCAM(j)_TERM(k) must be configured identically for i=0..1.\n+ */\n+union cvmx_pki_clx_pcamx_termx {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_pcamx_termx_s {\n+\t\tu64 valid : 1;\n+\t\tu64 reserved_48_62 : 15;\n+\t\tu64 term1 : 8;\n+\t\tu64 style1 : 8;\n+\t\tu64 reserved_16_31 : 16;\n+\t\tu64 term0 : 8;\n+\t\tu64 style0 : 8;\n+\t} s;\n+\tstruct cvmx_pki_clx_pcamx_termx_s cn73xx;\n+\tstruct cvmx_pki_clx_pcamx_termx_s cn78xx;\n+\tstruct cvmx_pki_clx_pcamx_termx_s cn78xxp1;\n+\tstruct cvmx_pki_clx_pcamx_termx_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_pcamx_termx cvmx_pki_clx_pcamx_termx_t;\n+\n+/**\n+ * cvmx_pki_cl#_pkind#_cfg\n+ *\n+ * This register is inside PKI_CL()_PKIND()_KMEM(). These CSRs are used only by\n+ * the PKI parse engine.\n+ *\n+ * For each legal j, PKI_CL(i)_PKIND(j)_CFG must be configured identically for i=0..1.\n+ */\n+union cvmx_pki_clx_pkindx_cfg {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_pkindx_cfg_s {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 lg_custom_layer : 3;\n+\t\tu64 fcs_pres : 1;\n+\t\tu64 mpls_en : 1;\n+\t\tu64 inst_hdr : 1;\n+\t\tu64 lg_custom : 1;\n+\t\tu64 fulc_en : 1;\n+\t\tu64 dsa_en : 1;\n+\t\tu64 hg2_en : 1;\n+\t\tu64 hg_en : 1;\n+\t} s;\n+\tstruct cvmx_pki_clx_pkindx_cfg_s cn73xx;\n+\tstruct cvmx_pki_clx_pkindx_cfg_s cn78xx;\n+\tstruct cvmx_pki_clx_pkindx_cfg_s cn78xxp1;\n+\tstruct cvmx_pki_clx_pkindx_cfg_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_pkindx_cfg cvmx_pki_clx_pkindx_cfg_t;\n+\n+/**\n+ * cvmx_pki_cl#_pkind#_kmem#\n+ *\n+ * This register initializes the KMEM, which initializes the parse engine state for each\n+ * pkind. These CSRs are used only by the PKI parse engine.\n+ *\n+ * Inside the KMEM are the following parse engine registers. These registers are the\n+ * preferred access method for software:\n+ * * PKI_CL()_PKIND()_CFG.\n+ * * PKI_CL()_PKIND()_STYLE.\n+ * * PKI_CL()_PKIND()_SKIP.\n+ * * PKI_CL()_PKIND()_L2_CUSTOM.\n+ * * PKI_CL()_PKIND()_LG_CUSTOM.\n+ *\n+ * To avoid overlapping addresses, these aliases have address bit 20 set in contrast to\n+ * this register; the PKI address decoder ignores bit 20 when accessing\n+ * PKI_CL()_PKIND()_KMEM().\n+ *\n+ * Software must reload the PKI_CL()_PKIND()_KMEM() registers upon the detection of\n+ * PKI_ECC_INT0[KMEM_SBE] or PKI_ECC_INT0[KMEM_DBE].\n+ *\n+ * For each legal j and k value, PKI_CL(i)_PKIND(j)_KMEM(k) must be configured\n+ * identically for i=0..1.\n+ */\n+union cvmx_pki_clx_pkindx_kmemx {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_pkindx_kmemx_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 data : 16;\n+\t} s;\n+\tstruct cvmx_pki_clx_pkindx_kmemx_s cn73xx;\n+\tstruct cvmx_pki_clx_pkindx_kmemx_s cn78xx;\n+\tstruct cvmx_pki_clx_pkindx_kmemx_s cn78xxp1;\n+\tstruct cvmx_pki_clx_pkindx_kmemx_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_pkindx_kmemx cvmx_pki_clx_pkindx_kmemx_t;\n+\n+/**\n+ * cvmx_pki_cl#_pkind#_l2_custom\n+ *\n+ * This register is inside PKI_CL()_PKIND()_KMEM(). These CSRs are used only by\n+ * the PKI parse engine.\n+ *\n+ * For each legal j, PKI_CL(i)_PKIND(j)_L2_CUSTOM must be configured identically for i=0..1.\n+ */\n+union cvmx_pki_clx_pkindx_l2_custom {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_pkindx_l2_custom_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 valid : 1;\n+\t\tu64 reserved_8_14 : 7;\n+\t\tu64 offset : 8;\n+\t} s;\n+\tstruct cvmx_pki_clx_pkindx_l2_custom_s cn73xx;\n+\tstruct cvmx_pki_clx_pkindx_l2_custom_s cn78xx;\n+\tstruct cvmx_pki_clx_pkindx_l2_custom_s cn78xxp1;\n+\tstruct cvmx_pki_clx_pkindx_l2_custom_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_pkindx_l2_custom cvmx_pki_clx_pkindx_l2_custom_t;\n+\n+/**\n+ * cvmx_pki_cl#_pkind#_lg_custom\n+ *\n+ * This register is inside PKI_CL()_PKIND()_KMEM(). These CSRs are used only by\n+ * the PKI parse engine.\n+ *\n+ * For each legal j, PKI_CL(i)_PKIND(j)_LG_CUSTOM must be configured identically for i=0..1.\n+ */\n+union cvmx_pki_clx_pkindx_lg_custom {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_pkindx_lg_custom_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 offset : 8;\n+\t} s;\n+\tstruct cvmx_pki_clx_pkindx_lg_custom_s cn73xx;\n+\tstruct cvmx_pki_clx_pkindx_lg_custom_s cn78xx;\n+\tstruct cvmx_pki_clx_pkindx_lg_custom_s cn78xxp1;\n+\tstruct cvmx_pki_clx_pkindx_lg_custom_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_pkindx_lg_custom cvmx_pki_clx_pkindx_lg_custom_t;\n+\n+/**\n+ * cvmx_pki_cl#_pkind#_skip\n+ *\n+ * This register is inside PKI_CL()_PKIND()_KMEM(). These CSRs are used only by\n+ * the PKI parse engine.\n+ *\n+ * For each legal j, PKI_CL(i)_PKIND(j)_SKIP must be configured identically for i=0..1.\n+ */\n+union cvmx_pki_clx_pkindx_skip {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_pkindx_skip_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 fcs_skip : 8;\n+\t\tu64 inst_skip : 8;\n+\t} s;\n+\tstruct cvmx_pki_clx_pkindx_skip_s cn73xx;\n+\tstruct cvmx_pki_clx_pkindx_skip_s cn78xx;\n+\tstruct cvmx_pki_clx_pkindx_skip_s cn78xxp1;\n+\tstruct cvmx_pki_clx_pkindx_skip_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_pkindx_skip cvmx_pki_clx_pkindx_skip_t;\n+\n+/**\n+ * cvmx_pki_cl#_pkind#_style\n+ *\n+ * This register is inside PKI_CL()_PKIND()_KMEM(). These CSRs are used only by\n+ * the PKI parse engine.\n+ *\n+ * For each legal j, PKI_CL(i)_PKIND(j)_STYLE must be configured identically for i=0..1.\n+ */\n+union cvmx_pki_clx_pkindx_style {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_pkindx_style_s {\n+\t\tu64 reserved_15_63 : 49;\n+\t\tu64 pm : 7;\n+\t\tu64 style : 8;\n+\t} s;\n+\tstruct cvmx_pki_clx_pkindx_style_s cn73xx;\n+\tstruct cvmx_pki_clx_pkindx_style_s cn78xx;\n+\tstruct cvmx_pki_clx_pkindx_style_s cn78xxp1;\n+\tstruct cvmx_pki_clx_pkindx_style_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_pkindx_style cvmx_pki_clx_pkindx_style_t;\n+\n+/**\n+ * cvmx_pki_cl#_smem#\n+ *\n+ * This register initializes the SMEM, which configures the parse engine. These CSRs\n+ * are used by the PKI parse engine and other PKI hardware.\n+ *\n+ * Inside the SMEM are the following parse engine registers. These registers are the\n+ * preferred access method for software:\n+ * * PKI_CL()_STYLE()_CFG\n+ * * PKI_CL()_STYLE()_CFG2\n+ * * PKI_CL()_STYLE()_ALG\n+ *\n+ * To avoid overlapping addresses, these aliases have address bit 20 set in contrast to\n+ * this register; the PKI address decoder ignores bit 20 when accessing\n+ * PKI_CL()_SMEM().\n+ *\n+ * Software must reload the PKI_CL()_SMEM() registers upon the detection of\n+ * PKI_CL()_ECC_INT[SMEM_SBE] or PKI_CL()_ECC_INT[SMEM_DBE].\n+ *\n+ * For each legal j, PKI_CL(i)_SMEM(j) must be configured identically for i=0..1.\n+ */\n+union cvmx_pki_clx_smemx {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_smemx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 data : 32;\n+\t} s;\n+\tstruct cvmx_pki_clx_smemx_s cn73xx;\n+\tstruct cvmx_pki_clx_smemx_s cn78xx;\n+\tstruct cvmx_pki_clx_smemx_s cn78xxp1;\n+\tstruct cvmx_pki_clx_smemx_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_smemx cvmx_pki_clx_smemx_t;\n+\n+/**\n+ * cvmx_pki_cl#_start\n+ *\n+ * This register configures a cluster. All of PKI_CL()_START must be programmed identically.\n+ *\n+ */\n+union cvmx_pki_clx_start {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_start_s {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 start : 11;\n+\t} s;\n+\tstruct cvmx_pki_clx_start_s cn73xx;\n+\tstruct cvmx_pki_clx_start_s cn78xx;\n+\tstruct cvmx_pki_clx_start_s cn78xxp1;\n+\tstruct cvmx_pki_clx_start_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_start cvmx_pki_clx_start_t;\n+\n+/**\n+ * cvmx_pki_cl#_style#_alg\n+ *\n+ * This register is inside PKI_CL()_SMEM(). These CSRs are used only by\n+ * the PKI parse engine.\n+ *\n+ * For each legal j, PKI_CL(i)_STYLE(j)_ALG must be configured identically for i=0..1.\n+ */\n+union cvmx_pki_clx_stylex_alg {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_stylex_alg_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 tt : 2;\n+\t\tu64 apad_nip : 3;\n+\t\tu64 qpg_qos : 3;\n+\t\tu64 qpg_port_sh : 3;\n+\t\tu64 qpg_port_msb : 4;\n+\t\tu64 reserved_11_16 : 6;\n+\t\tu64 tag_vni : 1;\n+\t\tu64 tag_gtp : 1;\n+\t\tu64 tag_spi : 1;\n+\t\tu64 tag_syn : 1;\n+\t\tu64 tag_pctl : 1;\n+\t\tu64 tag_vs1 : 1;\n+\t\tu64 tag_vs0 : 1;\n+\t\tu64 tag_vlan : 1;\n+\t\tu64 tag_mpls0 : 1;\n+\t\tu64 tag_prt : 1;\n+\t\tu64 wqe_vs : 1;\n+\t} s;\n+\tstruct cvmx_pki_clx_stylex_alg_s cn73xx;\n+\tstruct cvmx_pki_clx_stylex_alg_s cn78xx;\n+\tstruct cvmx_pki_clx_stylex_alg_s cn78xxp1;\n+\tstruct cvmx_pki_clx_stylex_alg_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_stylex_alg cvmx_pki_clx_stylex_alg_t;\n+\n+/**\n+ * cvmx_pki_cl#_style#_cfg\n+ *\n+ * This register is inside PKI_CL()_SMEM(). These CSRs are used by\n+ * the PKI parse engine and other PKI hardware.\n+ *\n+ * For each legal j, PKI_CL(i)_STYLE(j)_CFG must be configured identically for i=0..1.\n+ */\n+union cvmx_pki_clx_stylex_cfg {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_stylex_cfg_s {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 ip6_udp_opt : 1;\n+\t\tu64 lenerr_en : 1;\n+\t\tu64 lenerr_eqpad : 1;\n+\t\tu64 minmax_sel : 1;\n+\t\tu64 maxerr_en : 1;\n+\t\tu64 minerr_en : 1;\n+\t\tu64 qpg_dis_grptag : 1;\n+\t\tu64 fcs_strip : 1;\n+\t\tu64 fcs_chk : 1;\n+\t\tu64 rawdrp : 1;\n+\t\tu64 drop : 1;\n+\t\tu64 nodrop : 1;\n+\t\tu64 qpg_dis_padd : 1;\n+\t\tu64 qpg_dis_grp : 1;\n+\t\tu64 qpg_dis_aura : 1;\n+\t\tu64 reserved_11_15 : 5;\n+\t\tu64 qpg_base : 11;\n+\t} s;\n+\tstruct cvmx_pki_clx_stylex_cfg_s cn73xx;\n+\tstruct cvmx_pki_clx_stylex_cfg_s cn78xx;\n+\tstruct cvmx_pki_clx_stylex_cfg_s cn78xxp1;\n+\tstruct cvmx_pki_clx_stylex_cfg_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_stylex_cfg cvmx_pki_clx_stylex_cfg_t;\n+\n+/**\n+ * cvmx_pki_cl#_style#_cfg2\n+ *\n+ * This register is inside PKI_CL()_SMEM(). These CSRs are used by\n+ * the PKI parse engine and other PKI hardware.\n+ *\n+ * For each legal j, PKI_CL(i)_STYLE(j)_CFG2 must be configured identically for i=0..1.\n+ */\n+union cvmx_pki_clx_stylex_cfg2 {\n+\tu64 u64;\n+\tstruct cvmx_pki_clx_stylex_cfg2_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 tag_inc : 4;\n+\t\tu64 reserved_25_27 : 3;\n+\t\tu64 tag_masken : 1;\n+\t\tu64 tag_src_lg : 1;\n+\t\tu64 tag_src_lf : 1;\n+\t\tu64 tag_src_le : 1;\n+\t\tu64 tag_src_ld : 1;\n+\t\tu64 tag_src_lc : 1;\n+\t\tu64 tag_src_lb : 1;\n+\t\tu64 tag_dst_lg : 1;\n+\t\tu64 tag_dst_lf : 1;\n+\t\tu64 tag_dst_le : 1;\n+\t\tu64 tag_dst_ld : 1;\n+\t\tu64 tag_dst_lc : 1;\n+\t\tu64 tag_dst_lb : 1;\n+\t\tu64 len_lg : 1;\n+\t\tu64 len_lf : 1;\n+\t\tu64 len_le : 1;\n+\t\tu64 len_ld : 1;\n+\t\tu64 len_lc : 1;\n+\t\tu64 len_lb : 1;\n+\t\tu64 csum_lg : 1;\n+\t\tu64 csum_lf : 1;\n+\t\tu64 csum_le : 1;\n+\t\tu64 csum_ld : 1;\n+\t\tu64 csum_lc : 1;\n+\t\tu64 csum_lb : 1;\n+\t} s;\n+\tstruct cvmx_pki_clx_stylex_cfg2_s cn73xx;\n+\tstruct cvmx_pki_clx_stylex_cfg2_s cn78xx;\n+\tstruct cvmx_pki_clx_stylex_cfg2_s cn78xxp1;\n+\tstruct cvmx_pki_clx_stylex_cfg2_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clx_stylex_cfg2 cvmx_pki_clx_stylex_cfg2_t;\n+\n+/**\n+ * cvmx_pki_clken\n+ */\n+union cvmx_pki_clken {\n+\tu64 u64;\n+\tstruct cvmx_pki_clken_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 clken : 1;\n+\t} s;\n+\tstruct cvmx_pki_clken_s cn73xx;\n+\tstruct cvmx_pki_clken_s cn78xx;\n+\tstruct cvmx_pki_clken_s cn78xxp1;\n+\tstruct cvmx_pki_clken_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_clken cvmx_pki_clken_t;\n+\n+/**\n+ * cvmx_pki_dstat#_stat0\n+ *\n+ * This register contains statistics indexed by PKI_QPG_TBLB()[DSTAT_ID].\n+ *\n+ */\n+union cvmx_pki_dstatx_stat0 {\n+\tu64 u64;\n+\tstruct cvmx_pki_dstatx_stat0_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 pkts : 32;\n+\t} s;\n+\tstruct cvmx_pki_dstatx_stat0_s cn73xx;\n+\tstruct cvmx_pki_dstatx_stat0_s cn78xx;\n+\tstruct cvmx_pki_dstatx_stat0_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_dstatx_stat0 cvmx_pki_dstatx_stat0_t;\n+\n+/**\n+ * cvmx_pki_dstat#_stat1\n+ *\n+ * This register contains statistics indexed by PKI_QPG_TBLB()[DSTAT_ID].\n+ *\n+ */\n+union cvmx_pki_dstatx_stat1 {\n+\tu64 u64;\n+\tstruct cvmx_pki_dstatx_stat1_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 octs : 40;\n+\t} s;\n+\tstruct cvmx_pki_dstatx_stat1_s cn73xx;\n+\tstruct cvmx_pki_dstatx_stat1_s cn78xx;\n+\tstruct cvmx_pki_dstatx_stat1_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_dstatx_stat1 cvmx_pki_dstatx_stat1_t;\n+\n+/**\n+ * cvmx_pki_dstat#_stat2\n+ *\n+ * This register contains statistics indexed by PKI_QPG_TBLB()[DSTAT_ID].\n+ *\n+ */\n+union cvmx_pki_dstatx_stat2 {\n+\tu64 u64;\n+\tstruct cvmx_pki_dstatx_stat2_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 err_pkts : 32;\n+\t} s;\n+\tstruct cvmx_pki_dstatx_stat2_s cn73xx;\n+\tstruct cvmx_pki_dstatx_stat2_s cn78xx;\n+\tstruct cvmx_pki_dstatx_stat2_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_dstatx_stat2 cvmx_pki_dstatx_stat2_t;\n+\n+/**\n+ * cvmx_pki_dstat#_stat3\n+ *\n+ * This register contains statistics indexed by PKI_QPG_TBLB()[DSTAT_ID].\n+ *\n+ */\n+union cvmx_pki_dstatx_stat3 {\n+\tu64 u64;\n+\tstruct cvmx_pki_dstatx_stat3_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 drp_pkts : 32;\n+\t} s;\n+\tstruct cvmx_pki_dstatx_stat3_s cn73xx;\n+\tstruct cvmx_pki_dstatx_stat3_s cn78xx;\n+\tstruct cvmx_pki_dstatx_stat3_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_dstatx_stat3 cvmx_pki_dstatx_stat3_t;\n+\n+/**\n+ * cvmx_pki_dstat#_stat4\n+ *\n+ * This register contains statistics indexed by PKI_QPG_TBLB()[DSTAT_ID].\n+ *\n+ */\n+union cvmx_pki_dstatx_stat4 {\n+\tu64 u64;\n+\tstruct cvmx_pki_dstatx_stat4_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 drp_octs : 40;\n+\t} s;\n+\tstruct cvmx_pki_dstatx_stat4_s cn73xx;\n+\tstruct cvmx_pki_dstatx_stat4_s cn78xx;\n+\tstruct cvmx_pki_dstatx_stat4_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_dstatx_stat4 cvmx_pki_dstatx_stat4_t;\n+\n+/**\n+ * cvmx_pki_ecc_ctl0\n+ *\n+ * This register allows inserting ECC errors for testing.\n+ *\n+ */\n+union cvmx_pki_ecc_ctl0 {\n+\tu64 u64;\n+\tstruct cvmx_pki_ecc_ctl0_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 ldfif_flip : 2;\n+\t\tu64 ldfif_cdis : 1;\n+\t\tu64 pbe_flip : 2;\n+\t\tu64 pbe_cdis : 1;\n+\t\tu64 wadr_flip : 2;\n+\t\tu64 wadr_cdis : 1;\n+\t\tu64 nxtptag_flip : 2;\n+\t\tu64 nxtptag_cdis : 1;\n+\t\tu64 curptag_flip : 2;\n+\t\tu64 curptag_cdis : 1;\n+\t\tu64 nxtblk_flip : 2;\n+\t\tu64 nxtblk_cdis : 1;\n+\t\tu64 kmem_flip : 2;\n+\t\tu64 kmem_cdis : 1;\n+\t\tu64 asm_flip : 2;\n+\t\tu64 asm_cdis : 1;\n+\t} s;\n+\tstruct cvmx_pki_ecc_ctl0_s cn73xx;\n+\tstruct cvmx_pki_ecc_ctl0_s cn78xx;\n+\tstruct cvmx_pki_ecc_ctl0_s cn78xxp1;\n+\tstruct cvmx_pki_ecc_ctl0_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_ecc_ctl0 cvmx_pki_ecc_ctl0_t;\n+\n+/**\n+ * cvmx_pki_ecc_ctl1\n+ *\n+ * This register allows inserting ECC errors for testing.\n+ *\n+ */\n+union cvmx_pki_ecc_ctl1 {\n+\tu64 u64;\n+\tstruct cvmx_pki_ecc_ctl1_s {\n+\t\tu64 reserved_51_63 : 13;\n+\t\tu64 sws_flip : 2;\n+\t\tu64 sws_cdis : 1;\n+\t\tu64 wqeout_flip : 2;\n+\t\tu64 wqeout_cdis : 1;\n+\t\tu64 doa_flip : 2;\n+\t\tu64 doa_cdis : 1;\n+\t\tu64 bpid_flip : 2;\n+\t\tu64 bpid_cdis : 1;\n+\t\tu64 reserved_30_38 : 9;\n+\t\tu64 plc_flip : 2;\n+\t\tu64 plc_cdis : 1;\n+\t\tu64 pktwq_flip : 2;\n+\t\tu64 pktwq_cdis : 1;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 stylewq2_flip : 2;\n+\t\tu64 stylewq2_cdis : 1;\n+\t\tu64 tag_flip : 2;\n+\t\tu64 tag_cdis : 1;\n+\t\tu64 aura_flip : 2;\n+\t\tu64 aura_cdis : 1;\n+\t\tu64 chan_flip : 2;\n+\t\tu64 chan_cdis : 1;\n+\t\tu64 pbtag_flip : 2;\n+\t\tu64 pbtag_cdis : 1;\n+\t\tu64 stylewq_flip : 2;\n+\t\tu64 stylewq_cdis : 1;\n+\t\tu64 qpg_flip : 2;\n+\t\tu64 qpg_cdis : 1;\n+\t} s;\n+\tstruct cvmx_pki_ecc_ctl1_s cn73xx;\n+\tstruct cvmx_pki_ecc_ctl1_s cn78xx;\n+\tstruct cvmx_pki_ecc_ctl1_cn78xxp1 {\n+\t\tu64 reserved_51_63 : 13;\n+\t\tu64 sws_flip : 2;\n+\t\tu64 sws_cdis : 1;\n+\t\tu64 wqeout_flip : 2;\n+\t\tu64 wqeout_cdis : 1;\n+\t\tu64 doa_flip : 2;\n+\t\tu64 doa_cdis : 1;\n+\t\tu64 bpid_flip : 2;\n+\t\tu64 bpid_cdis : 1;\n+\t\tu64 reserved_30_38 : 9;\n+\t\tu64 plc_flip : 2;\n+\t\tu64 plc_cdis : 1;\n+\t\tu64 pktwq_flip : 2;\n+\t\tu64 pktwq_cdis : 1;\n+\t\tu64 reserved_18_23 : 6;\n+\t\tu64 tag_flip : 2;\n+\t\tu64 tag_cdis : 1;\n+\t\tu64 aura_flip : 2;\n+\t\tu64 aura_cdis : 1;\n+\t\tu64 chan_flip : 2;\n+\t\tu64 chan_cdis : 1;\n+\t\tu64 pbtag_flip : 2;\n+\t\tu64 pbtag_cdis : 1;\n+\t\tu64 stylewq_flip : 2;\n+\t\tu64 stylewq_cdis : 1;\n+\t\tu64 qpg_flip : 2;\n+\t\tu64 qpg_cdis : 1;\n+\t} cn78xxp1;\n+\tstruct cvmx_pki_ecc_ctl1_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_ecc_ctl1 cvmx_pki_ecc_ctl1_t;\n+\n+/**\n+ * cvmx_pki_ecc_ctl2\n+ *\n+ * This register allows inserting ECC errors for testing.\n+ *\n+ */\n+union cvmx_pki_ecc_ctl2 {\n+\tu64 u64;\n+\tstruct cvmx_pki_ecc_ctl2_s {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 imem_flip : 2;\n+\t\tu64 imem_cdis : 1;\n+\t} s;\n+\tstruct cvmx_pki_ecc_ctl2_s cn73xx;\n+\tstruct cvmx_pki_ecc_ctl2_s cn78xx;\n+\tstruct cvmx_pki_ecc_ctl2_s cn78xxp1;\n+\tstruct cvmx_pki_ecc_ctl2_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_ecc_ctl2 cvmx_pki_ecc_ctl2_t;\n+\n+/**\n+ * cvmx_pki_ecc_int0\n+ */\n+union cvmx_pki_ecc_int0 {\n+\tu64 u64;\n+\tstruct cvmx_pki_ecc_int0_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 ldfif_dbe : 1;\n+\t\tu64 ldfif_sbe : 1;\n+\t\tu64 pbe_dbe : 1;\n+\t\tu64 pbe_sbe : 1;\n+\t\tu64 wadr_dbe : 1;\n+\t\tu64 wadr_sbe : 1;\n+\t\tu64 nxtptag_dbe : 1;\n+\t\tu64 nxtptag_sbe : 1;\n+\t\tu64 curptag_dbe : 1;\n+\t\tu64 curptag_sbe : 1;\n+\t\tu64 nxtblk_dbe : 1;\n+\t\tu64 nxtblk_sbe : 1;\n+\t\tu64 kmem_dbe : 1;\n+\t\tu64 kmem_sbe : 1;\n+\t\tu64 asm_dbe : 1;\n+\t\tu64 asm_sbe : 1;\n+\t} s;\n+\tstruct cvmx_pki_ecc_int0_s cn73xx;\n+\tstruct cvmx_pki_ecc_int0_s cn78xx;\n+\tstruct cvmx_pki_ecc_int0_s cn78xxp1;\n+\tstruct cvmx_pki_ecc_int0_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_ecc_int0 cvmx_pki_ecc_int0_t;\n+\n+/**\n+ * cvmx_pki_ecc_int1\n+ */\n+union cvmx_pki_ecc_int1 {\n+\tu64 u64;\n+\tstruct cvmx_pki_ecc_int1_s {\n+\t\tu64 reserved_34_63 : 30;\n+\t\tu64 sws_dbe : 1;\n+\t\tu64 sws_sbe : 1;\n+\t\tu64 wqeout_dbe : 1;\n+\t\tu64 wqeout_sbe : 1;\n+\t\tu64 doa_dbe : 1;\n+\t\tu64 doa_sbe : 1;\n+\t\tu64 bpid_dbe : 1;\n+\t\tu64 bpid_sbe : 1;\n+\t\tu64 reserved_20_25 : 6;\n+\t\tu64 plc_dbe : 1;\n+\t\tu64 plc_sbe : 1;\n+\t\tu64 pktwq_dbe : 1;\n+\t\tu64 pktwq_sbe : 1;\n+\t\tu64 reserved_12_15 : 4;\n+\t\tu64 tag_dbe : 1;\n+\t\tu64 tag_sbe : 1;\n+\t\tu64 aura_dbe : 1;\n+\t\tu64 aura_sbe : 1;\n+\t\tu64 chan_dbe : 1;\n+\t\tu64 chan_sbe : 1;\n+\t\tu64 pbtag_dbe : 1;\n+\t\tu64 pbtag_sbe : 1;\n+\t\tu64 stylewq_dbe : 1;\n+\t\tu64 stylewq_sbe : 1;\n+\t\tu64 qpg_dbe : 1;\n+\t\tu64 qpg_sbe : 1;\n+\t} s;\n+\tstruct cvmx_pki_ecc_int1_s cn73xx;\n+\tstruct cvmx_pki_ecc_int1_s cn78xx;\n+\tstruct cvmx_pki_ecc_int1_s cn78xxp1;\n+\tstruct cvmx_pki_ecc_int1_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_ecc_int1 cvmx_pki_ecc_int1_t;\n+\n+/**\n+ * cvmx_pki_ecc_int2\n+ */\n+union cvmx_pki_ecc_int2 {\n+\tu64 u64;\n+\tstruct cvmx_pki_ecc_int2_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 imem_dbe : 1;\n+\t\tu64 imem_sbe : 1;\n+\t} s;\n+\tstruct cvmx_pki_ecc_int2_s cn73xx;\n+\tstruct cvmx_pki_ecc_int2_s cn78xx;\n+\tstruct cvmx_pki_ecc_int2_s cn78xxp1;\n+\tstruct cvmx_pki_ecc_int2_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_ecc_int2 cvmx_pki_ecc_int2_t;\n+\n+/**\n+ * cvmx_pki_frm_len_chk#\n+ */\n+union cvmx_pki_frm_len_chkx {\n+\tu64 u64;\n+\tstruct cvmx_pki_frm_len_chkx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 maxlen : 16;\n+\t\tu64 minlen : 16;\n+\t} s;\n+\tstruct cvmx_pki_frm_len_chkx_s cn73xx;\n+\tstruct cvmx_pki_frm_len_chkx_s cn78xx;\n+\tstruct cvmx_pki_frm_len_chkx_s cn78xxp1;\n+\tstruct cvmx_pki_frm_len_chkx_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_frm_len_chkx cvmx_pki_frm_len_chkx_t;\n+\n+/**\n+ * cvmx_pki_gbl_pen\n+ *\n+ * This register contains global configuration information that applies to all\n+ * pkinds. The values are opaque to PKI HW.\n+ *\n+ * This is intended for communication between the higher-level software SDK, and the\n+ * SDK code that loads PKI_IMEM() with the parse engine code. This allows the loader to\n+ * appropriately select the parse engine code with only those features required, so that\n+ * performance will be optimized.\n+ */\n+union cvmx_pki_gbl_pen {\n+\tu64 u64;\n+\tstruct cvmx_pki_gbl_pen_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 virt_pen : 1;\n+\t\tu64 clg_pen : 1;\n+\t\tu64 cl2_pen : 1;\n+\t\tu64 l4_pen : 1;\n+\t\tu64 il3_pen : 1;\n+\t\tu64 l3_pen : 1;\n+\t\tu64 mpls_pen : 1;\n+\t\tu64 fulc_pen : 1;\n+\t\tu64 dsa_pen : 1;\n+\t\tu64 hg_pen : 1;\n+\t} s;\n+\tstruct cvmx_pki_gbl_pen_s cn73xx;\n+\tstruct cvmx_pki_gbl_pen_s cn78xx;\n+\tstruct cvmx_pki_gbl_pen_s cn78xxp1;\n+\tstruct cvmx_pki_gbl_pen_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_gbl_pen cvmx_pki_gbl_pen_t;\n+\n+/**\n+ * cvmx_pki_gen_int\n+ */\n+union cvmx_pki_gen_int {\n+\tu64 u64;\n+\tstruct cvmx_pki_gen_int_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 bufs_oflow : 1;\n+\t\tu64 pkt_size_oflow : 1;\n+\t\tu64 x2p_req_ofl : 1;\n+\t\tu64 drp_noavail : 1;\n+\t\tu64 dat : 1;\n+\t\tu64 eop : 1;\n+\t\tu64 sop : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 crcerr : 1;\n+\t\tu64 pktdrp : 1;\n+\t} s;\n+\tstruct cvmx_pki_gen_int_s cn73xx;\n+\tstruct cvmx_pki_gen_int_s cn78xx;\n+\tstruct cvmx_pki_gen_int_cn78xxp1 {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 x2p_req_ofl : 1;\n+\t\tu64 drp_noavail : 1;\n+\t\tu64 dat : 1;\n+\t\tu64 eop : 1;\n+\t\tu64 sop : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 crcerr : 1;\n+\t\tu64 pktdrp : 1;\n+\t} cn78xxp1;\n+\tstruct cvmx_pki_gen_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_gen_int cvmx_pki_gen_int_t;\n+\n+/**\n+ * cvmx_pki_icg#_cfg\n+ *\n+ * This register configures the cluster group.\n+ *\n+ */\n+union cvmx_pki_icgx_cfg {\n+\tu64 u64;\n+\tstruct cvmx_pki_icgx_cfg_s {\n+\t\tu64 reserved_53_63 : 11;\n+\t\tu64 maxipe_use : 5;\n+\t\tu64 reserved_36_47 : 12;\n+\t\tu64 clusters : 4;\n+\t\tu64 reserved_27_31 : 5;\n+\t\tu64 release_rqd : 1;\n+\t\tu64 mlo : 1;\n+\t\tu64 pena : 1;\n+\t\tu64 timer : 12;\n+\t\tu64 delay : 12;\n+\t} s;\n+\tstruct cvmx_pki_icgx_cfg_s cn73xx;\n+\tstruct cvmx_pki_icgx_cfg_s cn78xx;\n+\tstruct cvmx_pki_icgx_cfg_s cn78xxp1;\n+\tstruct cvmx_pki_icgx_cfg_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_icgx_cfg cvmx_pki_icgx_cfg_t;\n+\n+/**\n+ * cvmx_pki_imem#\n+ */\n+union cvmx_pki_imemx {\n+\tu64 u64;\n+\tstruct cvmx_pki_imemx_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_pki_imemx_s cn73xx;\n+\tstruct cvmx_pki_imemx_s cn78xx;\n+\tstruct cvmx_pki_imemx_s cn78xxp1;\n+\tstruct cvmx_pki_imemx_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_imemx cvmx_pki_imemx_t;\n+\n+/**\n+ * cvmx_pki_ltype#_map\n+ *\n+ * This register is the layer type map, indexed by PKI_LTYPE_E.\n+ *\n+ */\n+union cvmx_pki_ltypex_map {\n+\tu64 u64;\n+\tstruct cvmx_pki_ltypex_map_s {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 beltype : 3;\n+\t} s;\n+\tstruct cvmx_pki_ltypex_map_s cn73xx;\n+\tstruct cvmx_pki_ltypex_map_s cn78xx;\n+\tstruct cvmx_pki_ltypex_map_s cn78xxp1;\n+\tstruct cvmx_pki_ltypex_map_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_ltypex_map cvmx_pki_ltypex_map_t;\n+\n+/**\n+ * cvmx_pki_pbe_eco\n+ */\n+union cvmx_pki_pbe_eco {\n+\tu64 u64;\n+\tstruct cvmx_pki_pbe_eco_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 eco_rw : 32;\n+\t} s;\n+\tstruct cvmx_pki_pbe_eco_s cn73xx;\n+\tstruct cvmx_pki_pbe_eco_s cn78xx;\n+\tstruct cvmx_pki_pbe_eco_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_pbe_eco cvmx_pki_pbe_eco_t;\n+\n+/**\n+ * cvmx_pki_pcam_lookup\n+ *\n+ * For diagnostic use only, this register performs a PCAM lookup against the provided\n+ * cluster and PCAM instance and loads results into PKI_PCAM_RESULT.\n+ */\n+union cvmx_pki_pcam_lookup {\n+\tu64 u64;\n+\tstruct cvmx_pki_pcam_lookup_s {\n+\t\tu64 reserved_54_63 : 10;\n+\t\tu64 cl : 2;\n+\t\tu64 reserved_49_51 : 3;\n+\t\tu64 pcam : 1;\n+\t\tu64 term : 8;\n+\t\tu64 style : 8;\n+\t\tu64 data : 32;\n+\t} s;\n+\tstruct cvmx_pki_pcam_lookup_s cn73xx;\n+\tstruct cvmx_pki_pcam_lookup_s cn78xx;\n+\tstruct cvmx_pki_pcam_lookup_s cn78xxp1;\n+\tstruct cvmx_pki_pcam_lookup_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_pcam_lookup cvmx_pki_pcam_lookup_t;\n+\n+/**\n+ * cvmx_pki_pcam_result\n+ *\n+ * For diagnostic use only, this register returns PCAM results for the most recent write to\n+ * PKI_PCAM_LOOKUP. The read will stall until the lookup is completed.\n+ * PKI_CL()_ECC_CTL[PCAM_EN] must be clear before accessing this register. Read stall\n+ * is implemented by delaying the PKI_PCAM_LOOKUP write acknowledge until the PCAM is\n+ * free and the lookup can be issued.\n+ */\n+union cvmx_pki_pcam_result {\n+\tu64 u64;\n+\tstruct cvmx_pki_pcam_result_s {\n+\t\tu64 reserved_41_63 : 23;\n+\t\tu64 match : 1;\n+\t\tu64 entry : 8;\n+\t\tu64 result : 32;\n+\t} s;\n+\tstruct cvmx_pki_pcam_result_cn73xx {\n+\t\tu64 conflict : 1;\n+\t\tu64 reserved_41_62 : 22;\n+\t\tu64 match : 1;\n+\t\tu64 entry : 8;\n+\t\tu64 result : 32;\n+\t} cn73xx;\n+\tstruct cvmx_pki_pcam_result_cn73xx cn78xx;\n+\tstruct cvmx_pki_pcam_result_cn73xx cn78xxp1;\n+\tstruct cvmx_pki_pcam_result_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pki_pcam_result cvmx_pki_pcam_result_t;\n+\n+/**\n+ * cvmx_pki_pfe_diag\n+ */\n+union cvmx_pki_pfe_diag {\n+\tu64 u64;\n+\tstruct cvmx_pki_pfe_diag_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 bad_rid : 1;\n+\t} s;\n+\tstruct cvmx_pki_pfe_diag_s cn73xx;\n+\tstruct cvmx_pki_pfe_diag_s cn78xx;\n+\tstruct cvmx_pki_pfe_diag_s cn78xxp1;\n+\tstruct cvmx_pki_pfe_diag_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_pfe_diag cvmx_pki_pfe_diag_t;\n+\n+/**\n+ * cvmx_pki_pfe_eco\n+ */\n+union cvmx_pki_pfe_eco {\n+\tu64 u64;\n+\tstruct cvmx_pki_pfe_eco_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 eco_rw : 32;\n+\t} s;\n+\tstruct cvmx_pki_pfe_eco_s cn73xx;\n+\tstruct cvmx_pki_pfe_eco_s cn78xx;\n+\tstruct cvmx_pki_pfe_eco_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_pfe_eco cvmx_pki_pfe_eco_t;\n+\n+/**\n+ * cvmx_pki_pix_clken\n+ */\n+union cvmx_pki_pix_clken {\n+\tu64 u64;\n+\tstruct cvmx_pki_pix_clken_s {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 mech : 1;\n+\t\tu64 reserved_4_15 : 12;\n+\t\tu64 cls : 4;\n+\t} s;\n+\tstruct cvmx_pki_pix_clken_s cn73xx;\n+\tstruct cvmx_pki_pix_clken_s cn78xx;\n+\tstruct cvmx_pki_pix_clken_s cn78xxp1;\n+\tstruct cvmx_pki_pix_clken_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_pix_clken cvmx_pki_pix_clken_t;\n+\n+/**\n+ * cvmx_pki_pix_diag\n+ */\n+union cvmx_pki_pix_diag {\n+\tu64 u64;\n+\tstruct cvmx_pki_pix_diag_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 nosched : 4;\n+\t} s;\n+\tstruct cvmx_pki_pix_diag_s cn73xx;\n+\tstruct cvmx_pki_pix_diag_s cn78xx;\n+\tstruct cvmx_pki_pix_diag_s cn78xxp1;\n+\tstruct cvmx_pki_pix_diag_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_pix_diag cvmx_pki_pix_diag_t;\n+\n+/**\n+ * cvmx_pki_pix_eco\n+ */\n+union cvmx_pki_pix_eco {\n+\tu64 u64;\n+\tstruct cvmx_pki_pix_eco_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 eco_rw : 32;\n+\t} s;\n+\tstruct cvmx_pki_pix_eco_s cn73xx;\n+\tstruct cvmx_pki_pix_eco_s cn78xx;\n+\tstruct cvmx_pki_pix_eco_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_pix_eco cvmx_pki_pix_eco_t;\n+\n+/**\n+ * cvmx_pki_pkind#_icgsel\n+ */\n+union cvmx_pki_pkindx_icgsel {\n+\tu64 u64;\n+\tstruct cvmx_pki_pkindx_icgsel_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 icg : 2;\n+\t} s;\n+\tstruct cvmx_pki_pkindx_icgsel_s cn73xx;\n+\tstruct cvmx_pki_pkindx_icgsel_s cn78xx;\n+\tstruct cvmx_pki_pkindx_icgsel_s cn78xxp1;\n+\tstruct cvmx_pki_pkindx_icgsel_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_pkindx_icgsel cvmx_pki_pkindx_icgsel_t;\n+\n+/**\n+ * cvmx_pki_pknd#_inb_stat0\n+ *\n+ * This register counts inbound statistics, indexed by pkind.\n+ *\n+ */\n+union cvmx_pki_pkndx_inb_stat0 {\n+\tu64 u64;\n+\tstruct cvmx_pki_pkndx_inb_stat0_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 pkts : 48;\n+\t} s;\n+\tstruct cvmx_pki_pkndx_inb_stat0_s cn73xx;\n+\tstruct cvmx_pki_pkndx_inb_stat0_s cn78xx;\n+\tstruct cvmx_pki_pkndx_inb_stat0_s cn78xxp1;\n+\tstruct cvmx_pki_pkndx_inb_stat0_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_pkndx_inb_stat0 cvmx_pki_pkndx_inb_stat0_t;\n+\n+/**\n+ * cvmx_pki_pknd#_inb_stat1\n+ *\n+ * This register counts inbound statistics, indexed by pkind.\n+ *\n+ */\n+union cvmx_pki_pkndx_inb_stat1 {\n+\tu64 u64;\n+\tstruct cvmx_pki_pkndx_inb_stat1_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 octs : 48;\n+\t} s;\n+\tstruct cvmx_pki_pkndx_inb_stat1_s cn73xx;\n+\tstruct cvmx_pki_pkndx_inb_stat1_s cn78xx;\n+\tstruct cvmx_pki_pkndx_inb_stat1_s cn78xxp1;\n+\tstruct cvmx_pki_pkndx_inb_stat1_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_pkndx_inb_stat1 cvmx_pki_pkndx_inb_stat1_t;\n+\n+/**\n+ * cvmx_pki_pknd#_inb_stat2\n+ *\n+ * This register counts inbound statistics, indexed by pkind.\n+ *\n+ */\n+union cvmx_pki_pkndx_inb_stat2 {\n+\tu64 u64;\n+\tstruct cvmx_pki_pkndx_inb_stat2_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 errs : 48;\n+\t} s;\n+\tstruct cvmx_pki_pkndx_inb_stat2_s cn73xx;\n+\tstruct cvmx_pki_pkndx_inb_stat2_s cn78xx;\n+\tstruct cvmx_pki_pkndx_inb_stat2_s cn78xxp1;\n+\tstruct cvmx_pki_pkndx_inb_stat2_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_pkndx_inb_stat2 cvmx_pki_pkndx_inb_stat2_t;\n+\n+/**\n+ * cvmx_pki_pkt_err\n+ */\n+union cvmx_pki_pkt_err {\n+\tu64 u64;\n+\tstruct cvmx_pki_pkt_err_s {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 reasm : 7;\n+\t} s;\n+\tstruct cvmx_pki_pkt_err_s cn73xx;\n+\tstruct cvmx_pki_pkt_err_s cn78xx;\n+\tstruct cvmx_pki_pkt_err_s cn78xxp1;\n+\tstruct cvmx_pki_pkt_err_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_pkt_err cvmx_pki_pkt_err_t;\n+\n+/**\n+ * cvmx_pki_ptag_avail\n+ *\n+ * For diagnostic use only.\n+ *\n+ */\n+union cvmx_pki_ptag_avail {\n+\tu64 u64;\n+\tstruct cvmx_pki_ptag_avail_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 avail : 8;\n+\t} s;\n+\tstruct cvmx_pki_ptag_avail_s cn73xx;\n+\tstruct cvmx_pki_ptag_avail_s cn78xx;\n+\tstruct cvmx_pki_ptag_avail_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_ptag_avail cvmx_pki_ptag_avail_t;\n+\n+/**\n+ * cvmx_pki_qpg_tbl#\n+ *\n+ * These registers are used by PKI BE to indirectly calculate the Portadd/Aura/Group\n+ * from the Diffsrv, HiGig or VLAN information as described in QPG. See also\n+ * PKI_QPG_TBLB().\n+ */\n+union cvmx_pki_qpg_tblx {\n+\tu64 u64;\n+\tstruct cvmx_pki_qpg_tblx_s {\n+\t\tu64 reserved_60_63 : 4;\n+\t\tu64 padd : 12;\n+\t\tu64 grptag_ok : 3;\n+\t\tu64 reserved_42_44 : 3;\n+\t\tu64 grp_ok : 10;\n+\t\tu64 grptag_bad : 3;\n+\t\tu64 reserved_26_28 : 3;\n+\t\tu64 grp_bad : 10;\n+\t\tu64 reserved_12_15 : 4;\n+\t\tu64 aura_node : 2;\n+\t\tu64 laura : 10;\n+\t} s;\n+\tstruct cvmx_pki_qpg_tblx_s cn73xx;\n+\tstruct cvmx_pki_qpg_tblx_s cn78xx;\n+\tstruct cvmx_pki_qpg_tblx_s cn78xxp1;\n+\tstruct cvmx_pki_qpg_tblx_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_qpg_tblx cvmx_pki_qpg_tblx_t;\n+\n+/**\n+ * cvmx_pki_qpg_tblb#\n+ *\n+ * This register configures the QPG table. See also PKI_QPG_TBL().\n+ *\n+ */\n+union cvmx_pki_qpg_tblbx {\n+\tu64 u64;\n+\tstruct cvmx_pki_qpg_tblbx_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 dstat_id : 10;\n+\t} s;\n+\tstruct cvmx_pki_qpg_tblbx_s cn73xx;\n+\tstruct cvmx_pki_qpg_tblbx_s cn78xx;\n+\tstruct cvmx_pki_qpg_tblbx_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_qpg_tblbx cvmx_pki_qpg_tblbx_t;\n+\n+/**\n+ * cvmx_pki_reasm_sop#\n+ */\n+union cvmx_pki_reasm_sopx {\n+\tu64 u64;\n+\tstruct cvmx_pki_reasm_sopx_s {\n+\t\tu64 sop : 64;\n+\t} s;\n+\tstruct cvmx_pki_reasm_sopx_s cn73xx;\n+\tstruct cvmx_pki_reasm_sopx_s cn78xx;\n+\tstruct cvmx_pki_reasm_sopx_s cn78xxp1;\n+\tstruct cvmx_pki_reasm_sopx_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_reasm_sopx cvmx_pki_reasm_sopx_t;\n+\n+/**\n+ * cvmx_pki_req_wgt\n+ *\n+ * This register controls the round-robin weights between each PKI requestor. For diagnostic\n+ * tuning only.\n+ */\n+union cvmx_pki_req_wgt {\n+\tu64 u64;\n+\tstruct cvmx_pki_req_wgt_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 wgt8 : 4;\n+\t\tu64 wgt7 : 4;\n+\t\tu64 wgt6 : 4;\n+\t\tu64 wgt5 : 4;\n+\t\tu64 wgt4 : 4;\n+\t\tu64 wgt3 : 4;\n+\t\tu64 wgt2 : 4;\n+\t\tu64 wgt1 : 4;\n+\t\tu64 wgt0 : 4;\n+\t} s;\n+\tstruct cvmx_pki_req_wgt_s cn73xx;\n+\tstruct cvmx_pki_req_wgt_s cn78xx;\n+\tstruct cvmx_pki_req_wgt_s cn78xxp1;\n+\tstruct cvmx_pki_req_wgt_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_req_wgt cvmx_pki_req_wgt_t;\n+\n+/**\n+ * cvmx_pki_sft_rst\n+ */\n+union cvmx_pki_sft_rst {\n+\tu64 u64;\n+\tstruct cvmx_pki_sft_rst_s {\n+\t\tu64 busy : 1;\n+\t\tu64 reserved_33_62 : 30;\n+\t\tu64 active : 1;\n+\t\tu64 reserved_1_31 : 31;\n+\t\tu64 rst : 1;\n+\t} s;\n+\tstruct cvmx_pki_sft_rst_s cn73xx;\n+\tstruct cvmx_pki_sft_rst_s cn78xx;\n+\tstruct cvmx_pki_sft_rst_s cn78xxp1;\n+\tstruct cvmx_pki_sft_rst_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_sft_rst cvmx_pki_sft_rst_t;\n+\n+/**\n+ * cvmx_pki_stat#_hist0\n+ */\n+union cvmx_pki_statx_hist0 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_hist0_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 h1to63 : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_hist0_s cn73xx;\n+\tstruct cvmx_pki_statx_hist0_s cn78xx;\n+\tstruct cvmx_pki_statx_hist0_s cn78xxp1;\n+\tstruct cvmx_pki_statx_hist0_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_hist0 cvmx_pki_statx_hist0_t;\n+\n+/**\n+ * cvmx_pki_stat#_hist1\n+ */\n+union cvmx_pki_statx_hist1 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_hist1_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 h64to127 : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_hist1_s cn73xx;\n+\tstruct cvmx_pki_statx_hist1_s cn78xx;\n+\tstruct cvmx_pki_statx_hist1_s cn78xxp1;\n+\tstruct cvmx_pki_statx_hist1_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_hist1 cvmx_pki_statx_hist1_t;\n+\n+/**\n+ * cvmx_pki_stat#_hist2\n+ */\n+union cvmx_pki_statx_hist2 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_hist2_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 h128to255 : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_hist2_s cn73xx;\n+\tstruct cvmx_pki_statx_hist2_s cn78xx;\n+\tstruct cvmx_pki_statx_hist2_s cn78xxp1;\n+\tstruct cvmx_pki_statx_hist2_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_hist2 cvmx_pki_statx_hist2_t;\n+\n+/**\n+ * cvmx_pki_stat#_hist3\n+ */\n+union cvmx_pki_statx_hist3 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_hist3_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 h256to511 : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_hist3_s cn73xx;\n+\tstruct cvmx_pki_statx_hist3_s cn78xx;\n+\tstruct cvmx_pki_statx_hist3_s cn78xxp1;\n+\tstruct cvmx_pki_statx_hist3_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_hist3 cvmx_pki_statx_hist3_t;\n+\n+/**\n+ * cvmx_pki_stat#_hist4\n+ */\n+union cvmx_pki_statx_hist4 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_hist4_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 h512to1023 : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_hist4_s cn73xx;\n+\tstruct cvmx_pki_statx_hist4_s cn78xx;\n+\tstruct cvmx_pki_statx_hist4_s cn78xxp1;\n+\tstruct cvmx_pki_statx_hist4_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_hist4 cvmx_pki_statx_hist4_t;\n+\n+/**\n+ * cvmx_pki_stat#_hist5\n+ */\n+union cvmx_pki_statx_hist5 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_hist5_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 h1024to1518 : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_hist5_s cn73xx;\n+\tstruct cvmx_pki_statx_hist5_s cn78xx;\n+\tstruct cvmx_pki_statx_hist5_s cn78xxp1;\n+\tstruct cvmx_pki_statx_hist5_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_hist5 cvmx_pki_statx_hist5_t;\n+\n+/**\n+ * cvmx_pki_stat#_hist6\n+ */\n+union cvmx_pki_statx_hist6 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_hist6_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 h1519 : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_hist6_s cn73xx;\n+\tstruct cvmx_pki_statx_hist6_s cn78xx;\n+\tstruct cvmx_pki_statx_hist6_s cn78xxp1;\n+\tstruct cvmx_pki_statx_hist6_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_hist6 cvmx_pki_statx_hist6_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat0\n+ */\n+union cvmx_pki_statx_stat0 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat0_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 pkts : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat0_s cn73xx;\n+\tstruct cvmx_pki_statx_stat0_s cn78xx;\n+\tstruct cvmx_pki_statx_stat0_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat0_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat0 cvmx_pki_statx_stat0_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat1\n+ */\n+union cvmx_pki_statx_stat1 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat1_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 octs : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat1_s cn73xx;\n+\tstruct cvmx_pki_statx_stat1_s cn78xx;\n+\tstruct cvmx_pki_statx_stat1_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat1_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat1 cvmx_pki_statx_stat1_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat10\n+ */\n+union cvmx_pki_statx_stat10 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat10_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 jabber : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat10_s cn73xx;\n+\tstruct cvmx_pki_statx_stat10_s cn78xx;\n+\tstruct cvmx_pki_statx_stat10_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat10_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat10 cvmx_pki_statx_stat10_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat11\n+ */\n+union cvmx_pki_statx_stat11 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat11_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 oversz : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat11_s cn73xx;\n+\tstruct cvmx_pki_statx_stat11_s cn78xx;\n+\tstruct cvmx_pki_statx_stat11_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat11_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat11 cvmx_pki_statx_stat11_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat12\n+ */\n+union cvmx_pki_statx_stat12 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat12_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 l2err : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat12_s cn73xx;\n+\tstruct cvmx_pki_statx_stat12_s cn78xx;\n+\tstruct cvmx_pki_statx_stat12_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat12_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat12 cvmx_pki_statx_stat12_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat13\n+ */\n+union cvmx_pki_statx_stat13 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat13_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 spec : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat13_s cn73xx;\n+\tstruct cvmx_pki_statx_stat13_s cn78xx;\n+\tstruct cvmx_pki_statx_stat13_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat13_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat13 cvmx_pki_statx_stat13_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat14\n+ */\n+union cvmx_pki_statx_stat14 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat14_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 drp_bcast : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat14_s cn73xx;\n+\tstruct cvmx_pki_statx_stat14_s cn78xx;\n+\tstruct cvmx_pki_statx_stat14_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat14_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat14 cvmx_pki_statx_stat14_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat15\n+ */\n+union cvmx_pki_statx_stat15 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat15_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 drp_mcast : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat15_s cn73xx;\n+\tstruct cvmx_pki_statx_stat15_s cn78xx;\n+\tstruct cvmx_pki_statx_stat15_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat15_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat15 cvmx_pki_statx_stat15_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat16\n+ */\n+union cvmx_pki_statx_stat16 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat16_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 drp_bcast : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat16_s cn73xx;\n+\tstruct cvmx_pki_statx_stat16_s cn78xx;\n+\tstruct cvmx_pki_statx_stat16_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat16_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat16 cvmx_pki_statx_stat16_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat17\n+ */\n+union cvmx_pki_statx_stat17 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat17_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 drp_mcast : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat17_s cn73xx;\n+\tstruct cvmx_pki_statx_stat17_s cn78xx;\n+\tstruct cvmx_pki_statx_stat17_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat17_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat17 cvmx_pki_statx_stat17_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat18\n+ */\n+union cvmx_pki_statx_stat18 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat18_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 drp_spec : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat18_s cn73xx;\n+\tstruct cvmx_pki_statx_stat18_s cn78xx;\n+\tstruct cvmx_pki_statx_stat18_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat18_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat18 cvmx_pki_statx_stat18_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat2\n+ */\n+union cvmx_pki_statx_stat2 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat2_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 raw : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat2_s cn73xx;\n+\tstruct cvmx_pki_statx_stat2_s cn78xx;\n+\tstruct cvmx_pki_statx_stat2_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat2_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat2 cvmx_pki_statx_stat2_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat3\n+ */\n+union cvmx_pki_statx_stat3 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat3_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 drp_pkts : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat3_s cn73xx;\n+\tstruct cvmx_pki_statx_stat3_s cn78xx;\n+\tstruct cvmx_pki_statx_stat3_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat3_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat3 cvmx_pki_statx_stat3_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat4\n+ */\n+union cvmx_pki_statx_stat4 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat4_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 drp_octs : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat4_s cn73xx;\n+\tstruct cvmx_pki_statx_stat4_s cn78xx;\n+\tstruct cvmx_pki_statx_stat4_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat4_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat4 cvmx_pki_statx_stat4_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat5\n+ */\n+union cvmx_pki_statx_stat5 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat5_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 bcast : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat5_s cn73xx;\n+\tstruct cvmx_pki_statx_stat5_s cn78xx;\n+\tstruct cvmx_pki_statx_stat5_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat5_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat5 cvmx_pki_statx_stat5_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat6\n+ */\n+union cvmx_pki_statx_stat6 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat6_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 mcast : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat6_s cn73xx;\n+\tstruct cvmx_pki_statx_stat6_s cn78xx;\n+\tstruct cvmx_pki_statx_stat6_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat6_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat6 cvmx_pki_statx_stat6_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat7\n+ */\n+union cvmx_pki_statx_stat7 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat7_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 fcs : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat7_s cn73xx;\n+\tstruct cvmx_pki_statx_stat7_s cn78xx;\n+\tstruct cvmx_pki_statx_stat7_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat7_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat7 cvmx_pki_statx_stat7_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat8\n+ */\n+union cvmx_pki_statx_stat8 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat8_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 frag : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat8_s cn73xx;\n+\tstruct cvmx_pki_statx_stat8_s cn78xx;\n+\tstruct cvmx_pki_statx_stat8_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat8_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat8 cvmx_pki_statx_stat8_t;\n+\n+/**\n+ * cvmx_pki_stat#_stat9\n+ */\n+union cvmx_pki_statx_stat9 {\n+\tu64 u64;\n+\tstruct cvmx_pki_statx_stat9_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 undersz : 48;\n+\t} s;\n+\tstruct cvmx_pki_statx_stat9_s cn73xx;\n+\tstruct cvmx_pki_statx_stat9_s cn78xx;\n+\tstruct cvmx_pki_statx_stat9_s cn78xxp1;\n+\tstruct cvmx_pki_statx_stat9_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_statx_stat9 cvmx_pki_statx_stat9_t;\n+\n+/**\n+ * cvmx_pki_stat_ctl\n+ *\n+ * This register controls how the PKI statistics counters are handled.\n+ *\n+ */\n+union cvmx_pki_stat_ctl {\n+\tu64 u64;\n+\tstruct cvmx_pki_stat_ctl_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 mode : 2;\n+\t} s;\n+\tstruct cvmx_pki_stat_ctl_s cn73xx;\n+\tstruct cvmx_pki_stat_ctl_s cn78xx;\n+\tstruct cvmx_pki_stat_ctl_s cn78xxp1;\n+\tstruct cvmx_pki_stat_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_stat_ctl cvmx_pki_stat_ctl_t;\n+\n+/**\n+ * cvmx_pki_style#_buf\n+ *\n+ * This register configures the PKI BE skip amounts and other information.\n+ * It is indexed by final style, PKI_WQE_S[STYLE]<5:0>.\n+ */\n+union cvmx_pki_stylex_buf {\n+\tu64 u64;\n+\tstruct cvmx_pki_stylex_buf_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 pkt_lend : 1;\n+\t\tu64 wqe_hsz : 2;\n+\t\tu64 wqe_skip : 2;\n+\t\tu64 first_skip : 6;\n+\t\tu64 later_skip : 6;\n+\t\tu64 opc_mode : 2;\n+\t\tu64 dis_wq_dat : 1;\n+\t\tu64 mb_size : 13;\n+\t} s;\n+\tstruct cvmx_pki_stylex_buf_s cn73xx;\n+\tstruct cvmx_pki_stylex_buf_s cn78xx;\n+\tstruct cvmx_pki_stylex_buf_s cn78xxp1;\n+\tstruct cvmx_pki_stylex_buf_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_stylex_buf cvmx_pki_stylex_buf_t;\n+\n+/**\n+ * cvmx_pki_style#_tag_mask\n+ *\n+ * This register configures the PKI BE tag algorithm.\n+ * It is indexed by final style, PKI_WQE_S[STYLE]<5:0>.\n+ */\n+union cvmx_pki_stylex_tag_mask {\n+\tu64 u64;\n+\tstruct cvmx_pki_stylex_tag_mask_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 mask : 16;\n+\t} s;\n+\tstruct cvmx_pki_stylex_tag_mask_s cn73xx;\n+\tstruct cvmx_pki_stylex_tag_mask_s cn78xx;\n+\tstruct cvmx_pki_stylex_tag_mask_s cn78xxp1;\n+\tstruct cvmx_pki_stylex_tag_mask_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_stylex_tag_mask cvmx_pki_stylex_tag_mask_t;\n+\n+/**\n+ * cvmx_pki_style#_tag_sel\n+ *\n+ * This register configures the PKI BE tag algorithm.\n+ * It is indexed by final style, PKI_WQE_S[STYLE]<5:0>.\n+ */\n+union cvmx_pki_stylex_tag_sel {\n+\tu64 u64;\n+\tstruct cvmx_pki_stylex_tag_sel_s {\n+\t\tu64 reserved_27_63 : 37;\n+\t\tu64 tag_idx3 : 3;\n+\t\tu64 reserved_19_23 : 5;\n+\t\tu64 tag_idx2 : 3;\n+\t\tu64 reserved_11_15 : 5;\n+\t\tu64 tag_idx1 : 3;\n+\t\tu64 reserved_3_7 : 5;\n+\t\tu64 tag_idx0 : 3;\n+\t} s;\n+\tstruct cvmx_pki_stylex_tag_sel_s cn73xx;\n+\tstruct cvmx_pki_stylex_tag_sel_s cn78xx;\n+\tstruct cvmx_pki_stylex_tag_sel_s cn78xxp1;\n+\tstruct cvmx_pki_stylex_tag_sel_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_stylex_tag_sel cvmx_pki_stylex_tag_sel_t;\n+\n+/**\n+ * cvmx_pki_style#_wq2\n+ *\n+ * This register configures the PKI BE WQE generation.\n+ * It is indexed by final style, PKI_WQE_S[STYLE]<5:0>.\n+ */\n+union cvmx_pki_stylex_wq2 {\n+\tu64 u64;\n+\tstruct cvmx_pki_stylex_wq2_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_pki_stylex_wq2_s cn73xx;\n+\tstruct cvmx_pki_stylex_wq2_s cn78xx;\n+\tstruct cvmx_pki_stylex_wq2_s cn78xxp1;\n+\tstruct cvmx_pki_stylex_wq2_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_stylex_wq2 cvmx_pki_stylex_wq2_t;\n+\n+/**\n+ * cvmx_pki_style#_wq4\n+ *\n+ * This register configures the PKI BE WQE generation.\n+ * It is indexed by final style, PKI_WQE_S[STYLE]<5:0>.\n+ */\n+union cvmx_pki_stylex_wq4 {\n+\tu64 u64;\n+\tstruct cvmx_pki_stylex_wq4_s {\n+\t\tu64 data : 64;\n+\t} s;\n+\tstruct cvmx_pki_stylex_wq4_s cn73xx;\n+\tstruct cvmx_pki_stylex_wq4_s cn78xx;\n+\tstruct cvmx_pki_stylex_wq4_s cn78xxp1;\n+\tstruct cvmx_pki_stylex_wq4_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_stylex_wq4 cvmx_pki_stylex_wq4_t;\n+\n+/**\n+ * cvmx_pki_tag_inc#_ctl\n+ */\n+union cvmx_pki_tag_incx_ctl {\n+\tu64 u64;\n+\tstruct cvmx_pki_tag_incx_ctl_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 ptr_sel : 4;\n+\t\tu64 offset : 8;\n+\t} s;\n+\tstruct cvmx_pki_tag_incx_ctl_s cn73xx;\n+\tstruct cvmx_pki_tag_incx_ctl_s cn78xx;\n+\tstruct cvmx_pki_tag_incx_ctl_s cn78xxp1;\n+\tstruct cvmx_pki_tag_incx_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_tag_incx_ctl cvmx_pki_tag_incx_ctl_t;\n+\n+/**\n+ * cvmx_pki_tag_inc#_mask\n+ */\n+union cvmx_pki_tag_incx_mask {\n+\tu64 u64;\n+\tstruct cvmx_pki_tag_incx_mask_s {\n+\t\tu64 en : 64;\n+\t} s;\n+\tstruct cvmx_pki_tag_incx_mask_s cn73xx;\n+\tstruct cvmx_pki_tag_incx_mask_s cn78xx;\n+\tstruct cvmx_pki_tag_incx_mask_s cn78xxp1;\n+\tstruct cvmx_pki_tag_incx_mask_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_tag_incx_mask cvmx_pki_tag_incx_mask_t;\n+\n+/**\n+ * cvmx_pki_tag_secret\n+ *\n+ * The source and destination initial values (IVs) in tag generation provide a mechanism for\n+ * seeding with a random initialization value to reduce cache collision attacks.\n+ */\n+union cvmx_pki_tag_secret {\n+\tu64 u64;\n+\tstruct cvmx_pki_tag_secret_s {\n+\t\tu64 dst6 : 16;\n+\t\tu64 src6 : 16;\n+\t\tu64 dst : 16;\n+\t\tu64 src : 16;\n+\t} s;\n+\tstruct cvmx_pki_tag_secret_s cn73xx;\n+\tstruct cvmx_pki_tag_secret_s cn78xx;\n+\tstruct cvmx_pki_tag_secret_s cn78xxp1;\n+\tstruct cvmx_pki_tag_secret_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_tag_secret cvmx_pki_tag_secret_t;\n+\n+/**\n+ * cvmx_pki_x2p_req_ofl\n+ */\n+union cvmx_pki_x2p_req_ofl {\n+\tu64 u64;\n+\tstruct cvmx_pki_x2p_req_ofl_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 x2p_did : 4;\n+\t} s;\n+\tstruct cvmx_pki_x2p_req_ofl_s cn73xx;\n+\tstruct cvmx_pki_x2p_req_ofl_s cn78xx;\n+\tstruct cvmx_pki_x2p_req_ofl_s cn78xxp1;\n+\tstruct cvmx_pki_x2p_req_ofl_s cnf75xx;\n+};\n+\n+typedef union cvmx_pki_x2p_req_ofl cvmx_pki_x2p_req_ofl_t;\n+\n+#endif\n",
    "prefixes": [
        "v1",
        "23/50"
    ]
}