Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1415006/?format=api
{ "id": 1415006, "url": "http://patchwork.ozlabs.org/api/patches/1415006/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-39-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-39-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:06:00", "name": "[v1,38/50] mips: octeon: Add cvmx-helper-jtag.c", "commit_ref": "23753c6c4d08f1ede8ebf94a5bb30800bd11078a", "pull_url": null, "state": "accepted", "archived": false, "hash": "b8bc97b622f15eb95a1b514d368e61efd0066753", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-39-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1415006/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1415006/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=P4JoMkUi;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4Cswm40xwgz9sSs\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:12:20 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 73D8582748;\n\tFri, 11 Dec 2020 17:08:29 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id F0508827AB; Fri, 11 Dec 2020 17:07:56 +0100 (CET)", "from mx2.mailbox.org (mx2a.mailbox.org\n [IPv6:2001:67c:2050:104:0:2:25:2])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 601DF8270C\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:28 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id 00910A0E3F;\n Fri, 11 Dec 2020 17:06:27 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter04.heinlein-hosting.de (spamfilter04.heinlein-hosting.de\n [80.241.56.122]) (amavisd-new, port 10030)\n with ESMTP id KVONrrCqzXkU; Fri, 11 Dec 2020 17:06:24 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702909;\n\tbh=p+VmxxDIwa9EACr/fv8dNJXM64V0uIZQTD0o+9cRDgE=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=P4JoMkUizOLM72rmBF3ZgB49wma7rmisYLn8Xx9ergK7tSRtcD03Klef5PtnroTMv\n\t x64/4TmfkfBZsbPbWTRRad2VQgRS3m73UcsF5AH97BedgIH1ul11qXGW/kqr0JldgB\n\t 9IJCy06AQC8P4bYN+8KWuWVbW//CEKCdxF+TNDJ3myAxpdJlfEobOv0GgyS91BI1It\n\t FHKJM1ANatFI2IcPXYRgONabONxeWd+yk/mdSoWceZxj1ZzoHZQ+fu+xBo7Jo1fpFq\n\t OimWFg/hWwW6VjP002z6k+WVbwxdfGDqfWWVdjsX+iJl0dr2MEPxzWgcH7zdq/zyG9\n\t FkbthuvJi7tEA==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 38/50] mips: octeon: Add cvmx-helper-jtag.c", "Date": "Fri, 11 Dec 2020 17:06:00 +0100", "Message-Id": "<20201211160612.1498780-39-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-0.67 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "03C2D1880", "X-Rspamd-UID": "47ba48", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-helper-jtag.c from 2013 U-Boot. It will be used by the later\nadded drivers to support PCIe and networking on the MIPS Octeon II / III\nplatforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n arch/mips/mach-octeon/cvmx-helper-jtag.c | 172 +++++++++++++++++++++++\n 1 file changed, 172 insertions(+)\n create mode 100644 arch/mips/mach-octeon/cvmx-helper-jtag.c", "diff": "diff --git a/arch/mips/mach-octeon/cvmx-helper-jtag.c b/arch/mips/mach-octeon/cvmx-helper-jtag.c\nnew file mode 100644\nindex 0000000000..a6fa69b4c5\n--- /dev/null\n+++ b/arch/mips/mach-octeon/cvmx-helper-jtag.c\n@@ -0,0 +1,172 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Helper utilities for qlm_jtag.\n+ */\n+\n+#include <log.h>\n+#include <asm/global_data.h>\n+#include <linux/delay.h>\n+\n+#include <mach/cvmx-regs.h>\n+#include <mach/octeon-model.h>\n+#include <mach/cvmx-fuse.h>\n+#include <mach/octeon-feature.h>\n+#include <mach/cvmx-qlm.h>\n+#include <mach/octeon_qlm.h>\n+#include <mach/cvmx-pcie.h>\n+#include <mach/cvmx-ciu-defs.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+/**\n+ * Initialize the internal QLM JTAG logic to allow programming\n+ * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.\n+ * These functions should only be used at the direction of Cavium\n+ * Networks. Programming incorrect values into the JTAG chain\n+ * can cause chip damage.\n+ */\n+void cvmx_helper_qlm_jtag_init(void)\n+{\n+\tunion cvmx_ciu_qlm_jtgc jtgc;\n+\tint clock_div = 0;\n+\tint divisor;\n+\n+\tdivisor = gd->bus_clk / (1000000 * (OCTEON_IS_MODEL(OCTEON_CN68XX) ? 10 : 25));\n+\n+\tdivisor = (divisor - 1) >> 2;\n+\t/* Convert the divisor into a power of 2 shift */\n+\twhile (divisor) {\n+\t\tclock_div++;\n+\t\tdivisor >>= 1;\n+\t}\n+\n+\t/*\n+\t * Clock divider for QLM JTAG operations. sclk is divided by\n+\t * 2^(CLK_DIV + 2)\n+\t */\n+\tjtgc.u64 = 0;\n+\tjtgc.s.clk_div = clock_div;\n+\tjtgc.s.mux_sel = 0;\n+\tif (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))\n+\t\tjtgc.s.bypass = 0x7;\n+\telse\n+\t\tjtgc.s.bypass = 0xf;\n+\tif (OCTEON_IS_MODEL(OCTEON_CN68XX))\n+\t\tjtgc.s.bypass_ext = 1;\n+\tcsr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64);\n+\tcsr_rd(CVMX_CIU_QLM_JTGC);\n+}\n+\n+/**\n+ * Write up to 32bits into the QLM jtag chain. Bits are shifted\n+ * into the MSB and out the LSB, so you should shift in the low\n+ * order bits followed by the high order bits. The JTAG chain for\n+ * CN52XX and CN56XX is 4 * 268 bits long, or 1072. The JTAG chain\n+ * for CN63XX is 4 * 300 bits long, or 1200.\n+ *\n+ * @param qlm QLM to shift value into\n+ * @param bits Number of bits to shift in (1-32).\n+ * @param data Data to shift in. Bit 0 enters the chain first, followed by\n+ * bit 1, etc.\n+ *\n+ * @return The low order bits of the JTAG chain that shifted out of the\n+ * circle.\n+ */\n+uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)\n+{\n+\tunion cvmx_ciu_qlm_jtgc jtgc;\n+\tunion cvmx_ciu_qlm_jtgd jtgd;\n+\n+\tjtgc.u64 = csr_rd(CVMX_CIU_QLM_JTGC);\n+\tjtgc.s.mux_sel = qlm;\n+\tcsr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64);\n+\tcsr_rd(CVMX_CIU_QLM_JTGC);\n+\n+\tjtgd.u64 = 0;\n+\tjtgd.s.shift = 1;\n+\tjtgd.s.shft_cnt = bits - 1;\n+\tjtgd.s.shft_reg = data;\n+\tjtgd.s.select = 1 << qlm;\n+\tcsr_wr(CVMX_CIU_QLM_JTGD, jtgd.u64);\n+\tdo {\n+\t\tjtgd.u64 = csr_rd(CVMX_CIU_QLM_JTGD);\n+\t} while (jtgd.s.shift);\n+\treturn jtgd.s.shft_reg >> (32 - bits);\n+}\n+\n+/**\n+ * Shift long sequences of zeros into the QLM JTAG chain. It is\n+ * common to need to shift more than 32 bits of zeros into the\n+ * chain. This function is a convience wrapper around\n+ * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of\n+ * zeros at a time.\n+ *\n+ * @param qlm QLM to shift zeros into\n+ * @param bits\n+ */\n+void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)\n+{\n+\twhile (bits > 0) {\n+\t\tint n = bits;\n+\n+\t\tif (n > 32)\n+\t\t\tn = 32;\n+\t\tcvmx_helper_qlm_jtag_shift(qlm, n, 0);\n+\t\tbits -= n;\n+\t}\n+}\n+\n+/**\n+ * Program the QLM JTAG chain into all lanes of the QLM. You must\n+ * have already shifted in the proper number of bits into the\n+ * JTAG chain. Updating invalid values can possibly cause chip damage.\n+ *\n+ * @param qlm QLM to program\n+ */\n+void cvmx_helper_qlm_jtag_update(int qlm)\n+{\n+\tunion cvmx_ciu_qlm_jtgc jtgc;\n+\tunion cvmx_ciu_qlm_jtgd jtgd;\n+\n+\tjtgc.u64 = csr_rd(CVMX_CIU_QLM_JTGC);\n+\tjtgc.s.mux_sel = qlm;\n+\n+\tcsr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64);\n+\tcsr_rd(CVMX_CIU_QLM_JTGC);\n+\n+\t/* Update the new data */\n+\tjtgd.u64 = 0;\n+\tjtgd.s.update = 1;\n+\tjtgd.s.select = 1 << qlm;\n+\tcsr_wr(CVMX_CIU_QLM_JTGD, jtgd.u64);\n+\tdo {\n+\t\tjtgd.u64 = csr_rd(CVMX_CIU_QLM_JTGD);\n+\t} while (jtgd.s.update);\n+}\n+\n+/**\n+ * Load the QLM JTAG chain with data from all lanes of the QLM.\n+ *\n+ * @param qlm QLM to program\n+ */\n+void cvmx_helper_qlm_jtag_capture(int qlm)\n+{\n+\tunion cvmx_ciu_qlm_jtgc jtgc;\n+\tunion cvmx_ciu_qlm_jtgd jtgd;\n+\n+\tjtgc.u64 = csr_rd(CVMX_CIU_QLM_JTGC);\n+\tjtgc.s.mux_sel = qlm;\n+\n+\tcsr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64);\n+\tcsr_rd(CVMX_CIU_QLM_JTGC);\n+\n+\tjtgd.u64 = 0;\n+\tjtgd.s.capture = 1;\n+\tjtgd.s.select = 1 << qlm;\n+\tcsr_wr(CVMX_CIU_QLM_JTGD, jtgd.u64);\n+\tdo {\n+\t\tjtgd.u64 = csr_rd(CVMX_CIU_QLM_JTGD);\n+\t} while (jtgd.s.capture);\n+}\n", "prefixes": [ "v1", "38/50" ] }