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GET /api/patches/1415005/?format=api
{ "id": 1415005, "url": "http://patchwork.ozlabs.org/api/patches/1415005/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-35-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-35-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:56", "name": "[v1,34/50] mips: octeon: Misc changes required because of the newly added headers", "commit_ref": "cbcf35850a206d5ebb01a68a2d32a89d37f567d5", "pull_url": null, "state": "accepted", "archived": false, "hash": "3477f7abade40ac11b00f87ca3ce7411fa45ccf7", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-35-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1415005/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1415005/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=jiUtIBi/;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4Cswlq1dhWz9sSs\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:12:07 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 5E284827B9;\n\tFri, 11 Dec 2020 17:08:25 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 1BF2E8276B; Fri, 11 Dec 2020 17:07:50 +0100 (CET)", "from mx2.mailbox.org (mx2.mailbox.org [80.241.60.215])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 0890F82637\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:28 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org\n [IPv6:2001:67c:2050:105:465:1:1:0])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id BF940A0B6C;\n Fri, 11 Dec 2020 17:06:27 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter05.heinlein-hosting.de (spamfilter05.heinlein-hosting.de\n [80.241.56.123]) (amavisd-new, port 10030)\n with ESMTP id x9c7st56tto2; Fri, 11 Dec 2020 17:06:23 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702905;\n\tbh=6T+G/kedyAwfcSThsrbV6bJidmjAnTdayDvsFSd5dv8=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=jiUtIBi/1c4wHzibPEuW0f7sd2UI3vxPWp4y5JohMsZfIc2x99mnHjxifmyU7mWCW\n\t 3gjacU0ngycpfZv8/vcFMk/JF/WdL71pz7LesvxF2s7ir1Pne8MAcVPTkI4f104+Qv\n\t dmmNuDvWjYeU74wqh2eAhcdJYczuDbeaHWHPSDzfuQJj3uCbRghjAJDa5Zqk10ruXQ\n\t ChSgM35ACOvjkg/vMCRmHkqFGvF1ICu03EeONW5LBsMzoFd9mbze0jaVrSnMqW+SU/\n\t rVplyrRmvHYztfc1P5QQ0Rtqp7xG7KeD5FwRF2TE5qq877+8m+nM23rkWsqlviya1O\n\t f5GJMrXsDkpxQ==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE,T_FILL_THIS_FORM_SHORT autolearn=ham autolearn_force=no\n version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 34/50] mips: octeon: Misc changes required because of the\n newly added headers", "Date": "Fri, 11 Dec 2020 17:05:56 +0100", "Message-Id": "<20201211160612.1498780-35-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "*", "X-Rspamd-Score": "0.69 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "B0F0F1870", "X-Rspamd-UID": "d4843d", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "With the newly added headers and their restructuring (which macro is\ndefined where), some changes in the already existing Octeon files are\nnecessary. This patch makes the necessary changes.\n\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n arch/mips/mach-octeon/bootoctlinux.c | 1 +\n arch/mips/mach-octeon/cvmx-bootmem.c | 6 -\n arch/mips/mach-octeon/cvmx-coremask.c | 1 +\n .../mips/mach-octeon/include/mach/cvmx-regs.h | 330 +++++++++++++++++-\n .../mach-octeon/include/mach/octeon-feature.h | 2 +\n .../mach-octeon/include/mach/octeon-model.h | 2 +\n .../mach-octeon/include/mach/octeon_ddr.h | 187 +---------\n drivers/ram/octeon/octeon3_lmc.c | 28 +-\n drivers/ram/octeon/octeon_ddr.c | 22 +-\n 9 files changed, 343 insertions(+), 236 deletions(-)", "diff": "diff --git a/arch/mips/mach-octeon/bootoctlinux.c b/arch/mips/mach-octeon/bootoctlinux.c\nindex 26136902f3..e6eefc6103 100644\n--- a/arch/mips/mach-octeon/bootoctlinux.c\n+++ b/arch/mips/mach-octeon/bootoctlinux.c\n@@ -24,6 +24,7 @@\n #include <mach/octeon-model.h>\n #include <mach/octeon-feature.h>\n #include <mach/bootoct_cmd.h>\n+#include <mach/cvmx-ciu-defs.h>\n \n DECLARE_GLOBAL_DATA_PTR;\n \ndiff --git a/arch/mips/mach-octeon/cvmx-bootmem.c b/arch/mips/mach-octeon/cvmx-bootmem.c\nindex 80bb7ac6c8..4b10effefb 100644\n--- a/arch/mips/mach-octeon/cvmx-bootmem.c\n+++ b/arch/mips/mach-octeon/cvmx-bootmem.c\n@@ -21,12 +21,6 @@\n \n DECLARE_GLOBAL_DATA_PTR;\n \n-#define CVMX_MIPS32_SPACE_KSEG0\t\t1L\n-#define CVMX_MIPS_SPACE_XKPHYS\t\t2LL\n-\n-#define CVMX_ADD_SEG(seg, add)\t\t((((u64)(seg)) << 62) | (add))\n-#define CVMX_ADD_SEG32(seg, add)\t(((u32)(seg) << 31) | (u32)(add))\n-\n /**\n * This is the physical location of a struct cvmx_bootmem_desc\n * structure in Octeon's memory. Note that dues to addressing\ndiff --git a/arch/mips/mach-octeon/cvmx-coremask.c b/arch/mips/mach-octeon/cvmx-coremask.c\nindex cff8c08b97..ed673e4993 100644\n--- a/arch/mips/mach-octeon/cvmx-coremask.c\n+++ b/arch/mips/mach-octeon/cvmx-coremask.c\n@@ -14,6 +14,7 @@\n #include <mach/cvmx-fuse.h>\n #include <mach/octeon-model.h>\n #include <mach/octeon-feature.h>\n+#include <mach/cvmx-ciu-defs.h>\n \n struct cvmx_coremask *get_coremask_override(struct cvmx_coremask *pcm)\n {\ndiff --git a/arch/mips/mach-octeon/include/mach/cvmx-regs.h b/arch/mips/mach-octeon/include/mach/cvmx-regs.h\nindex b84fc9fd57..56528bc1bf 100644\n--- a/arch/mips/mach-octeon/include/mach/cvmx-regs.h\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-regs.h\n@@ -9,6 +9,7 @@\n #include <linux/bitfield.h>\n #include <linux/bitops.h>\n #include <linux/io.h>\n+#include <mach/cvmx-address.h>\n \n /* General defines */\n #define CVMX_MAX_CORES\t\t48\n@@ -26,48 +27,116 @@\n \n #define MAX_CORE_TADS\t\t8\n \n-#define CAST_ULL(v)\t\t((unsigned long long)(v))\n #define CASTPTR(type, v)\t((type *)(long)(v))\n+#define CAST64(v)\t\t((long long)(long)(v))\n \n /* Regs */\n-#define CVMX_CIU_PP_RST\t\t0x0001010000000100ULL\n #define CVMX_CIU3_NMI\t\t0x0001010000000160ULL\n-#define CVMX_CIU_FUSE\t\t0x00010100000001a0ULL\n-#define CVMX_CIU_NMI\t\t0x0001070000000718ULL\n \n #define CVMX_MIO_BOOT_LOC_CFGX(x) (0x0001180000000080ULL + ((x) & 1) * 8)\n-#define MIO_BOOT_LOC_CFG_BASE\t\tGENMASK_ULL(27, 3)\n-#define MIO_BOOT_LOC_CFG_EN\t\tBIT_ULL(31)\n+#define MIO_BOOT_LOC_CFG_BASE\tGENMASK_ULL(27, 3)\n+#define MIO_BOOT_LOC_CFG_EN\tBIT_ULL(31)\n \n #define CVMX_MIO_BOOT_LOC_ADR\t0x0001180000000090ULL\n-#define MIO_BOOT_LOC_ADR_ADR\t\tGENMASK_ULL(7, 3)\n+#define MIO_BOOT_LOC_ADR_ADR\tGENMASK_ULL(7, 3)\n \n #define CVMX_MIO_BOOT_LOC_DAT\t0x0001180000000098ULL\n \n #define CVMX_MIO_FUS_DAT2\t0x0001180000001410ULL\n-#define MIO_FUS_DAT2_NOCRYPTO\t\tBIT_ULL(26)\n-#define MIO_FUS_DAT2_NOMUL\t\tBIT_ULL(27)\n-#define MIO_FUS_DAT2_DORM_CRYPTO\tBIT_ULL(34)\n+#define MIO_FUS_DAT2_NOCRYPTO\tBIT_ULL(26)\n+#define MIO_FUS_DAT2_NOMUL\tBIT_ULL(27)\n+#define MIO_FUS_DAT2_DORM_CRYPTO BIT_ULL(34)\n \n #define CVMX_MIO_FUS_RCMD\t0x0001180000001500ULL\n-#define MIO_FUS_RCMD_ADDR\t\tGENMASK_ULL(7, 0)\n-#define MIO_FUS_RCMD_PEND\t\tBIT_ULL(12)\n-#define MIO_FUS_RCMD_DAT\t\tGENMASK_ULL(23, 16)\n+#define MIO_FUS_RCMD_ADDR\tGENMASK_ULL(7, 0)\n+#define MIO_FUS_RCMD_PEND\tBIT_ULL(12)\n+#define MIO_FUS_RCMD_DAT\tGENMASK_ULL(23, 16)\n \n #define CVMX_RNM_CTL_STATUS\t0x0001180040000000ULL\n-#define RNM_CTL_STATUS_EER_VAL\t\tBIT_ULL(9)\n+#define RNM_CTL_STATUS_EER_VAL\tBIT_ULL(9)\n+\n+#define CVMX_IOBDMA_ORDERED_IO_ADDR 0xffffffffffffa200ull\n \n /* turn the variable name into a string */\n #define CVMX_TMP_STR(x)\t\tCVMX_TMP_STR2(x)\n #define CVMX_TMP_STR2(x)\t#x\n \n+#define CVMX_RDHWR(result, regstr)\t\t\t\t\t\\\n+\tasm volatile(\"rdhwr %[rt],$\" CVMX_TMP_STR(regstr) : [rt] \"=d\"(result))\n #define CVMX_RDHWRNV(result, regstr)\t\t\t\t\t\\\n-\tasm volatile (\"rdhwr %[rt],$\" CVMX_TMP_STR(regstr) : [rt] \"=d\" (result))\n+\tasm(\"rdhwr %[rt],$\" CVMX_TMP_STR(regstr) : [rt] \"=d\"(result))\n+#define CVMX_POP(result, input)\t\t\t\t\t\t\\\n+\tasm(\"pop %[rd],%[rs]\" : [rd] \"=d\"(result) : [rs] \"d\"(input))\n+\n+#define CVMX_SYNCW asm volatile(\"syncw\\nsyncw\\n\" : : : \"memory\")\n+#define CVMX_SYNCS asm volatile(\"syncs\\n\" : : : \"memory\")\n+#define CVMX_SYNCWS asm volatile(\"syncws\\n\" : : : \"memory\")\n+\n+#define CVMX_CACHE_LINE_SIZE\t128\t\t\t // In bytes\n+#define CVMX_CACHE_LINE_MASK\t(CVMX_CACHE_LINE_SIZE - 1) // In bytes\n+#define CVMX_CACHE_LINE_ALIGNED __aligned(CVMX_CACHE_LINE_SIZE)\n+\n+#define CVMX_SYNCIOBDMA\t\tasm volatile(\"synciobdma\" : : : \"memory\")\n+\n+#define CVMX_MF_CHORD(dest)\tCVMX_RDHWR(dest, 30)\n+\n+/*\n+ * The macros cvmx_likely and cvmx_unlikely use the\n+ * __builtin_expect GCC operation to control branch\n+ * probabilities for a conditional. For example, an \"if\"\n+ * statement in the code that will almost always be\n+ * executed should be written as \"if (cvmx_likely(...))\".\n+ * If the \"else\" section of an if statement is more\n+ * probable, use \"if (cvmx_unlikey(...))\".\n+ */\n+#define cvmx_likely(x)\t __builtin_expect(!!(x), 1)\n+#define cvmx_unlikely(x) __builtin_expect(!!(x), 0)\n+\n+#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, to_us)\t\\\n+\t({\t\t\t\t\t\t\t\t\\\n+\t\tint result;\t\t\t\t\t\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\tu64 done = get_timer(0);\t\t\t\\\n+\t\t\ttype c;\t\t\t\t\t\t\\\n+\t\t\twhile (1) {\t\t\t\t\t\\\n+\t\t\t\tc.u64 = csr_rd(address);\t\t\\\n+\t\t\t\tif ((c.s.field)op(value)) {\t\t\\\n+\t\t\t\t\tresult = 0;\t\t\t\\\n+\t\t\t\t\tbreak;\t\t\t\t\\\n+\t\t\t\t} else if (get_timer(done) > ((to_us) / 1000)) { \\\n+\t\t\t\t\tresult = -1;\t\t\t\\\n+\t\t\t\t\tbreak;\t\t\t\t\\\n+\t\t\t\t} else\t\t\t\t\t\\\n+\t\t\t\t\tudelay(100);\t\t\t\\\n+\t\t\t}\t\t\t\t\t\t\\\n+\t\t} while (0);\t\t\t\t\t\t\\\n+\t\tresult;\t\t\t\t\t\t\t\\\n+\t})\n \n-#define CVMX_SYNCW\t\t\t\t\t\\\n-\tasm volatile (\"syncw\\nsyncw\\n\" : : : \"memory\")\n+#define CVMX_WAIT_FOR_FIELD64_NODE(node, address, type, field, op, value, to_us) \\\n+\t({\t\t\t\t\t\t\t\t\\\n+\t\tint result;\t\t\t\t\t\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\tu64 done = get_timer(0);\t\t\t\\\n+\t\t\ttype c;\t\t\t\t\t\t\\\n+\t\t\twhile (1) {\t\t\t\t\t\\\n+\t\t\t\tc.u64 = csr_rd(address);\t\t\\\n+\t\t\t\tif ((c.s.field)op(value)) {\t\t\\\n+\t\t\t\t\tresult = 0;\t\t\t\\\n+\t\t\t\t\tbreak;\t\t\t\t\\\n+\t\t\t\t} else if (get_timer(done) > ((to_us) / 1000)) { \\\n+\t\t\t\t\tresult = -1;\t\t\t\\\n+\t\t\t\t\tbreak;\t\t\t\t\\\n+\t\t\t\t} else\t\t\t\t\t\\\n+\t\t\t\t\tudelay(100);\t\t\t\\\n+\t\t\t}\t\t\t\t\t\t\\\n+\t\t} while (0);\t\t\t\t\t\t\\\n+\t\tresult;\t\t\t\t\t\t\t\\\n+\t})\n \n /* ToDo: Currently only node = 0 supported */\n+#define cvmx_get_node_num()\t0\n+\n static inline u64 csr_rd_node(int node, u64 addr)\n {\n \tvoid __iomem *base;\n@@ -76,11 +145,24 @@ static inline u64 csr_rd_node(int node, u64 addr)\n \treturn ioread64(base);\n }\n \n+static inline u32 csr_rd32_node(int node, u64 addr)\n+{\n+\tvoid __iomem *base;\n+\n+\tbase = ioremap_nocache(addr, 0x100);\n+\treturn ioread32(base);\n+}\n+\n static inline u64 csr_rd(u64 addr)\n {\n \treturn csr_rd_node(0, addr);\n }\n \n+static inline u32 csr_rd32(u64 addr)\n+{\n+\treturn csr_rd32_node(0, addr);\n+}\n+\n static inline void csr_wr_node(int node, u64 addr, u64 val)\n {\n \tvoid __iomem *base;\n@@ -89,11 +171,24 @@ static inline void csr_wr_node(int node, u64 addr, u64 val)\n \tiowrite64(val, base);\n }\n \n+static inline void csr_wr32_node(int node, u64 addr, u32 val)\n+{\n+\tvoid __iomem *base;\n+\n+\tbase = ioremap_nocache(addr, 0x100);\n+\tiowrite32(val, base);\n+}\n+\n static inline void csr_wr(u64 addr, u64 val)\n {\n \tcsr_wr_node(0, addr, val);\n }\n \n+static inline void csr_wr32(u64 addr, u32 val)\n+{\n+\tcsr_wr32_node(0, addr, val);\n+}\n+\n /*\n * We need to use the volatile access here, otherwise the IO accessor\n * functions might swap the bytes\n@@ -103,21 +198,173 @@ static inline u64 cvmx_read64_uint64(u64 addr)\n \treturn *(volatile u64 *)addr;\n }\n \n+static inline s64 cvmx_read64_int64(u64 addr)\n+{\n+\treturn *(volatile s64 *)addr;\n+}\n+\n static inline void cvmx_write64_uint64(u64 addr, u64 val)\n {\n \t*(volatile u64 *)addr = val;\n }\n \n+static inline void cvmx_write64_int64(u64 addr, s64 val)\n+{\n+\t*(volatile s64 *)addr = val;\n+}\n+\n static inline u32 cvmx_read64_uint32(u64 addr)\n {\n \treturn *(volatile u32 *)addr;\n }\n \n+static inline s32 cvmx_read64_int32(u64 addr)\n+{\n+\treturn *(volatile s32 *)addr;\n+}\n+\n static inline void cvmx_write64_uint32(u64 addr, u32 val)\n {\n \t*(volatile u32 *)addr = val;\n }\n \n+static inline void cvmx_write64_int32(u64 addr, s32 val)\n+{\n+\t*(volatile s32 *)addr = val;\n+}\n+\n+static inline void cvmx_write64_int16(u64 addr, s16 val)\n+{\n+\t*(volatile s16 *)addr = val;\n+}\n+\n+static inline void cvmx_write64_uint16(u64 addr, u16 val)\n+{\n+\t*(volatile u16 *)addr = val;\n+}\n+\n+static inline void cvmx_write64_int8(u64 addr, int8_t val)\n+{\n+\t*(volatile int8_t *)addr = val;\n+}\n+\n+static inline void cvmx_write64_uint8(u64 addr, u8 val)\n+{\n+\t*(volatile u8 *)addr = val;\n+}\n+\n+static inline s16 cvmx_read64_int16(u64 addr)\n+{\n+\treturn *(volatile s16 *)addr;\n+}\n+\n+static inline u16 cvmx_read64_uint16(u64 addr)\n+{\n+\treturn *(volatile u16 *)addr;\n+}\n+\n+static inline int8_t cvmx_read64_int8(u64 addr)\n+{\n+\treturn *(volatile int8_t *)addr;\n+}\n+\n+static inline u8 cvmx_read64_uint8(u64 addr)\n+{\n+\treturn *(volatile u8 *)addr;\n+}\n+\n+static inline void cvmx_send_single(u64 data)\n+{\n+\tcvmx_write64_uint64(CVMX_IOBDMA_ORDERED_IO_ADDR, data);\n+}\n+\n+/**\n+ * Perform a 64-bit write to an IO address\n+ *\n+ * @param io_addr\tI/O address to write to\n+ * @param val\t\t64-bit value to write\n+ */\n+static inline void cvmx_write_io(u64 io_addr, u64 val)\n+{\n+\tcvmx_write64_uint64(io_addr, val);\n+}\n+\n+/**\n+ * Builds a memory address for I/O based on the Major and Sub DID.\n+ *\n+ * @param major_did 5 bit major did\n+ * @param sub_did 3 bit sub did\n+ * @return I/O base address\n+ */\n+static inline u64 cvmx_build_io_address(u64 major_did, u64 sub_did)\n+{\n+\treturn ((0x1ull << 48) | (major_did << 43) | (sub_did << 40));\n+}\n+\n+/**\n+ * Builds a bit mask given the required size in bits.\n+ *\n+ * @param bits Number of bits in the mask\n+ * @return The mask\n+ */\n+static inline u64 cvmx_build_mask(u64 bits)\n+{\n+\tif (bits == 64)\n+\t\treturn -1;\n+\n+\treturn ~((~0x0ull) << bits);\n+}\n+\n+/**\n+ * Extract bits out of a number\n+ *\n+ * @param input Number to extract from\n+ * @param lsb Starting bit, least significant (0-63)\n+ * @param width Width in bits (1-64)\n+ *\n+ * @return Extracted number\n+ */\n+static inline u64 cvmx_bit_extract(u64 input, int lsb, int width)\n+{\n+\tu64 result = input >> lsb;\n+\n+\tresult &= cvmx_build_mask(width);\n+\n+\treturn result;\n+}\n+\n+/**\n+ * Perform mask and shift to place the supplied value into\n+ * the supplied bit rage.\n+ *\n+ * Example: cvmx_build_bits(39,24,value)\n+ * <pre>\n+ * 6 5 4 3 3 2 1\n+ * 3 5 7 9 1 3 5 7 0\n+ * +-------+-------+-------+-------+-------+-------+-------+------+\n+ * 000000000000000000000000___________value000000000000000000000000\n+ * </pre>\n+ *\n+ * @param high_bit Highest bit value can occupy (inclusive) 0-63\n+ * @param low_bit Lowest bit value can occupy inclusive 0-high_bit\n+ * @param value Value to use\n+ * @return Value masked and shifted\n+ */\n+static inline u64 cvmx_build_bits(u64 high_bit, u64 low_bit, u64 value)\n+{\n+\treturn ((value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit);\n+}\n+\n+static inline u64 cvmx_mask_to_localaddr(u64 addr)\n+{\n+\treturn (addr & 0xffffffffff);\n+}\n+\n+static inline u64 cvmx_addr_on_node(u64 node, u64 addr)\n+{\n+\treturn (node << 40) | cvmx_mask_to_localaddr(addr);\n+}\n+\n static inline void *cvmx_phys_to_ptr(u64 addr)\n {\n \treturn (void *)CKSEG0ADDR(addr);\n@@ -141,4 +388,53 @@ static inline unsigned int cvmx_get_core_num(void)\n \treturn core_num;\n }\n \n+/**\n+ * Node-local number of the core on which the program is currently running.\n+ *\n+ * @return core number on local node\n+ */\n+static inline unsigned int cvmx_get_local_core_num(void)\n+{\n+\tunsigned int core_num, core_mask;\n+\n+\tCVMX_RDHWRNV(core_num, 0);\n+\t/* note that MAX_CORES may not be power of 2 */\n+\tcore_mask = (1 << CVMX_NODE_NO_SHIFT) - 1;\n+\n+\treturn core_num & core_mask;\n+}\n+\n+/**\n+ * Returns the number of bits set in the provided value.\n+ * Simple wrapper for POP instruction.\n+ *\n+ * @param val 32 bit value to count set bits in\n+ *\n+ * @return Number of bits set\n+ */\n+static inline u32 cvmx_pop(u32 val)\n+{\n+\tu32 pop;\n+\n+\tCVMX_POP(pop, val);\n+\n+\treturn pop;\n+}\n+\n+#define cvmx_read_csr_node(node, addr)\t csr_rd(addr)\n+#define cvmx_write_csr_node(node, addr, val) csr_wr(addr, val)\n+\n+#define cvmx_printf printf\n+#define cvmx_vprintf vprintf\n+\n+#if defined(DEBUG)\n+void cvmx_warn(const char *format, ...) __printf(1, 2);\n+#else\n+void cvmx_warn(const char *format, ...);\n+#endif\n+\n+#define cvmx_warn_if(expression, format, ...)\t\t\t\t\\\n+\tif (expression)\t\t\t\t\t\t\t\\\n+\t\tcvmx_warn(format, ##__VA_ARGS__)\n+\n #endif /* __CVMX_REGS_H__ */\ndiff --git a/arch/mips/mach-octeon/include/mach/octeon-feature.h b/arch/mips/mach-octeon/include/mach/octeon-feature.h\nindex 1202716ba5..2eb1714e90 100644\n--- a/arch/mips/mach-octeon/include/mach/octeon-feature.h\n+++ b/arch/mips/mach-octeon/include/mach/octeon-feature.h\n@@ -6,6 +6,8 @@\n #ifndef __OCTEON_FEATURE_H__\n #define __OCTEON_FEATURE_H__\n \n+#include \"cvmx-fuse.h\"\n+\n /*\n * Octeon models are declared after the macros in octeon-model.h with the\n * suffix _FEATURE. The individual features are declared with the\ndiff --git a/arch/mips/mach-octeon/include/mach/octeon-model.h b/arch/mips/mach-octeon/include/mach/octeon-model.h\nindex 22d6df6a9e..9164a4cfd6 100644\n--- a/arch/mips/mach-octeon/include/mach/octeon-model.h\n+++ b/arch/mips/mach-octeon/include/mach/octeon-model.h\n@@ -28,6 +28,8 @@\n * use only, and may change without notice.\n */\n \n+#include <asm/mipsregs.h>\n+\n #define OCTEON_FAMILY_MASK 0x00ffff00\n #define OCTEON_PRID_MASK\t0x00ffffff\n \ndiff --git a/arch/mips/mach-octeon/include/mach/octeon_ddr.h b/arch/mips/mach-octeon/include/mach/octeon_ddr.h\nindex 4473be4d44..e630dc5ae3 100644\n--- a/arch/mips/mach-octeon/include/mach/octeon_ddr.h\n+++ b/arch/mips/mach-octeon/include/mach/octeon_ddr.h\n@@ -12,12 +12,8 @@\n #include <linux/io.h>\n #include <mach/octeon-model.h>\n #include <mach/cvmx/cvmx-lmcx-defs.h>\n-\n-/* Mapping is done starting from 0x11800.80000000 */\n-#define CVMX_L2C_CTL\t\t0x00800000\n-#define CVMX_L2C_BIG_CTL\t0x00800030\n-#define CVMX_L2C_TADX_INT(i)\t(0x00a00028 + (((i) & 7) * 0x40000))\n-#define CVMX_L2C_MCIX_INT(i)\t(0x00c00028 + (((i) & 3) * 0x40000))\n+#include <mach/cvmx-regs.h>\n+#include <mach/cvmx-l2c-defs.h>\n \n /* Some \"external\" (non-LMC) registers */\n #define CVMX_IPD_CLK_COUNT\t\t0x00014F0000000338\n@@ -68,34 +64,6 @@ static inline void l2c_wr(struct ddr_priv *priv, u64 addr, u64 val)\n \tiowrite64(val, priv->l2c_base + addr);\n }\n \n-/* Access other CSR registers not located inside the LMC address space */\n-static inline u64 csr_rd(u64 addr)\n-{\n-\tvoid __iomem *base;\n-\n-\tbase = ioremap_nocache(addr, 0x100);\n-\treturn ioread64(base);\n-}\n-\n-static inline void csr_wr(u64 addr, u64 val)\n-{\n-\tvoid __iomem *base;\n-\n-\tbase = ioremap_nocache(addr, 0x100);\n-\treturn iowrite64(val, base);\n-}\n-\n-/* \"Normal\" access, without any offsets and/or mapping */\n-static inline u64 cvmx_read64_uint64(u64 addr)\n-{\n-\treturn readq((void *)addr);\n-}\n-\n-static inline void cvmx_write64_uint64(u64 addr, u64 val)\n-{\n-\twriteq(val, (void *)addr);\n-}\n-\n /* Failsafe mode */\n #define FLAG_FAILSAFE_MODE\t\t0x01000\n /* Note that the DDR clock initialized flags must be contiguous */\n@@ -167,157 +135,6 @@ static inline int ddr_verbose(void)\n #define CVMX_DCACHE_INVALIDATE\t\t\t\t\t\\\n \t{ CVMX_SYNC; asm volatile (\"cache 9, 0($0)\" : : ); }\n \n-/**\n- * cvmx_l2c_cfg\n- *\n- * Specify the RSL base addresses for the block\n- *\n- * L2C_CFG = L2C Configuration\n- *\n- * Description:\n- */\n-union cvmx_l2c_cfg {\n-\tu64 u64;\n-\tstruct cvmx_l2c_cfg_s {\n-\t\tuint64_t reserved_20_63:44;\n-\t\tuint64_t bstrun:1;\n-\t\tuint64_t lbist:1;\n-\t\tuint64_t xor_bank:1;\n-\t\tuint64_t dpres1:1;\n-\t\tuint64_t dpres0:1;\n-\t\tuint64_t dfill_dis:1;\n-\t\tuint64_t fpexp:4;\n-\t\tuint64_t fpempty:1;\n-\t\tuint64_t fpen:1;\n-\t\tuint64_t idxalias:1;\n-\t\tuint64_t mwf_crd:4;\n-\t\tuint64_t rsp_arb_mode:1;\n-\t\tuint64_t rfb_arb_mode:1;\n-\t\tuint64_t lrf_arb_mode:1;\n-\t} s;\n-};\n-\n-/**\n- * cvmx_l2c_ctl\n- *\n- * L2C_CTL = L2C Control\n- *\n- *\n- * Notes:\n- * (1) If MAXVAB is != 0, VAB_THRESH should be less than MAXVAB.\n- *\n- * (2) L2DFDBE and L2DFSBE allows software to generate L2DSBE, L2DDBE, VBFSBE,\n- * and VBFDBE errors for the purposes of testing error handling code. When\n- * one (or both) of these bits are set a PL2 which misses in the L2 will fill\n- * with the appropriate error in the first 2 OWs of the fill. Software can\n- * determine which OW pair gets the error by choosing the desired fill order\n- * (address<6:5>). A PL2 which hits in the L2 will not inject any errors.\n- * Therefore sending a WBIL2 prior to the PL2 is recommended to make a miss\n- * likely (if multiple processors are involved software must be careful to be\n- * sure no other processor or IO device can bring the block into the L2).\n- *\n- * To generate a VBFSBE or VBFDBE, software must first get the cache block\n- * into the cache with an error using a PL2 which misses the L2. Then a\n- * store partial to a portion of the cache block without the error must\n- * change the block to dirty. Then, a subsequent WBL2/WBIL2/victim will\n- * trigger the VBFSBE/VBFDBE error.\n- */\n-union cvmx_l2c_ctl {\n-\tu64 u64;\n-\tstruct cvmx_l2c_ctl_s {\n-\t\tuint64_t reserved_29_63:35;\n-\t\tuint64_t rdf_fast:1;\n-\t\tuint64_t disstgl2i:1;\n-\t\tuint64_t l2dfsbe:1;\n-\t\tuint64_t l2dfdbe:1;\n-\t\tuint64_t discclk:1;\n-\t\tuint64_t maxvab:4;\n-\t\tuint64_t maxlfb:4;\n-\t\tuint64_t rsp_arb_mode:1;\n-\t\tuint64_t xmc_arb_mode:1;\n-\t\tuint64_t reserved_2_13:12;\n-\t\tuint64_t disecc:1;\n-\t\tuint64_t disidxalias:1;\n-\t} s;\n-\n-\tstruct cvmx_l2c_ctl_cn73xx {\n-\t\tuint64_t reserved_32_63:32;\n-\t\tuint64_t ocla_qos:3;\n-\t\tuint64_t reserved_28_28:1;\n-\t\tuint64_t disstgl2i:1;\n-\t\tuint64_t reserved_25_26:2;\n-\t\tuint64_t discclk:1;\n-\t\tuint64_t reserved_16_23:8;\n-\t\tuint64_t rsp_arb_mode:1;\n-\t\tuint64_t xmc_arb_mode:1;\n-\t\tuint64_t rdf_cnt:8;\n-\t\tuint64_t reserved_4_5:2;\n-\t\tuint64_t disldwb:1;\n-\t\tuint64_t dissblkdty:1;\n-\t\tuint64_t disecc:1;\n-\t\tuint64_t disidxalias:1;\n-\t} cn73xx;\n-\n-\tstruct cvmx_l2c_ctl_cn73xx cn78xx;\n-};\n-\n-/**\n- * cvmx_l2c_big_ctl\n- *\n- * L2C_BIG_CTL = L2C Big memory control register\n- *\n- *\n- * Notes:\n- * (1) BIGRD interrupts can occur during normal operation as the PP's are\n- * allowed to prefetch to non-existent memory locations. Therefore,\n- * BIGRD is for informational purposes only.\n- *\n- * (2) When HOLEWR/BIGWR blocks a store L2C_VER_ID, L2C_VER_PP, L2C_VER_IOB,\n- * and L2C_VER_MSC will be loaded just like a store which is blocked by VRTWR.\n- * Additionally, L2C_ERR_XMC will be loaded.\n- */\n-union cvmx_l2c_big_ctl {\n-\tu64 u64;\n-\tstruct cvmx_l2c_big_ctl_s {\n-\t\tuint64_t reserved_8_63:56;\n-\t\tuint64_t maxdram:4;\n-\t\tuint64_t reserved_0_3:4;\n-\t} s;\n-\tstruct cvmx_l2c_big_ctl_cn61xx {\n-\t\tuint64_t reserved_8_63:56;\n-\t\tuint64_t maxdram:4;\n-\t\tuint64_t reserved_1_3:3;\n-\t\tuint64_t disable:1;\n-\t} cn61xx;\n-\tstruct cvmx_l2c_big_ctl_cn61xx cn63xx;\n-\tstruct cvmx_l2c_big_ctl_cn61xx cn66xx;\n-\tstruct cvmx_l2c_big_ctl_cn61xx cn68xx;\n-\tstruct cvmx_l2c_big_ctl_cn61xx cn68xxp1;\n-\tstruct cvmx_l2c_big_ctl_cn70xx {\n-\t\tuint64_t reserved_8_63:56;\n-\t\tuint64_t maxdram:4;\n-\t\tuint64_t reserved_1_3:3;\n-\t\tuint64_t disbig:1;\n-\t} cn70xx;\n-\tstruct cvmx_l2c_big_ctl_cn70xx cn70xxp1;\n-\tstruct cvmx_l2c_big_ctl_cn70xx cn73xx;\n-\tstruct cvmx_l2c_big_ctl_cn70xx cn78xx;\n-\tstruct cvmx_l2c_big_ctl_cn70xx cn78xxp1;\n-\tstruct cvmx_l2c_big_ctl_cn61xx cnf71xx;\n-\tstruct cvmx_l2c_big_ctl_cn70xx cnf75xx;\n-};\n-\n-struct rlevel_byte_data {\n-\tint delay;\n-\tint loop_total;\n-\tint loop_count;\n-\tint best;\n-\tu64 bm;\n-\tint bmerrs;\n-\tint sqerrs;\n-\tint bestsq;\n-};\n-\n #define DEBUG_VALIDATE_BITMASK 0\n #if DEBUG_VALIDATE_BITMASK\n #define debug_bitmask_print printf\ndiff --git a/drivers/ram/octeon/octeon3_lmc.c b/drivers/ram/octeon/octeon3_lmc.c\nindex 327cdc5873..349abc179f 100644\n--- a/drivers/ram/octeon/octeon3_lmc.c\n+++ b/drivers/ram/octeon/octeon3_lmc.c\n@@ -17,14 +17,8 @@\n \n /* Random number generator stuff */\n \n-#define CVMX_RNM_CTL_STATUS\t0x0001180040000000\n #define CVMX_OCT_DID_RNG\t8ULL\n \n-static u64 cvmx_build_io_address(u64 major_did, u64 sub_did)\n-{\n-\treturn ((0x1ull << 48) | (major_did << 43) | (sub_did << 40));\n-}\n-\n static u64 cvmx_rng_get_random64(void)\n {\n \treturn csr_rd(cvmx_build_io_address(CVMX_OCT_DID_RNG, 0));\n@@ -285,10 +279,10 @@ static int test_dram_byte64(struct ddr_priv *priv, int lmc, u64 p,\n \tint node = 0;\n \n \t// Force full cacheline write-backs to boost traffic\n-\tl2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL);\n+\tl2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);\n \tsaved_dissblkdty = l2c_ctl.cn78xx.dissblkdty;\n \tl2c_ctl.cn78xx.dissblkdty = 1;\n-\tl2c_wr(priv, CVMX_L2C_CTL, l2c_ctl.u64);\n+\tl2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64);\n \n \tif (octeon_is_cpuid(OCTEON_CN73XX) || octeon_is_cpuid(OCTEON_CNF75XX))\n \t\tkbitno = 18;\n@@ -489,9 +483,9 @@ static int test_dram_byte64(struct ddr_priv *priv, int lmc, u64 p,\n \t}\n \n \t// Restore original setting that could enable partial cacheline writes\n-\tl2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL);\n+\tl2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);\n \tl2c_ctl.cn78xx.dissblkdty = saved_dissblkdty;\n-\tl2c_wr(priv, CVMX_L2C_CTL, l2c_ctl.u64);\n+\tl2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64);\n \n \treturn errors;\n }\n@@ -6315,17 +6309,17 @@ static void lmc_final(struct ddr_priv *priv)\n \tlmc_rd(priv, CVMX_LMCX_INT(if_num));\n \n \tfor (tad = 0; tad < num_tads; tad++) {\n-\t\tl2c_wr(priv, CVMX_L2C_TADX_INT(tad),\n-\t\t l2c_rd(priv, CVMX_L2C_TADX_INT(tad)));\n+\t\tl2c_wr(priv, CVMX_L2C_TADX_INT_REL(tad),\n+\t\t l2c_rd(priv, CVMX_L2C_TADX_INT_REL(tad)));\n \t\tdebug(\"%-45s : (%d) 0x%08llx\\n\", \"CVMX_L2C_TAD_INT\", tad,\n-\t\t l2c_rd(priv, CVMX_L2C_TADX_INT(tad)));\n+\t\t l2c_rd(priv, CVMX_L2C_TADX_INT_REL(tad)));\n \t}\n \n \tfor (mci = 0; mci < num_mcis; mci++) {\n-\t\tl2c_wr(priv, CVMX_L2C_MCIX_INT(mci),\n-\t\t l2c_rd(priv, CVMX_L2C_MCIX_INT(mci)));\n+\t\tl2c_wr(priv, CVMX_L2C_MCIX_INT_REL(mci),\n+\t\t l2c_rd(priv, CVMX_L2C_MCIX_INT_REL(mci)));\n \t\tdebug(\"%-45s : (%d) 0x%08llx\\n\", \"L2C_MCI_INT\", mci,\n-\t\t l2c_rd(priv, CVMX_L2C_MCIX_INT(mci)));\n+\t\t l2c_rd(priv, CVMX_L2C_MCIX_INT_REL(mci)));\n \t}\n \n \tdebug(\"%-45s : 0x%08llx\\n\", \"LMC_INT\",\n@@ -9827,7 +9821,7 @@ static void cvmx_dram_address_extract_info(struct ddr_priv *priv, u64 address,\n \t\taddress -= ADDRESS_HOLE;\n \n \t/* Determine the LMC controllers */\n-\tl2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL);\n+\tl2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);\n \n \t/* xbits depends on number of LMCs */\n \txbits = cvmx_dram_get_num_lmc(priv) >> 1;\t// 4->2, 2->1, 1->0\ndiff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c\nindex aaff9c3687..98f9646487 100644\n--- a/drivers/ram/octeon/octeon_ddr.c\n+++ b/drivers/ram/octeon/octeon_ddr.c\n@@ -144,7 +144,7 @@ static void cvmx_l2c_set_big_size(struct ddr_priv *priv, u64 mem_size, int mode)\n \t\tbig_ctl.u64 = 0;\n \t\tbig_ctl.s.maxdram = bits - 9;\n \t\tbig_ctl.cn61xx.disable = mode;\n-\t\tl2c_wr(priv, CVMX_L2C_BIG_CTL, big_ctl.u64);\n+\t\tl2c_wr(priv, CVMX_L2C_BIG_CTL_REL, big_ctl.u64);\n \t}\n }\n \n@@ -2273,15 +2273,15 @@ static int octeon_ddr_initialize(struct ddr_priv *priv, u32 cpu_hertz,\n \t\tprintf(\"Disabling L2 ECC based on disable_l2_ecc environment variable\\n\");\n \t\tunion cvmx_l2c_ctl l2c_val;\n \n-\t\tl2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL);\n+\t\tl2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);\n \t\tl2c_val.s.disecc = 1;\n-\t\tl2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64);\n+\t\tl2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64);\n \t} else {\n \t\tunion cvmx_l2c_ctl l2c_val;\n \n-\t\tl2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL);\n+\t\tl2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);\n \t\tl2c_val.s.disecc = 0;\n-\t\tl2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64);\n+\t\tl2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64);\n \t}\n \n \t/*\n@@ -2294,17 +2294,17 @@ static int octeon_ddr_initialize(struct ddr_priv *priv, u32 cpu_hertz,\n \n \t\tputs(\"L2 index aliasing disabled.\\n\");\n \n-\t\tl2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL);\n+\t\tl2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);\n \t\tl2c_val.s.disidxalias = 1;\n-\t\tl2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64);\n+\t\tl2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64);\n \t} else {\n \t\tunion cvmx_l2c_ctl l2c_val;\n \n \t\t/* Enable L2C index aliasing */\n \n-\t\tl2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL);\n+\t\tl2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);\n \t\tl2c_val.s.disidxalias = 0;\n-\t\tl2c_wr(priv, CVMX_L2C_CTL, l2c_val.u64);\n+\t\tl2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64);\n \t}\n \n \tif (OCTEON_IS_OCTEON3()) {\n@@ -2320,7 +2320,7 @@ static int octeon_ddr_initialize(struct ddr_priv *priv, u32 cpu_hertz,\n \t\tu64 rdf_cnt;\n \t\tchar *s;\n \n-\t\tl2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL);\n+\t\tl2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL);\n \n \t\t/*\n \t\t * It is more convenient to compute the ratio using clock\n@@ -2337,7 +2337,7 @@ static int octeon_ddr_initialize(struct ddr_priv *priv, u32 cpu_hertz,\n \t\tdebug(\"%-45s : %d, cpu_hertz:%d, ddr_hertz:%d\\n\",\n \t\t \"EARLY FILL COUNT \", l2c_ctl.cn78xx.rdf_cnt, cpu_hertz,\n \t\t ddr_hertz);\n-\t\tl2c_wr(priv, CVMX_L2C_CTL, l2c_ctl.u64);\n+\t\tl2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64);\n \t}\n \n \t/* Check for lower DIMM socket populated */\n", "prefixes": [ "v1", "34/50" ] }