Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 1415003,
    "url": "http://patchwork.ozlabs.org/api/patches/1415003/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-23-sr@denx.de/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20201211160612.1498780-23-sr@denx.de>",
    "list_archive_url": null,
    "date": "2020-12-11T16:05:44",
    "name": "[v1,22/50] mips: octeon: Add cvmx-pip-defs.h header file",
    "commit_ref": "784ad918d1e404f192dc2760f29f2f6b38235576",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "c97216c87cf5b17fe99471c64227a791a1638a8b",
    "submitter": {
        "id": 13,
        "url": "http://patchwork.ozlabs.org/api/people/13/?format=api",
        "name": "Stefan Roese",
        "email": "sr@denx.de"
    },
    "delegate": {
        "id": 4307,
        "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api",
        "username": "danielschwierzeck",
        "first_name": "Daniel",
        "last_name": "Schwierzeck",
        "email": "daniel.schwierzeck@googlemail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-23-sr@denx.de/mbox/",
    "series": [
        {
            "id": 220054,
            "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054",
            "date": "2020-12-11T16:05:23",
            "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1415003/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1415003/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<u-boot-bounces@lists.denx.de>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": [
            "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)",
            "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de",
            "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=khi3Nxf7;\n\tdkim-atps=neutral",
            "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de",
            "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de",
            "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de",
            "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de"
        ],
        "Received": [
            "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4CswlX3sl3z9sSs\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:11:52 +1100 (AEDT)",
            "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 57E3E826BC;\n\tFri, 11 Dec 2020 17:08:21 +0100 (CET)",
            "by phobos.denx.de (Postfix, from userid 109)\n id 21260827A0; Fri, 11 Dec 2020 17:07:43 +0100 (CET)",
            "from mx2.mailbox.org (mx2a.mailbox.org\n [IPv6:2001:67c:2050:104:0:2:25:2])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 67B9782730\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:26 +0100 (CET)",
            "from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id B2E0DA0BEB;\n Fri, 11 Dec 2020 17:06:25 +0100 (CET)",
            "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter06.heinlein-hosting.de (spamfilter06.heinlein-hosting.de\n [80.241.56.125]) (amavisd-new, port 10030)\n with ESMTP id bBnQp33wJ2NR; Fri, 11 Dec 2020 17:06:20 +0100 (CET)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702901;\n\tbh=j6paFAdSXRG+EzQzAn3wnymEdPWnWDey6ssTCFfzgDs=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=khi3Nxf7i6P/9R/RqhxRY1S8jWmNPIvYqlPncLS5EYQykvxZGy8CX1zKfzeslaydo\n\t r6Eu0OTzeL2Ydvh9o7+pSpiYfyhYmdnk7fn8CcIjERMzFkeOOeDM+w5i/U3Ow2oTMJ\n\t WMq4W4qsGvR6ayriX4/3gy9G2rX/odmrVAzie5AZFrgIPz1o9+7+TgYEfWsnZinlAi\n\t nhuhWx9KUqsW/m0rTpRLPm6KYublHNz1+B5bXT15fPFCYhaIMAcNzFbBIyY/On89mq\n\t W7DV72z/Ohufdh1SI2y1rsefrtUdkzpvr60gitZkD2WWeGwilkeziM54S7FheKdKEP\n\t 9zf88GURNocaQ==",
        "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de",
        "X-Spam-Level": "",
        "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2",
        "From": "Stefan Roese <sr@denx.de>",
        "To": "u-boot@lists.denx.de",
        "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com",
        "Subject": "[PATCH v1 22/50] mips: octeon: Add cvmx-pip-defs.h header file",
        "Date": "Fri, 11 Dec 2020 17:05:44 +0100",
        "Message-Id": "<20201211160612.1498780-23-sr@denx.de>",
        "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>",
        "References": "<20201211160612.1498780-1-sr@denx.de>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-MBO-SPAM-Probability": "",
        "X-Rspamd-Score": "-0.65 / 15.00 / 15.00",
        "X-Rspamd-Queue-Id": "94C371892",
        "X-Rspamd-UID": "ffdacd",
        "X-BeenThere": "u-boot@lists.denx.de",
        "X-Mailman-Version": "2.1.34",
        "Precedence": "list",
        "List-Id": "U-Boot discussion <u-boot.lists.denx.de>",
        "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>",
        "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>",
        "List-Post": "<mailto:u-boot@lists.denx.de>",
        "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>",
        "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>",
        "Errors-To": "u-boot-bounces@lists.denx.de",
        "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>",
        "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de",
        "X-Virus-Status": "Clean"
    },
    "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-pip-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-pip-defs.h  | 3040 +++++++++++++++++\n 1 file changed, 3040 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pip-defs.h",
    "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pip-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-pip-defs.h\nnew file mode 100644\nindex 0000000000..574e80b6f2\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-pip-defs.h\n@@ -0,0 +1,3040 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon pip.\n+ */\n+\n+#ifndef __CVMX_PIP_DEFS_H__\n+#define __CVMX_PIP_DEFS_H__\n+\n+#define CVMX_PIP_ALT_SKIP_CFGX(offset)\t     (0x00011800A0002A00ull + ((offset) & 3) * 8)\n+#define CVMX_PIP_BCK_PRS\t\t     (0x00011800A0000038ull)\n+#define CVMX_PIP_BIST_STATUS\t\t     (0x00011800A0000000ull)\n+#define CVMX_PIP_BSEL_EXT_CFGX(offset)\t     (0x00011800A0002800ull + ((offset) & 3) * 16)\n+#define CVMX_PIP_BSEL_EXT_POSX(offset)\t     (0x00011800A0002808ull + ((offset) & 3) * 16)\n+#define CVMX_PIP_BSEL_TBL_ENTX(offset)\t     (0x00011800A0003000ull + ((offset) & 511) * 8)\n+#define CVMX_PIP_CLKEN\t\t\t     (0x00011800A0000040ull)\n+#define CVMX_PIP_CRC_CTLX(offset)\t     (0x00011800A0000040ull + ((offset) & 1) * 8)\n+#define CVMX_PIP_CRC_IVX(offset)\t     (0x00011800A0000050ull + ((offset) & 1) * 8)\n+#define CVMX_PIP_DEC_IPSECX(offset)\t     (0x00011800A0000080ull + ((offset) & 3) * 8)\n+#define CVMX_PIP_DSA_SRC_GRP\t\t     (0x00011800A0000190ull)\n+#define CVMX_PIP_DSA_VID_GRP\t\t     (0x00011800A0000198ull)\n+#define CVMX_PIP_FRM_LEN_CHKX(offset)\t     (0x00011800A0000180ull + ((offset) & 1) * 8)\n+#define CVMX_PIP_GBL_CFG\t\t     (0x00011800A0000028ull)\n+#define CVMX_PIP_GBL_CTL\t\t     (0x00011800A0000020ull)\n+#define CVMX_PIP_HG_PRI_QOS\t\t     (0x00011800A00001A0ull)\n+#define CVMX_PIP_INT_EN\t\t\t     (0x00011800A0000010ull)\n+#define CVMX_PIP_INT_REG\t\t     (0x00011800A0000008ull)\n+#define CVMX_PIP_IP_OFFSET\t\t     (0x00011800A0000060ull)\n+#define CVMX_PIP_PRI_TBLX(offset)\t     (0x00011800A0004000ull + ((offset) & 255) * 8)\n+#define CVMX_PIP_PRT_CFGBX(offset)\t     (0x00011800A0008000ull + ((offset) & 63) * 8)\n+#define CVMX_PIP_PRT_CFGX(offset)\t     (0x00011800A0000200ull + ((offset) & 63) * 8)\n+#define CVMX_PIP_PRT_TAGX(offset)\t     (0x00011800A0000400ull + ((offset) & 63) * 8)\n+#define CVMX_PIP_QOS_DIFFX(offset)\t     (0x00011800A0000600ull + ((offset) & 63) * 8)\n+#define CVMX_PIP_QOS_VLANX(offset)\t     (0x00011800A00000C0ull + ((offset) & 7) * 8)\n+#define CVMX_PIP_QOS_WATCHX(offset)\t     (0x00011800A0000100ull + ((offset) & 7) * 8)\n+#define CVMX_PIP_RAW_WORD\t\t     (0x00011800A00000B0ull)\n+#define CVMX_PIP_SFT_RST\t\t     (0x00011800A0000030ull)\n+#define CVMX_PIP_STAT0_PRTX(offset)\t     (0x00011800A0000800ull + ((offset) & 63) * 80)\n+#define CVMX_PIP_STAT0_X(offset)\t     (0x00011800A0040000ull + ((offset) & 63) * 128)\n+#define CVMX_PIP_STAT10_PRTX(offset)\t     (0x00011800A0001480ull + ((offset) & 63) * 16)\n+#define CVMX_PIP_STAT10_X(offset)\t     (0x00011800A0040050ull + ((offset) & 63) * 128)\n+#define CVMX_PIP_STAT11_PRTX(offset)\t     (0x00011800A0001488ull + ((offset) & 63) * 16)\n+#define CVMX_PIP_STAT11_X(offset)\t     (0x00011800A0040058ull + ((offset) & 63) * 128)\n+#define CVMX_PIP_STAT1_PRTX(offset)\t     (0x00011800A0000808ull + ((offset) & 63) * 80)\n+#define CVMX_PIP_STAT1_X(offset)\t     (0x00011800A0040008ull + ((offset) & 63) * 128)\n+#define CVMX_PIP_STAT2_PRTX(offset)\t     (0x00011800A0000810ull + ((offset) & 63) * 80)\n+#define CVMX_PIP_STAT2_X(offset)\t     (0x00011800A0040010ull + ((offset) & 63) * 128)\n+#define CVMX_PIP_STAT3_PRTX(offset)\t     (0x00011800A0000818ull + ((offset) & 63) * 80)\n+#define CVMX_PIP_STAT3_X(offset)\t     (0x00011800A0040018ull + ((offset) & 63) * 128)\n+#define CVMX_PIP_STAT4_PRTX(offset)\t     (0x00011800A0000820ull + ((offset) & 63) * 80)\n+#define CVMX_PIP_STAT4_X(offset)\t     (0x00011800A0040020ull + ((offset) & 63) * 128)\n+#define CVMX_PIP_STAT5_PRTX(offset)\t     (0x00011800A0000828ull + ((offset) & 63) * 80)\n+#define CVMX_PIP_STAT5_X(offset)\t     (0x00011800A0040028ull + ((offset) & 63) * 128)\n+#define CVMX_PIP_STAT6_PRTX(offset)\t     (0x00011800A0000830ull + ((offset) & 63) * 80)\n+#define CVMX_PIP_STAT6_X(offset)\t     (0x00011800A0040030ull + ((offset) & 63) * 128)\n+#define CVMX_PIP_STAT7_PRTX(offset)\t     (0x00011800A0000838ull + ((offset) & 63) * 80)\n+#define CVMX_PIP_STAT7_X(offset)\t     (0x00011800A0040038ull + ((offset) & 63) * 128)\n+#define CVMX_PIP_STAT8_PRTX(offset)\t     (0x00011800A0000840ull + ((offset) & 63) * 80)\n+#define CVMX_PIP_STAT8_X(offset)\t     (0x00011800A0040040ull + ((offset) & 63) * 128)\n+#define CVMX_PIP_STAT9_PRTX(offset)\t     (0x00011800A0000848ull + ((offset) & 63) * 80)\n+#define CVMX_PIP_STAT9_X(offset)\t     (0x00011800A0040048ull + ((offset) & 63) * 128)\n+#define CVMX_PIP_STAT_CTL\t\t     (0x00011800A0000018ull)\n+#define CVMX_PIP_STAT_INB_ERRSX(offset)\t     (0x00011800A0001A10ull + ((offset) & 63) * 32)\n+#define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (0x00011800A0020010ull + ((offset) & 63) * 32)\n+#define CVMX_PIP_STAT_INB_OCTSX(offset)\t     (0x00011800A0001A08ull + ((offset) & 63) * 32)\n+#define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (0x00011800A0020008ull + ((offset) & 63) * 32)\n+#define CVMX_PIP_STAT_INB_PKTSX(offset)\t     (0x00011800A0001A00ull + ((offset) & 63) * 32)\n+#define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (0x00011800A0020000ull + ((offset) & 63) * 32)\n+#define CVMX_PIP_SUB_PKIND_FCSX(offset)\t     (0x00011800A0080000ull)\n+#define CVMX_PIP_TAG_INCX(offset)\t     (0x00011800A0001800ull + ((offset) & 63) * 8)\n+#define CVMX_PIP_TAG_MASK\t\t     (0x00011800A0000070ull)\n+#define CVMX_PIP_TAG_SECRET\t\t     (0x00011800A0000068ull)\n+#define CVMX_PIP_TODO_ENTRY\t\t     (0x00011800A0000078ull)\n+#define CVMX_PIP_VLAN_ETYPESX(offset)\t     (0x00011800A00001C0ull + ((offset) & 1) * 8)\n+#define CVMX_PIP_XSTAT0_PRTX(offset)\t     (0x00011800A0002000ull + ((offset) & 63) * 80 - 80 * 40)\n+#define CVMX_PIP_XSTAT10_PRTX(offset)\t     (0x00011800A0001700ull + ((offset) & 63) * 16 - 16 * 40)\n+#define CVMX_PIP_XSTAT11_PRTX(offset)\t     (0x00011800A0001708ull + ((offset) & 63) * 16 - 16 * 40)\n+#define CVMX_PIP_XSTAT1_PRTX(offset)\t     (0x00011800A0002008ull + ((offset) & 63) * 80 - 80 * 40)\n+#define CVMX_PIP_XSTAT2_PRTX(offset)\t     (0x00011800A0002010ull + ((offset) & 63) * 80 - 80 * 40)\n+#define CVMX_PIP_XSTAT3_PRTX(offset)\t     (0x00011800A0002018ull + ((offset) & 63) * 80 - 80 * 40)\n+#define CVMX_PIP_XSTAT4_PRTX(offset)\t     (0x00011800A0002020ull + ((offset) & 63) * 80 - 80 * 40)\n+#define CVMX_PIP_XSTAT5_PRTX(offset)\t     (0x00011800A0002028ull + ((offset) & 63) * 80 - 80 * 40)\n+#define CVMX_PIP_XSTAT6_PRTX(offset)\t     (0x00011800A0002030ull + ((offset) & 63) * 80 - 80 * 40)\n+#define CVMX_PIP_XSTAT7_PRTX(offset)\t     (0x00011800A0002038ull + ((offset) & 63) * 80 - 80 * 40)\n+#define CVMX_PIP_XSTAT8_PRTX(offset)\t     (0x00011800A0002040ull + ((offset) & 63) * 80 - 80 * 40)\n+#define CVMX_PIP_XSTAT9_PRTX(offset)\t     (0x00011800A0002048ull + ((offset) & 63) * 80 - 80 * 40)\n+\n+/**\n+ * cvmx_pip_alt_skip_cfg#\n+ *\n+ * Notes:\n+ * The actual SKIP I determined by HW is based on the packet contents.  BIT0 and\n+ * BIT1 make up a two value value that the selects the skip value as follows.\n+ *\n+ *    lookup_value = LEN ? ( packet_in_bits[BIT1], packet_in_bits[BIT0] ) : ( 0, packet_in_bits[BIT0] );\n+ *    SKIP I       = lookup_value == 3 ? SKIP3 :\n+ *                   lookup_value == 2 ? SKIP2 :\n+ *                   lookup_value == 1 ? SKIP1 :\n+ *                   PIP_PRT_CFG<pknd>[SKIP];\n+ */\n+union cvmx_pip_alt_skip_cfgx {\n+\tu64 u64;\n+\tstruct cvmx_pip_alt_skip_cfgx_s {\n+\t\tu64 reserved_57_63 : 7;\n+\t\tu64 len : 1;\n+\t\tu64 reserved_46_55 : 10;\n+\t\tu64 bit1 : 6;\n+\t\tu64 reserved_38_39 : 2;\n+\t\tu64 bit0 : 6;\n+\t\tu64 reserved_23_31 : 9;\n+\t\tu64 skip3 : 7;\n+\t\tu64 reserved_15_15 : 1;\n+\t\tu64 skip2 : 7;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 skip1 : 7;\n+\t} s;\n+\tstruct cvmx_pip_alt_skip_cfgx_s cn61xx;\n+\tstruct cvmx_pip_alt_skip_cfgx_s cn66xx;\n+\tstruct cvmx_pip_alt_skip_cfgx_s cn68xx;\n+\tstruct cvmx_pip_alt_skip_cfgx_s cn70xx;\n+\tstruct cvmx_pip_alt_skip_cfgx_s cn70xxp1;\n+\tstruct cvmx_pip_alt_skip_cfgx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_alt_skip_cfgx cvmx_pip_alt_skip_cfgx_t;\n+\n+/**\n+ * cvmx_pip_bck_prs\n+ *\n+ * When to assert backpressure based on the todo list filling up\n+ *\n+ */\n+union cvmx_pip_bck_prs {\n+\tu64 u64;\n+\tstruct cvmx_pip_bck_prs_s {\n+\t\tu64 bckprs : 1;\n+\t\tu64 reserved_13_62 : 50;\n+\t\tu64 hiwater : 5;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 lowater : 5;\n+\t} s;\n+\tstruct cvmx_pip_bck_prs_s cn38xx;\n+\tstruct cvmx_pip_bck_prs_s cn38xxp2;\n+\tstruct cvmx_pip_bck_prs_s cn56xx;\n+\tstruct cvmx_pip_bck_prs_s cn56xxp1;\n+\tstruct cvmx_pip_bck_prs_s cn58xx;\n+\tstruct cvmx_pip_bck_prs_s cn58xxp1;\n+\tstruct cvmx_pip_bck_prs_s cn61xx;\n+\tstruct cvmx_pip_bck_prs_s cn63xx;\n+\tstruct cvmx_pip_bck_prs_s cn63xxp1;\n+\tstruct cvmx_pip_bck_prs_s cn66xx;\n+\tstruct cvmx_pip_bck_prs_s cn68xx;\n+\tstruct cvmx_pip_bck_prs_s cn68xxp1;\n+\tstruct cvmx_pip_bck_prs_s cn70xx;\n+\tstruct cvmx_pip_bck_prs_s cn70xxp1;\n+\tstruct cvmx_pip_bck_prs_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_bck_prs cvmx_pip_bck_prs_t;\n+\n+/**\n+ * cvmx_pip_bist_status\n+ *\n+ * PIP_BIST_STATUS = PIP's BIST Results\n+ *\n+ */\n+union cvmx_pip_bist_status {\n+\tu64 u64;\n+\tstruct cvmx_pip_bist_status_s {\n+\t\tu64 reserved_22_63 : 42;\n+\t\tu64 bist : 22;\n+\t} s;\n+\tstruct cvmx_pip_bist_status_cn30xx {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 bist : 18;\n+\t} cn30xx;\n+\tstruct cvmx_pip_bist_status_cn30xx cn31xx;\n+\tstruct cvmx_pip_bist_status_cn30xx cn38xx;\n+\tstruct cvmx_pip_bist_status_cn30xx cn38xxp2;\n+\tstruct cvmx_pip_bist_status_cn50xx {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 bist : 17;\n+\t} cn50xx;\n+\tstruct cvmx_pip_bist_status_cn30xx cn52xx;\n+\tstruct cvmx_pip_bist_status_cn30xx cn52xxp1;\n+\tstruct cvmx_pip_bist_status_cn30xx cn56xx;\n+\tstruct cvmx_pip_bist_status_cn30xx cn56xxp1;\n+\tstruct cvmx_pip_bist_status_cn30xx cn58xx;\n+\tstruct cvmx_pip_bist_status_cn30xx cn58xxp1;\n+\tstruct cvmx_pip_bist_status_cn61xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 bist : 20;\n+\t} cn61xx;\n+\tstruct cvmx_pip_bist_status_cn30xx cn63xx;\n+\tstruct cvmx_pip_bist_status_cn30xx cn63xxp1;\n+\tstruct cvmx_pip_bist_status_cn61xx cn66xx;\n+\tstruct cvmx_pip_bist_status_s cn68xx;\n+\tstruct cvmx_pip_bist_status_cn61xx cn68xxp1;\n+\tstruct cvmx_pip_bist_status_cn61xx cn70xx;\n+\tstruct cvmx_pip_bist_status_cn61xx cn70xxp1;\n+\tstruct cvmx_pip_bist_status_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_pip_bist_status cvmx_pip_bist_status_t;\n+\n+/**\n+ * cvmx_pip_bsel_ext_cfg#\n+ *\n+ * tag, offset, and skip values to be used when using the corresponding extractor.\n+ *\n+ */\n+union cvmx_pip_bsel_ext_cfgx {\n+\tu64 u64;\n+\tstruct cvmx_pip_bsel_ext_cfgx_s {\n+\t\tu64 reserved_56_63 : 8;\n+\t\tu64 upper_tag : 16;\n+\t\tu64 tag : 8;\n+\t\tu64 reserved_25_31 : 7;\n+\t\tu64 offset : 9;\n+\t\tu64 reserved_7_15 : 9;\n+\t\tu64 skip : 7;\n+\t} s;\n+\tstruct cvmx_pip_bsel_ext_cfgx_s cn61xx;\n+\tstruct cvmx_pip_bsel_ext_cfgx_s cn68xx;\n+\tstruct cvmx_pip_bsel_ext_cfgx_s cn70xx;\n+\tstruct cvmx_pip_bsel_ext_cfgx_s cn70xxp1;\n+\tstruct cvmx_pip_bsel_ext_cfgx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_bsel_ext_cfgx cvmx_pip_bsel_ext_cfgx_t;\n+\n+/**\n+ * cvmx_pip_bsel_ext_pos#\n+ *\n+ * bit positions and valids to be used when using the corresponding extractor.\n+ *\n+ */\n+union cvmx_pip_bsel_ext_posx {\n+\tu64 u64;\n+\tstruct cvmx_pip_bsel_ext_posx_s {\n+\t\tu64 pos7_val : 1;\n+\t\tu64 pos7 : 7;\n+\t\tu64 pos6_val : 1;\n+\t\tu64 pos6 : 7;\n+\t\tu64 pos5_val : 1;\n+\t\tu64 pos5 : 7;\n+\t\tu64 pos4_val : 1;\n+\t\tu64 pos4 : 7;\n+\t\tu64 pos3_val : 1;\n+\t\tu64 pos3 : 7;\n+\t\tu64 pos2_val : 1;\n+\t\tu64 pos2 : 7;\n+\t\tu64 pos1_val : 1;\n+\t\tu64 pos1 : 7;\n+\t\tu64 pos0_val : 1;\n+\t\tu64 pos0 : 7;\n+\t} s;\n+\tstruct cvmx_pip_bsel_ext_posx_s cn61xx;\n+\tstruct cvmx_pip_bsel_ext_posx_s cn68xx;\n+\tstruct cvmx_pip_bsel_ext_posx_s cn70xx;\n+\tstruct cvmx_pip_bsel_ext_posx_s cn70xxp1;\n+\tstruct cvmx_pip_bsel_ext_posx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_bsel_ext_posx cvmx_pip_bsel_ext_posx_t;\n+\n+/**\n+ * cvmx_pip_bsel_tbl_ent#\n+ *\n+ * PIP_BSEL_TBL_ENTX = Entry for the extractor table\n+ *\n+ */\n+union cvmx_pip_bsel_tbl_entx {\n+\tu64 u64;\n+\tstruct cvmx_pip_bsel_tbl_entx_s {\n+\t\tu64 tag_en : 1;\n+\t\tu64 grp_en : 1;\n+\t\tu64 tt_en : 1;\n+\t\tu64 qos_en : 1;\n+\t\tu64 reserved_40_59 : 20;\n+\t\tu64 tag : 8;\n+\t\tu64 reserved_22_31 : 10;\n+\t\tu64 grp : 6;\n+\t\tu64 reserved_10_15 : 6;\n+\t\tu64 tt : 2;\n+\t\tu64 reserved_3_7 : 5;\n+\t\tu64 qos : 3;\n+\t} s;\n+\tstruct cvmx_pip_bsel_tbl_entx_cn61xx {\n+\t\tu64 tag_en : 1;\n+\t\tu64 grp_en : 1;\n+\t\tu64 tt_en : 1;\n+\t\tu64 qos_en : 1;\n+\t\tu64 reserved_40_59 : 20;\n+\t\tu64 tag : 8;\n+\t\tu64 reserved_20_31 : 12;\n+\t\tu64 grp : 4;\n+\t\tu64 reserved_10_15 : 6;\n+\t\tu64 tt : 2;\n+\t\tu64 reserved_3_7 : 5;\n+\t\tu64 qos : 3;\n+\t} cn61xx;\n+\tstruct cvmx_pip_bsel_tbl_entx_s cn68xx;\n+\tstruct cvmx_pip_bsel_tbl_entx_cn61xx cn70xx;\n+\tstruct cvmx_pip_bsel_tbl_entx_cn61xx cn70xxp1;\n+\tstruct cvmx_pip_bsel_tbl_entx_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_pip_bsel_tbl_entx cvmx_pip_bsel_tbl_entx_t;\n+\n+/**\n+ * cvmx_pip_clken\n+ */\n+union cvmx_pip_clken {\n+\tu64 u64;\n+\tstruct cvmx_pip_clken_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 clken : 1;\n+\t} s;\n+\tstruct cvmx_pip_clken_s cn61xx;\n+\tstruct cvmx_pip_clken_s cn63xx;\n+\tstruct cvmx_pip_clken_s cn63xxp1;\n+\tstruct cvmx_pip_clken_s cn66xx;\n+\tstruct cvmx_pip_clken_s cn68xx;\n+\tstruct cvmx_pip_clken_s cn68xxp1;\n+\tstruct cvmx_pip_clken_s cn70xx;\n+\tstruct cvmx_pip_clken_s cn70xxp1;\n+\tstruct cvmx_pip_clken_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_clken cvmx_pip_clken_t;\n+\n+/**\n+ * cvmx_pip_crc_ctl#\n+ *\n+ * PIP_CRC_CTL = PIP CRC Control Register\n+ *\n+ * Controls datapath reflection when calculating CRC\n+ */\n+union cvmx_pip_crc_ctlx {\n+\tu64 u64;\n+\tstruct cvmx_pip_crc_ctlx_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 invres : 1;\n+\t\tu64 reflect : 1;\n+\t} s;\n+\tstruct cvmx_pip_crc_ctlx_s cn38xx;\n+\tstruct cvmx_pip_crc_ctlx_s cn38xxp2;\n+\tstruct cvmx_pip_crc_ctlx_s cn58xx;\n+\tstruct cvmx_pip_crc_ctlx_s cn58xxp1;\n+};\n+\n+typedef union cvmx_pip_crc_ctlx cvmx_pip_crc_ctlx_t;\n+\n+/**\n+ * cvmx_pip_crc_iv#\n+ *\n+ * PIP_CRC_IV = PIP CRC IV Register\n+ *\n+ * Determines the IV used by the CRC algorithm\n+ *\n+ * Notes:\n+ * * PIP_CRC_IV\n+ * PIP_CRC_IV controls the initial state of the CRC algorithm.  Octane can\n+ * support a wide range of CRC algorithms and as such, the IV must be\n+ * carefully constructed to meet the specific algorithm.  The code below\n+ * determines the value to program into Octane based on the algorthim's IV\n+ * and width.  In the case of Octane, the width should always be 32.\n+ *\n+ * PIP_CRC_IV0 sets the IV for ports 0-15 while PIP_CRC_IV1 sets the IV for\n+ * ports 16-31.\n+ *\n+ *  unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w)\n+ *  [\n+ *    int i;\n+ *    int doit;\n+ *    unsigned int current_val = algorithm_iv;\n+ *\n+ *    for(i = 0; i < w; i++) [\n+ *      doit = current_val & 0x1;\n+ *\n+ *      if(doit) current_val ^= poly;\n+ *      assert(!(current_val & 0x1));\n+ *\n+ *      current_val = (current_val >> 1) | (doit << (w-1));\n+ *    ]\n+ *\n+ *    return current_val;\n+ *  ]\n+ */\n+union cvmx_pip_crc_ivx {\n+\tu64 u64;\n+\tstruct cvmx_pip_crc_ivx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 iv : 32;\n+\t} s;\n+\tstruct cvmx_pip_crc_ivx_s cn38xx;\n+\tstruct cvmx_pip_crc_ivx_s cn38xxp2;\n+\tstruct cvmx_pip_crc_ivx_s cn58xx;\n+\tstruct cvmx_pip_crc_ivx_s cn58xxp1;\n+};\n+\n+typedef union cvmx_pip_crc_ivx cvmx_pip_crc_ivx_t;\n+\n+/**\n+ * cvmx_pip_dec_ipsec#\n+ *\n+ * PIP sets the dec_ipsec based on TCP or UDP destination port.\n+ *\n+ */\n+union cvmx_pip_dec_ipsecx {\n+\tu64 u64;\n+\tstruct cvmx_pip_dec_ipsecx_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 tcp : 1;\n+\t\tu64 udp : 1;\n+\t\tu64 dprt : 16;\n+\t} s;\n+\tstruct cvmx_pip_dec_ipsecx_s cn30xx;\n+\tstruct cvmx_pip_dec_ipsecx_s cn31xx;\n+\tstruct cvmx_pip_dec_ipsecx_s cn38xx;\n+\tstruct cvmx_pip_dec_ipsecx_s cn38xxp2;\n+\tstruct cvmx_pip_dec_ipsecx_s cn50xx;\n+\tstruct cvmx_pip_dec_ipsecx_s cn52xx;\n+\tstruct cvmx_pip_dec_ipsecx_s cn52xxp1;\n+\tstruct cvmx_pip_dec_ipsecx_s cn56xx;\n+\tstruct cvmx_pip_dec_ipsecx_s cn56xxp1;\n+\tstruct cvmx_pip_dec_ipsecx_s cn58xx;\n+\tstruct cvmx_pip_dec_ipsecx_s cn58xxp1;\n+\tstruct cvmx_pip_dec_ipsecx_s cn61xx;\n+\tstruct cvmx_pip_dec_ipsecx_s cn63xx;\n+\tstruct cvmx_pip_dec_ipsecx_s cn63xxp1;\n+\tstruct cvmx_pip_dec_ipsecx_s cn66xx;\n+\tstruct cvmx_pip_dec_ipsecx_s cn68xx;\n+\tstruct cvmx_pip_dec_ipsecx_s cn68xxp1;\n+\tstruct cvmx_pip_dec_ipsecx_s cn70xx;\n+\tstruct cvmx_pip_dec_ipsecx_s cn70xxp1;\n+\tstruct cvmx_pip_dec_ipsecx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_dec_ipsecx cvmx_pip_dec_ipsecx_t;\n+\n+/**\n+ * cvmx_pip_dsa_src_grp\n+ */\n+union cvmx_pip_dsa_src_grp {\n+\tu64 u64;\n+\tstruct cvmx_pip_dsa_src_grp_s {\n+\t\tu64 map15 : 4;\n+\t\tu64 map14 : 4;\n+\t\tu64 map13 : 4;\n+\t\tu64 map12 : 4;\n+\t\tu64 map11 : 4;\n+\t\tu64 map10 : 4;\n+\t\tu64 map9 : 4;\n+\t\tu64 map8 : 4;\n+\t\tu64 map7 : 4;\n+\t\tu64 map6 : 4;\n+\t\tu64 map5 : 4;\n+\t\tu64 map4 : 4;\n+\t\tu64 map3 : 4;\n+\t\tu64 map2 : 4;\n+\t\tu64 map1 : 4;\n+\t\tu64 map0 : 4;\n+\t} s;\n+\tstruct cvmx_pip_dsa_src_grp_s cn52xx;\n+\tstruct cvmx_pip_dsa_src_grp_s cn52xxp1;\n+\tstruct cvmx_pip_dsa_src_grp_s cn56xx;\n+\tstruct cvmx_pip_dsa_src_grp_s cn61xx;\n+\tstruct cvmx_pip_dsa_src_grp_s cn63xx;\n+\tstruct cvmx_pip_dsa_src_grp_s cn63xxp1;\n+\tstruct cvmx_pip_dsa_src_grp_s cn66xx;\n+\tstruct cvmx_pip_dsa_src_grp_s cn68xx;\n+\tstruct cvmx_pip_dsa_src_grp_s cn68xxp1;\n+\tstruct cvmx_pip_dsa_src_grp_s cn70xx;\n+\tstruct cvmx_pip_dsa_src_grp_s cn70xxp1;\n+\tstruct cvmx_pip_dsa_src_grp_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_dsa_src_grp cvmx_pip_dsa_src_grp_t;\n+\n+/**\n+ * cvmx_pip_dsa_vid_grp\n+ */\n+union cvmx_pip_dsa_vid_grp {\n+\tu64 u64;\n+\tstruct cvmx_pip_dsa_vid_grp_s {\n+\t\tu64 map15 : 4;\n+\t\tu64 map14 : 4;\n+\t\tu64 map13 : 4;\n+\t\tu64 map12 : 4;\n+\t\tu64 map11 : 4;\n+\t\tu64 map10 : 4;\n+\t\tu64 map9 : 4;\n+\t\tu64 map8 : 4;\n+\t\tu64 map7 : 4;\n+\t\tu64 map6 : 4;\n+\t\tu64 map5 : 4;\n+\t\tu64 map4 : 4;\n+\t\tu64 map3 : 4;\n+\t\tu64 map2 : 4;\n+\t\tu64 map1 : 4;\n+\t\tu64 map0 : 4;\n+\t} s;\n+\tstruct cvmx_pip_dsa_vid_grp_s cn52xx;\n+\tstruct cvmx_pip_dsa_vid_grp_s cn52xxp1;\n+\tstruct cvmx_pip_dsa_vid_grp_s cn56xx;\n+\tstruct cvmx_pip_dsa_vid_grp_s cn61xx;\n+\tstruct cvmx_pip_dsa_vid_grp_s cn63xx;\n+\tstruct cvmx_pip_dsa_vid_grp_s cn63xxp1;\n+\tstruct cvmx_pip_dsa_vid_grp_s cn66xx;\n+\tstruct cvmx_pip_dsa_vid_grp_s cn68xx;\n+\tstruct cvmx_pip_dsa_vid_grp_s cn68xxp1;\n+\tstruct cvmx_pip_dsa_vid_grp_s cn70xx;\n+\tstruct cvmx_pip_dsa_vid_grp_s cn70xxp1;\n+\tstruct cvmx_pip_dsa_vid_grp_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_dsa_vid_grp cvmx_pip_dsa_vid_grp_t;\n+\n+/**\n+ * cvmx_pip_frm_len_chk#\n+ *\n+ * Notes:\n+ * PIP_FRM_LEN_CHK0 is used for packets on packet interface0, PCI, PCI RAW, and PKO loopback ports.\n+ * PIP_FRM_LEN_CHK1 is unused.\n+ */\n+union cvmx_pip_frm_len_chkx {\n+\tu64 u64;\n+\tstruct cvmx_pip_frm_len_chkx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 maxlen : 16;\n+\t\tu64 minlen : 16;\n+\t} s;\n+\tstruct cvmx_pip_frm_len_chkx_s cn50xx;\n+\tstruct cvmx_pip_frm_len_chkx_s cn52xx;\n+\tstruct cvmx_pip_frm_len_chkx_s cn52xxp1;\n+\tstruct cvmx_pip_frm_len_chkx_s cn56xx;\n+\tstruct cvmx_pip_frm_len_chkx_s cn56xxp1;\n+\tstruct cvmx_pip_frm_len_chkx_s cn61xx;\n+\tstruct cvmx_pip_frm_len_chkx_s cn63xx;\n+\tstruct cvmx_pip_frm_len_chkx_s cn63xxp1;\n+\tstruct cvmx_pip_frm_len_chkx_s cn66xx;\n+\tstruct cvmx_pip_frm_len_chkx_s cn68xx;\n+\tstruct cvmx_pip_frm_len_chkx_s cn68xxp1;\n+\tstruct cvmx_pip_frm_len_chkx_s cn70xx;\n+\tstruct cvmx_pip_frm_len_chkx_s cn70xxp1;\n+\tstruct cvmx_pip_frm_len_chkx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_frm_len_chkx cvmx_pip_frm_len_chkx_t;\n+\n+/**\n+ * cvmx_pip_gbl_cfg\n+ *\n+ * Global config information that applies to all ports.\n+ *\n+ */\n+union cvmx_pip_gbl_cfg {\n+\tu64 u64;\n+\tstruct cvmx_pip_gbl_cfg_s {\n+\t\tu64 reserved_19_63 : 45;\n+\t\tu64 tag_syn : 1;\n+\t\tu64 ip6_udp : 1;\n+\t\tu64 max_l2 : 1;\n+\t\tu64 reserved_11_15 : 5;\n+\t\tu64 raw_shf : 3;\n+\t\tu64 reserved_3_7 : 5;\n+\t\tu64 nip_shf : 3;\n+\t} s;\n+\tstruct cvmx_pip_gbl_cfg_s cn30xx;\n+\tstruct cvmx_pip_gbl_cfg_s cn31xx;\n+\tstruct cvmx_pip_gbl_cfg_s cn38xx;\n+\tstruct cvmx_pip_gbl_cfg_s cn38xxp2;\n+\tstruct cvmx_pip_gbl_cfg_s cn50xx;\n+\tstruct cvmx_pip_gbl_cfg_s cn52xx;\n+\tstruct cvmx_pip_gbl_cfg_s cn52xxp1;\n+\tstruct cvmx_pip_gbl_cfg_s cn56xx;\n+\tstruct cvmx_pip_gbl_cfg_s cn56xxp1;\n+\tstruct cvmx_pip_gbl_cfg_s cn58xx;\n+\tstruct cvmx_pip_gbl_cfg_s cn58xxp1;\n+\tstruct cvmx_pip_gbl_cfg_s cn61xx;\n+\tstruct cvmx_pip_gbl_cfg_s cn63xx;\n+\tstruct cvmx_pip_gbl_cfg_s cn63xxp1;\n+\tstruct cvmx_pip_gbl_cfg_s cn66xx;\n+\tstruct cvmx_pip_gbl_cfg_s cn68xx;\n+\tstruct cvmx_pip_gbl_cfg_s cn68xxp1;\n+\tstruct cvmx_pip_gbl_cfg_s cn70xx;\n+\tstruct cvmx_pip_gbl_cfg_s cn70xxp1;\n+\tstruct cvmx_pip_gbl_cfg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_gbl_cfg cvmx_pip_gbl_cfg_t;\n+\n+/**\n+ * cvmx_pip_gbl_ctl\n+ *\n+ * Global control information.  These are the global checker enables for\n+ * IPv4/IPv6 and TCP/UDP parsing.  The enables effect all ports.\n+ */\n+union cvmx_pip_gbl_ctl {\n+\tu64 u64;\n+\tstruct cvmx_pip_gbl_ctl_s {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 egrp_dis : 1;\n+\t\tu64 ihmsk_dis : 1;\n+\t\tu64 dsa_grp_tvid : 1;\n+\t\tu64 dsa_grp_scmd : 1;\n+\t\tu64 dsa_grp_sid : 1;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 ring_en : 1;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 ignrs : 1;\n+\t\tu64 vs_wqe : 1;\n+\t\tu64 vs_qos : 1;\n+\t\tu64 l2_mal : 1;\n+\t\tu64 tcp_flag : 1;\n+\t\tu64 l4_len : 1;\n+\t\tu64 l4_chk : 1;\n+\t\tu64 l4_prt : 1;\n+\t\tu64 l4_mal : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ip6_eext : 2;\n+\t\tu64 ip4_opts : 1;\n+\t\tu64 ip_hop : 1;\n+\t\tu64 ip_mal : 1;\n+\t\tu64 ip_chk : 1;\n+\t} s;\n+\tstruct cvmx_pip_gbl_ctl_cn30xx {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 ignrs : 1;\n+\t\tu64 vs_wqe : 1;\n+\t\tu64 vs_qos : 1;\n+\t\tu64 l2_mal : 1;\n+\t\tu64 tcp_flag : 1;\n+\t\tu64 l4_len : 1;\n+\t\tu64 l4_chk : 1;\n+\t\tu64 l4_prt : 1;\n+\t\tu64 l4_mal : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ip6_eext : 2;\n+\t\tu64 ip4_opts : 1;\n+\t\tu64 ip_hop : 1;\n+\t\tu64 ip_mal : 1;\n+\t\tu64 ip_chk : 1;\n+\t} cn30xx;\n+\tstruct cvmx_pip_gbl_ctl_cn30xx cn31xx;\n+\tstruct cvmx_pip_gbl_ctl_cn30xx cn38xx;\n+\tstruct cvmx_pip_gbl_ctl_cn30xx cn38xxp2;\n+\tstruct cvmx_pip_gbl_ctl_cn30xx cn50xx;\n+\tstruct cvmx_pip_gbl_ctl_cn52xx {\n+\t\tu64 reserved_27_63 : 37;\n+\t\tu64 dsa_grp_tvid : 1;\n+\t\tu64 dsa_grp_scmd : 1;\n+\t\tu64 dsa_grp_sid : 1;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 ring_en : 1;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 ignrs : 1;\n+\t\tu64 vs_wqe : 1;\n+\t\tu64 vs_qos : 1;\n+\t\tu64 l2_mal : 1;\n+\t\tu64 tcp_flag : 1;\n+\t\tu64 l4_len : 1;\n+\t\tu64 l4_chk : 1;\n+\t\tu64 l4_prt : 1;\n+\t\tu64 l4_mal : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ip6_eext : 2;\n+\t\tu64 ip4_opts : 1;\n+\t\tu64 ip_hop : 1;\n+\t\tu64 ip_mal : 1;\n+\t\tu64 ip_chk : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pip_gbl_ctl_cn52xx cn52xxp1;\n+\tstruct cvmx_pip_gbl_ctl_cn52xx cn56xx;\n+\tstruct cvmx_pip_gbl_ctl_cn56xxp1 {\n+\t\tu64 reserved_21_63 : 43;\n+\t\tu64 ring_en : 1;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 ignrs : 1;\n+\t\tu64 vs_wqe : 1;\n+\t\tu64 vs_qos : 1;\n+\t\tu64 l2_mal : 1;\n+\t\tu64 tcp_flag : 1;\n+\t\tu64 l4_len : 1;\n+\t\tu64 l4_chk : 1;\n+\t\tu64 l4_prt : 1;\n+\t\tu64 l4_mal : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ip6_eext : 2;\n+\t\tu64 ip4_opts : 1;\n+\t\tu64 ip_hop : 1;\n+\t\tu64 ip_mal : 1;\n+\t\tu64 ip_chk : 1;\n+\t} cn56xxp1;\n+\tstruct cvmx_pip_gbl_ctl_cn30xx cn58xx;\n+\tstruct cvmx_pip_gbl_ctl_cn30xx cn58xxp1;\n+\tstruct cvmx_pip_gbl_ctl_cn61xx {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 ihmsk_dis : 1;\n+\t\tu64 dsa_grp_tvid : 1;\n+\t\tu64 dsa_grp_scmd : 1;\n+\t\tu64 dsa_grp_sid : 1;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 ring_en : 1;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 ignrs : 1;\n+\t\tu64 vs_wqe : 1;\n+\t\tu64 vs_qos : 1;\n+\t\tu64 l2_mal : 1;\n+\t\tu64 tcp_flag : 1;\n+\t\tu64 l4_len : 1;\n+\t\tu64 l4_chk : 1;\n+\t\tu64 l4_prt : 1;\n+\t\tu64 l4_mal : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ip6_eext : 2;\n+\t\tu64 ip4_opts : 1;\n+\t\tu64 ip_hop : 1;\n+\t\tu64 ip_mal : 1;\n+\t\tu64 ip_chk : 1;\n+\t} cn61xx;\n+\tstruct cvmx_pip_gbl_ctl_cn61xx cn63xx;\n+\tstruct cvmx_pip_gbl_ctl_cn61xx cn63xxp1;\n+\tstruct cvmx_pip_gbl_ctl_cn61xx cn66xx;\n+\tstruct cvmx_pip_gbl_ctl_cn68xx {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 egrp_dis : 1;\n+\t\tu64 ihmsk_dis : 1;\n+\t\tu64 dsa_grp_tvid : 1;\n+\t\tu64 dsa_grp_scmd : 1;\n+\t\tu64 dsa_grp_sid : 1;\n+\t\tu64 reserved_17_23 : 7;\n+\t\tu64 ignrs : 1;\n+\t\tu64 vs_wqe : 1;\n+\t\tu64 vs_qos : 1;\n+\t\tu64 l2_mal : 1;\n+\t\tu64 tcp_flag : 1;\n+\t\tu64 l4_len : 1;\n+\t\tu64 l4_chk : 1;\n+\t\tu64 l4_prt : 1;\n+\t\tu64 l4_mal : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ip6_eext : 2;\n+\t\tu64 ip4_opts : 1;\n+\t\tu64 ip_hop : 1;\n+\t\tu64 ip_mal : 1;\n+\t\tu64 ip_chk : 1;\n+\t} cn68xx;\n+\tstruct cvmx_pip_gbl_ctl_cn68xxp1 {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 ihmsk_dis : 1;\n+\t\tu64 dsa_grp_tvid : 1;\n+\t\tu64 dsa_grp_scmd : 1;\n+\t\tu64 dsa_grp_sid : 1;\n+\t\tu64 reserved_17_23 : 7;\n+\t\tu64 ignrs : 1;\n+\t\tu64 vs_wqe : 1;\n+\t\tu64 vs_qos : 1;\n+\t\tu64 l2_mal : 1;\n+\t\tu64 tcp_flag : 1;\n+\t\tu64 l4_len : 1;\n+\t\tu64 l4_chk : 1;\n+\t\tu64 l4_prt : 1;\n+\t\tu64 l4_mal : 1;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 ip6_eext : 2;\n+\t\tu64 ip4_opts : 1;\n+\t\tu64 ip_hop : 1;\n+\t\tu64 ip_mal : 1;\n+\t\tu64 ip_chk : 1;\n+\t} cn68xxp1;\n+\tstruct cvmx_pip_gbl_ctl_cn61xx cn70xx;\n+\tstruct cvmx_pip_gbl_ctl_cn61xx cn70xxp1;\n+\tstruct cvmx_pip_gbl_ctl_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_pip_gbl_ctl cvmx_pip_gbl_ctl_t;\n+\n+/**\n+ * cvmx_pip_hg_pri_qos\n+ *\n+ * Notes:\n+ * This register controls accesses to the HG_QOS_TABLE.  To write an entry of\n+ * the table, write PIP_HG_PRI_QOS with PRI=table address, QOS=priority level,\n+ * UP_QOS=1.  To read an entry of the table, write PIP_HG_PRI_QOS with\n+ * PRI=table address, QOS=dont_carepriority level, UP_QOS=0 and then read\n+ * PIP_HG_PRI_QOS.  The table data will be in PIP_HG_PRI_QOS[QOS].\n+ */\n+union cvmx_pip_hg_pri_qos {\n+\tu64 u64;\n+\tstruct cvmx_pip_hg_pri_qos_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 up_qos : 1;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 qos : 3;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 pri : 6;\n+\t} s;\n+\tstruct cvmx_pip_hg_pri_qos_s cn52xx;\n+\tstruct cvmx_pip_hg_pri_qos_s cn52xxp1;\n+\tstruct cvmx_pip_hg_pri_qos_s cn56xx;\n+\tstruct cvmx_pip_hg_pri_qos_s cn61xx;\n+\tstruct cvmx_pip_hg_pri_qos_s cn63xx;\n+\tstruct cvmx_pip_hg_pri_qos_s cn63xxp1;\n+\tstruct cvmx_pip_hg_pri_qos_s cn66xx;\n+\tstruct cvmx_pip_hg_pri_qos_s cn70xx;\n+\tstruct cvmx_pip_hg_pri_qos_s cn70xxp1;\n+\tstruct cvmx_pip_hg_pri_qos_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_hg_pri_qos cvmx_pip_hg_pri_qos_t;\n+\n+/**\n+ * cvmx_pip_int_en\n+ *\n+ * Determines if hardward should raise an interrupt to software\n+ * when an exception event occurs.\n+ */\n+union cvmx_pip_int_en {\n+\tu64 u64;\n+\tstruct cvmx_pip_int_en_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 punyerr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 minerr : 1;\n+\t\tu64 beperr : 1;\n+\t\tu64 feperr : 1;\n+\t\tu64 todoovr : 1;\n+\t\tu64 skprunt : 1;\n+\t\tu64 badtag : 1;\n+\t\tu64 prtnxa : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 crcerr : 1;\n+\t\tu64 pktdrp : 1;\n+\t} s;\n+\tstruct cvmx_pip_int_en_cn30xx {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 beperr : 1;\n+\t\tu64 feperr : 1;\n+\t\tu64 todoovr : 1;\n+\t\tu64 skprunt : 1;\n+\t\tu64 badtag : 1;\n+\t\tu64 prtnxa : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 crcerr : 1;\n+\t\tu64 pktdrp : 1;\n+\t} cn30xx;\n+\tstruct cvmx_pip_int_en_cn30xx cn31xx;\n+\tstruct cvmx_pip_int_en_cn30xx cn38xx;\n+\tstruct cvmx_pip_int_en_cn30xx cn38xxp2;\n+\tstruct cvmx_pip_int_en_cn50xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 lenerr : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 minerr : 1;\n+\t\tu64 beperr : 1;\n+\t\tu64 feperr : 1;\n+\t\tu64 todoovr : 1;\n+\t\tu64 skprunt : 1;\n+\t\tu64 badtag : 1;\n+\t\tu64 prtnxa : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pktdrp : 1;\n+\t} cn50xx;\n+\tstruct cvmx_pip_int_en_cn52xx {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 punyerr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 minerr : 1;\n+\t\tu64 beperr : 1;\n+\t\tu64 feperr : 1;\n+\t\tu64 todoovr : 1;\n+\t\tu64 skprunt : 1;\n+\t\tu64 badtag : 1;\n+\t\tu64 prtnxa : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pktdrp : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pip_int_en_cn52xx cn52xxp1;\n+\tstruct cvmx_pip_int_en_s cn56xx;\n+\tstruct cvmx_pip_int_en_cn56xxp1 {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 lenerr : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 minerr : 1;\n+\t\tu64 beperr : 1;\n+\t\tu64 feperr : 1;\n+\t\tu64 todoovr : 1;\n+\t\tu64 skprunt : 1;\n+\t\tu64 badtag : 1;\n+\t\tu64 prtnxa : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 crcerr : 1;\n+\t\tu64 pktdrp : 1;\n+\t} cn56xxp1;\n+\tstruct cvmx_pip_int_en_cn58xx {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 punyerr : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 beperr : 1;\n+\t\tu64 feperr : 1;\n+\t\tu64 todoovr : 1;\n+\t\tu64 skprunt : 1;\n+\t\tu64 badtag : 1;\n+\t\tu64 prtnxa : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 crcerr : 1;\n+\t\tu64 pktdrp : 1;\n+\t} cn58xx;\n+\tstruct cvmx_pip_int_en_cn30xx cn58xxp1;\n+\tstruct cvmx_pip_int_en_s cn61xx;\n+\tstruct cvmx_pip_int_en_s cn63xx;\n+\tstruct cvmx_pip_int_en_s cn63xxp1;\n+\tstruct cvmx_pip_int_en_s cn66xx;\n+\tstruct cvmx_pip_int_en_s cn68xx;\n+\tstruct cvmx_pip_int_en_s cn68xxp1;\n+\tstruct cvmx_pip_int_en_s cn70xx;\n+\tstruct cvmx_pip_int_en_s cn70xxp1;\n+\tstruct cvmx_pip_int_en_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_int_en cvmx_pip_int_en_t;\n+\n+/**\n+ * cvmx_pip_int_reg\n+ *\n+ * Any exception event that occurs is captured in the PIP_INT_REG.\n+ * PIP_INT_REG will set the exception bit regardless of the value\n+ * of PIP_INT_EN.  PIP_INT_EN only controls if an interrupt is\n+ * raised to software.\n+ */\n+union cvmx_pip_int_reg {\n+\tu64 u64;\n+\tstruct cvmx_pip_int_reg_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 punyerr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 minerr : 1;\n+\t\tu64 beperr : 1;\n+\t\tu64 feperr : 1;\n+\t\tu64 todoovr : 1;\n+\t\tu64 skprunt : 1;\n+\t\tu64 badtag : 1;\n+\t\tu64 prtnxa : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 crcerr : 1;\n+\t\tu64 pktdrp : 1;\n+\t} s;\n+\tstruct cvmx_pip_int_reg_cn30xx {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 beperr : 1;\n+\t\tu64 feperr : 1;\n+\t\tu64 todoovr : 1;\n+\t\tu64 skprunt : 1;\n+\t\tu64 badtag : 1;\n+\t\tu64 prtnxa : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 crcerr : 1;\n+\t\tu64 pktdrp : 1;\n+\t} cn30xx;\n+\tstruct cvmx_pip_int_reg_cn30xx cn31xx;\n+\tstruct cvmx_pip_int_reg_cn30xx cn38xx;\n+\tstruct cvmx_pip_int_reg_cn30xx cn38xxp2;\n+\tstruct cvmx_pip_int_reg_cn50xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 lenerr : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 minerr : 1;\n+\t\tu64 beperr : 1;\n+\t\tu64 feperr : 1;\n+\t\tu64 todoovr : 1;\n+\t\tu64 skprunt : 1;\n+\t\tu64 badtag : 1;\n+\t\tu64 prtnxa : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pktdrp : 1;\n+\t} cn50xx;\n+\tstruct cvmx_pip_int_reg_cn52xx {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 punyerr : 1;\n+\t\tu64 lenerr : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 minerr : 1;\n+\t\tu64 beperr : 1;\n+\t\tu64 feperr : 1;\n+\t\tu64 todoovr : 1;\n+\t\tu64 skprunt : 1;\n+\t\tu64 badtag : 1;\n+\t\tu64 prtnxa : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 pktdrp : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pip_int_reg_cn52xx cn52xxp1;\n+\tstruct cvmx_pip_int_reg_s cn56xx;\n+\tstruct cvmx_pip_int_reg_cn56xxp1 {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 lenerr : 1;\n+\t\tu64 maxerr : 1;\n+\t\tu64 minerr : 1;\n+\t\tu64 beperr : 1;\n+\t\tu64 feperr : 1;\n+\t\tu64 todoovr : 1;\n+\t\tu64 skprunt : 1;\n+\t\tu64 badtag : 1;\n+\t\tu64 prtnxa : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 crcerr : 1;\n+\t\tu64 pktdrp : 1;\n+\t} cn56xxp1;\n+\tstruct cvmx_pip_int_reg_cn58xx {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 punyerr : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 beperr : 1;\n+\t\tu64 feperr : 1;\n+\t\tu64 todoovr : 1;\n+\t\tu64 skprunt : 1;\n+\t\tu64 badtag : 1;\n+\t\tu64 prtnxa : 1;\n+\t\tu64 bckprs : 1;\n+\t\tu64 crcerr : 1;\n+\t\tu64 pktdrp : 1;\n+\t} cn58xx;\n+\tstruct cvmx_pip_int_reg_cn30xx cn58xxp1;\n+\tstruct cvmx_pip_int_reg_s cn61xx;\n+\tstruct cvmx_pip_int_reg_s cn63xx;\n+\tstruct cvmx_pip_int_reg_s cn63xxp1;\n+\tstruct cvmx_pip_int_reg_s cn66xx;\n+\tstruct cvmx_pip_int_reg_s cn68xx;\n+\tstruct cvmx_pip_int_reg_s cn68xxp1;\n+\tstruct cvmx_pip_int_reg_s cn70xx;\n+\tstruct cvmx_pip_int_reg_s cn70xxp1;\n+\tstruct cvmx_pip_int_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_int_reg cvmx_pip_int_reg_t;\n+\n+/**\n+ * cvmx_pip_ip_offset\n+ *\n+ * An 8-byte offset to find the start of the IP header in the data portion of IP workQ entires\n+ *\n+ */\n+union cvmx_pip_ip_offset {\n+\tu64 u64;\n+\tstruct cvmx_pip_ip_offset_s {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 offset : 3;\n+\t} s;\n+\tstruct cvmx_pip_ip_offset_s cn30xx;\n+\tstruct cvmx_pip_ip_offset_s cn31xx;\n+\tstruct cvmx_pip_ip_offset_s cn38xx;\n+\tstruct cvmx_pip_ip_offset_s cn38xxp2;\n+\tstruct cvmx_pip_ip_offset_s cn50xx;\n+\tstruct cvmx_pip_ip_offset_s cn52xx;\n+\tstruct cvmx_pip_ip_offset_s cn52xxp1;\n+\tstruct cvmx_pip_ip_offset_s cn56xx;\n+\tstruct cvmx_pip_ip_offset_s cn56xxp1;\n+\tstruct cvmx_pip_ip_offset_s cn58xx;\n+\tstruct cvmx_pip_ip_offset_s cn58xxp1;\n+\tstruct cvmx_pip_ip_offset_s cn61xx;\n+\tstruct cvmx_pip_ip_offset_s cn63xx;\n+\tstruct cvmx_pip_ip_offset_s cn63xxp1;\n+\tstruct cvmx_pip_ip_offset_s cn66xx;\n+\tstruct cvmx_pip_ip_offset_s cn68xx;\n+\tstruct cvmx_pip_ip_offset_s cn68xxp1;\n+\tstruct cvmx_pip_ip_offset_s cn70xx;\n+\tstruct cvmx_pip_ip_offset_s cn70xxp1;\n+\tstruct cvmx_pip_ip_offset_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_ip_offset cvmx_pip_ip_offset_t;\n+\n+/**\n+ * cvmx_pip_pri_tbl#\n+ *\n+ * Notes:\n+ * The priority level from HiGig header is as follows\n+ *\n+ * HiGig/HiGig+ PRI = [1'b0, CNG[1:0], COS[2:0]]\n+ * HiGig2       PRI = [DP[1:0], TC[3:0]]\n+ *\n+ * DSA          PRI = WORD0[15:13]\n+ *\n+ * VLAN         PRI = VLAN[15:13]\n+ *\n+ * DIFFSERV         = IP.TOS/CLASS<7:2>\n+ */\n+union cvmx_pip_pri_tblx {\n+\tu64 u64;\n+\tstruct cvmx_pip_pri_tblx_s {\n+\t\tu64 diff2_padd : 8;\n+\t\tu64 hg2_padd : 8;\n+\t\tu64 vlan2_padd : 8;\n+\t\tu64 reserved_38_39 : 2;\n+\t\tu64 diff2_bpid : 6;\n+\t\tu64 reserved_30_31 : 2;\n+\t\tu64 hg2_bpid : 6;\n+\t\tu64 reserved_22_23 : 2;\n+\t\tu64 vlan2_bpid : 6;\n+\t\tu64 reserved_11_15 : 5;\n+\t\tu64 diff2_qos : 3;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 hg2_qos : 3;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 vlan2_qos : 3;\n+\t} s;\n+\tstruct cvmx_pip_pri_tblx_s cn68xx;\n+\tstruct cvmx_pip_pri_tblx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_pri_tblx cvmx_pip_pri_tblx_t;\n+\n+/**\n+ * cvmx_pip_prt_cfg#\n+ *\n+ * PIP_PRT_CFGX = Per port config information\n+ *\n+ */\n+union cvmx_pip_prt_cfgx {\n+\tu64 u64;\n+\tstruct cvmx_pip_prt_cfgx_s {\n+\t\tu64 reserved_55_63 : 9;\n+\t\tu64 ih_pri : 1;\n+\t\tu64 len_chk_sel : 1;\n+\t\tu64 pad_len : 1;\n+\t\tu64 vlan_len : 1;\n+\t\tu64 lenerr_en : 1;\n+\t\tu64 maxerr_en : 1;\n+\t\tu64 minerr_en : 1;\n+\t\tu64 grp_wat_47 : 4;\n+\t\tu64 qos_wat_47 : 4;\n+\t\tu64 reserved_37_39 : 3;\n+\t\tu64 rawdrp : 1;\n+\t\tu64 tag_inc : 2;\n+\t\tu64 dyn_rs : 1;\n+\t\tu64 inst_hdr : 1;\n+\t\tu64 grp_wat : 4;\n+\t\tu64 hg_qos : 1;\n+\t\tu64 qos : 3;\n+\t\tu64 qos_wat : 4;\n+\t\tu64 qos_vsel : 1;\n+\t\tu64 qos_vod : 1;\n+\t\tu64 qos_diff : 1;\n+\t\tu64 qos_vlan : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 crc_en : 1;\n+\t\tu64 higig_en : 1;\n+\t\tu64 dsa_en : 1;\n+\t\tcvmx_pip_port_parse_mode_t mode : 2;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 skip : 7;\n+\t} s;\n+\tstruct cvmx_pip_prt_cfgx_cn30xx {\n+\t\tu64 reserved_37_63 : 27;\n+\t\tu64 rawdrp : 1;\n+\t\tu64 tag_inc : 2;\n+\t\tu64 dyn_rs : 1;\n+\t\tu64 inst_hdr : 1;\n+\t\tu64 grp_wat : 4;\n+\t\tu64 reserved_27_27 : 1;\n+\t\tu64 qos : 3;\n+\t\tu64 qos_wat : 4;\n+\t\tu64 reserved_18_19 : 2;\n+\t\tu64 qos_diff : 1;\n+\t\tu64 qos_vlan : 1;\n+\t\tu64 reserved_10_15 : 6;\n+\t\tcvmx_pip_port_parse_mode_t mode : 2;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 skip : 7;\n+\t} cn30xx;\n+\tstruct cvmx_pip_prt_cfgx_cn30xx cn31xx;\n+\tstruct cvmx_pip_prt_cfgx_cn38xx {\n+\t\tu64 reserved_37_63 : 27;\n+\t\tu64 rawdrp : 1;\n+\t\tu64 tag_inc : 2;\n+\t\tu64 dyn_rs : 1;\n+\t\tu64 inst_hdr : 1;\n+\t\tu64 grp_wat : 4;\n+\t\tu64 reserved_27_27 : 1;\n+\t\tu64 qos : 3;\n+\t\tu64 qos_wat : 4;\n+\t\tu64 reserved_18_19 : 2;\n+\t\tu64 qos_diff : 1;\n+\t\tu64 qos_vlan : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 crc_en : 1;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tcvmx_pip_port_parse_mode_t mode : 2;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 skip : 7;\n+\t} cn38xx;\n+\tstruct cvmx_pip_prt_cfgx_cn38xx cn38xxp2;\n+\tstruct cvmx_pip_prt_cfgx_cn50xx {\n+\t\tu64 reserved_53_63 : 11;\n+\t\tu64 pad_len : 1;\n+\t\tu64 vlan_len : 1;\n+\t\tu64 lenerr_en : 1;\n+\t\tu64 maxerr_en : 1;\n+\t\tu64 minerr_en : 1;\n+\t\tu64 grp_wat_47 : 4;\n+\t\tu64 qos_wat_47 : 4;\n+\t\tu64 reserved_37_39 : 3;\n+\t\tu64 rawdrp : 1;\n+\t\tu64 tag_inc : 2;\n+\t\tu64 dyn_rs : 1;\n+\t\tu64 inst_hdr : 1;\n+\t\tu64 grp_wat : 4;\n+\t\tu64 reserved_27_27 : 1;\n+\t\tu64 qos : 3;\n+\t\tu64 qos_wat : 4;\n+\t\tu64 reserved_19_19 : 1;\n+\t\tu64 qos_vod : 1;\n+\t\tu64 qos_diff : 1;\n+\t\tu64 qos_vlan : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 crc_en : 1;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tcvmx_pip_port_parse_mode_t mode : 2;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 skip : 7;\n+\t} cn50xx;\n+\tstruct cvmx_pip_prt_cfgx_cn52xx {\n+\t\tu64 reserved_53_63 : 11;\n+\t\tu64 pad_len : 1;\n+\t\tu64 vlan_len : 1;\n+\t\tu64 lenerr_en : 1;\n+\t\tu64 maxerr_en : 1;\n+\t\tu64 minerr_en : 1;\n+\t\tu64 grp_wat_47 : 4;\n+\t\tu64 qos_wat_47 : 4;\n+\t\tu64 reserved_37_39 : 3;\n+\t\tu64 rawdrp : 1;\n+\t\tu64 tag_inc : 2;\n+\t\tu64 dyn_rs : 1;\n+\t\tu64 inst_hdr : 1;\n+\t\tu64 grp_wat : 4;\n+\t\tu64 hg_qos : 1;\n+\t\tu64 qos : 3;\n+\t\tu64 qos_wat : 4;\n+\t\tu64 qos_vsel : 1;\n+\t\tu64 qos_vod : 1;\n+\t\tu64 qos_diff : 1;\n+\t\tu64 qos_vlan : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 crc_en : 1;\n+\t\tu64 higig_en : 1;\n+\t\tu64 dsa_en : 1;\n+\t\tcvmx_pip_port_parse_mode_t mode : 2;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 skip : 7;\n+\t} cn52xx;\n+\tstruct cvmx_pip_prt_cfgx_cn52xx cn52xxp1;\n+\tstruct cvmx_pip_prt_cfgx_cn52xx cn56xx;\n+\tstruct cvmx_pip_prt_cfgx_cn50xx cn56xxp1;\n+\tstruct cvmx_pip_prt_cfgx_cn58xx {\n+\t\tu64 reserved_37_63 : 27;\n+\t\tu64 rawdrp : 1;\n+\t\tu64 tag_inc : 2;\n+\t\tu64 dyn_rs : 1;\n+\t\tu64 inst_hdr : 1;\n+\t\tu64 grp_wat : 4;\n+\t\tu64 reserved_27_27 : 1;\n+\t\tu64 qos : 3;\n+\t\tu64 qos_wat : 4;\n+\t\tu64 reserved_19_19 : 1;\n+\t\tu64 qos_vod : 1;\n+\t\tu64 qos_diff : 1;\n+\t\tu64 qos_vlan : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 crc_en : 1;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tcvmx_pip_port_parse_mode_t mode : 2;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 skip : 7;\n+\t} cn58xx;\n+\tstruct cvmx_pip_prt_cfgx_cn58xx cn58xxp1;\n+\tstruct cvmx_pip_prt_cfgx_cn52xx cn61xx;\n+\tstruct cvmx_pip_prt_cfgx_cn52xx cn63xx;\n+\tstruct cvmx_pip_prt_cfgx_cn52xx cn63xxp1;\n+\tstruct cvmx_pip_prt_cfgx_cn52xx cn66xx;\n+\tstruct cvmx_pip_prt_cfgx_cn68xx {\n+\t\tu64 reserved_55_63 : 9;\n+\t\tu64 ih_pri : 1;\n+\t\tu64 len_chk_sel : 1;\n+\t\tu64 pad_len : 1;\n+\t\tu64 vlan_len : 1;\n+\t\tu64 lenerr_en : 1;\n+\t\tu64 maxerr_en : 1;\n+\t\tu64 minerr_en : 1;\n+\t\tu64 grp_wat_47 : 4;\n+\t\tu64 qos_wat_47 : 4;\n+\t\tu64 reserved_37_39 : 3;\n+\t\tu64 rawdrp : 1;\n+\t\tu64 tag_inc : 2;\n+\t\tu64 dyn_rs : 1;\n+\t\tu64 inst_hdr : 1;\n+\t\tu64 grp_wat : 4;\n+\t\tu64 hg_qos : 1;\n+\t\tu64 qos : 3;\n+\t\tu64 qos_wat : 4;\n+\t\tu64 reserved_19_19 : 1;\n+\t\tu64 qos_vod : 1;\n+\t\tu64 qos_diff : 1;\n+\t\tu64 qos_vlan : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 crc_en : 1;\n+\t\tu64 higig_en : 1;\n+\t\tu64 dsa_en : 1;\n+\t\tcvmx_pip_port_parse_mode_t mode : 2;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 skip : 7;\n+\t} cn68xx;\n+\tstruct cvmx_pip_prt_cfgx_cn68xx cn68xxp1;\n+\tstruct cvmx_pip_prt_cfgx_cn52xx cn70xx;\n+\tstruct cvmx_pip_prt_cfgx_cn52xx cn70xxp1;\n+\tstruct cvmx_pip_prt_cfgx_cn52xx cnf71xx;\n+};\n+\n+typedef union cvmx_pip_prt_cfgx cvmx_pip_prt_cfgx_t;\n+\n+/**\n+ * cvmx_pip_prt_cfgb#\n+ *\n+ * Notes:\n+ * PIP_PRT_CFGB* does not exist prior to pass 1.2.\n+ *\n+ */\n+union cvmx_pip_prt_cfgbx {\n+\tu64 u64;\n+\tstruct cvmx_pip_prt_cfgbx_s {\n+\t\tu64 reserved_39_63 : 25;\n+\t\tu64 alt_skp_sel : 2;\n+\t\tu64 alt_skp_en : 1;\n+\t\tu64 reserved_35_35 : 1;\n+\t\tu64 bsel_num : 2;\n+\t\tu64 bsel_en : 1;\n+\t\tu64 reserved_24_31 : 8;\n+\t\tu64 base : 8;\n+\t\tu64 reserved_6_15 : 10;\n+\t\tu64 bpid : 6;\n+\t} s;\n+\tstruct cvmx_pip_prt_cfgbx_cn61xx {\n+\t\tu64 reserved_39_63 : 25;\n+\t\tu64 alt_skp_sel : 2;\n+\t\tu64 alt_skp_en : 1;\n+\t\tu64 reserved_35_35 : 1;\n+\t\tu64 bsel_num : 2;\n+\t\tu64 bsel_en : 1;\n+\t\tu64 reserved_0_31 : 32;\n+\t} cn61xx;\n+\tstruct cvmx_pip_prt_cfgbx_cn66xx {\n+\t\tu64 reserved_39_63 : 25;\n+\t\tu64 alt_skp_sel : 2;\n+\t\tu64 alt_skp_en : 1;\n+\t\tu64 reserved_0_35 : 36;\n+\t} cn66xx;\n+\tstruct cvmx_pip_prt_cfgbx_s cn68xx;\n+\tstruct cvmx_pip_prt_cfgbx_cn68xxp1 {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 base : 8;\n+\t\tu64 reserved_6_15 : 10;\n+\t\tu64 bpid : 6;\n+\t} cn68xxp1;\n+\tstruct cvmx_pip_prt_cfgbx_cn61xx cn70xx;\n+\tstruct cvmx_pip_prt_cfgbx_cn61xx cn70xxp1;\n+\tstruct cvmx_pip_prt_cfgbx_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_pip_prt_cfgbx cvmx_pip_prt_cfgbx_t;\n+\n+/**\n+ * cvmx_pip_prt_tag#\n+ *\n+ * PIP_PRT_TAGX = Per port config information\n+ *\n+ */\n+union cvmx_pip_prt_tagx {\n+\tu64 u64;\n+\tstruct cvmx_pip_prt_tagx_s {\n+\t\tu64 reserved_54_63 : 10;\n+\t\tu64 portadd_en : 1;\n+\t\tu64 inc_hwchk : 1;\n+\t\tu64 reserved_50_51 : 2;\n+\t\tu64 grptagbase_msb : 2;\n+\t\tu64 reserved_46_47 : 2;\n+\t\tu64 grptagmask_msb : 2;\n+\t\tu64 reserved_42_43 : 2;\n+\t\tu64 grp_msb : 2;\n+\t\tu64 grptagbase : 4;\n+\t\tu64 grptagmask : 4;\n+\t\tu64 grptag : 1;\n+\t\tu64 grptag_mskip : 1;\n+\t\tu64 tag_mode : 2;\n+\t\tu64 inc_vs : 2;\n+\t\tu64 inc_vlan : 1;\n+\t\tu64 inc_prt_flag : 1;\n+\t\tu64 ip6_dprt_flag : 1;\n+\t\tu64 ip4_dprt_flag : 1;\n+\t\tu64 ip6_sprt_flag : 1;\n+\t\tu64 ip4_sprt_flag : 1;\n+\t\tu64 ip6_nxth_flag : 1;\n+\t\tu64 ip4_pctl_flag : 1;\n+\t\tu64 ip6_dst_flag : 1;\n+\t\tu64 ip4_dst_flag : 1;\n+\t\tu64 ip6_src_flag : 1;\n+\t\tu64 ip4_src_flag : 1;\n+\t\tcvmx_pow_tag_type_t tcp6_tag_type : 2;\n+\t\tcvmx_pow_tag_type_t tcp4_tag_type : 2;\n+\t\tcvmx_pow_tag_type_t ip6_tag_type : 2;\n+\t\tcvmx_pow_tag_type_t ip4_tag_type : 2;\n+\t\tcvmx_pow_tag_type_t non_tag_type : 2;\n+\t\tu64 grp : 4;\n+\t} s;\n+\tstruct cvmx_pip_prt_tagx_cn30xx {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 grptagbase : 4;\n+\t\tu64 grptagmask : 4;\n+\t\tu64 grptag : 1;\n+\t\tu64 reserved_30_30 : 1;\n+\t\tu64 tag_mode : 2;\n+\t\tu64 inc_vs : 2;\n+\t\tu64 inc_vlan : 1;\n+\t\tu64 inc_prt_flag : 1;\n+\t\tu64 ip6_dprt_flag : 1;\n+\t\tu64 ip4_dprt_flag : 1;\n+\t\tu64 ip6_sprt_flag : 1;\n+\t\tu64 ip4_sprt_flag : 1;\n+\t\tu64 ip6_nxth_flag : 1;\n+\t\tu64 ip4_pctl_flag : 1;\n+\t\tu64 ip6_dst_flag : 1;\n+\t\tu64 ip4_dst_flag : 1;\n+\t\tu64 ip6_src_flag : 1;\n+\t\tu64 ip4_src_flag : 1;\n+\t\tcvmx_pow_tag_type_t tcp6_tag_type : 2;\n+\t\tcvmx_pow_tag_type_t tcp4_tag_type : 2;\n+\t\tcvmx_pow_tag_type_t ip6_tag_type : 2;\n+\t\tcvmx_pow_tag_type_t ip4_tag_type : 2;\n+\t\tcvmx_pow_tag_type_t non_tag_type : 2;\n+\t\tu64 grp : 4;\n+\t} cn30xx;\n+\tstruct cvmx_pip_prt_tagx_cn30xx cn31xx;\n+\tstruct cvmx_pip_prt_tagx_cn30xx cn38xx;\n+\tstruct cvmx_pip_prt_tagx_cn30xx cn38xxp2;\n+\tstruct cvmx_pip_prt_tagx_cn50xx {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 grptagbase : 4;\n+\t\tu64 grptagmask : 4;\n+\t\tu64 grptag : 1;\n+\t\tu64 grptag_mskip : 1;\n+\t\tu64 tag_mode : 2;\n+\t\tu64 inc_vs : 2;\n+\t\tu64 inc_vlan : 1;\n+\t\tu64 inc_prt_flag : 1;\n+\t\tu64 ip6_dprt_flag : 1;\n+\t\tu64 ip4_dprt_flag : 1;\n+\t\tu64 ip6_sprt_flag : 1;\n+\t\tu64 ip4_sprt_flag : 1;\n+\t\tu64 ip6_nxth_flag : 1;\n+\t\tu64 ip4_pctl_flag : 1;\n+\t\tu64 ip6_dst_flag : 1;\n+\t\tu64 ip4_dst_flag : 1;\n+\t\tu64 ip6_src_flag : 1;\n+\t\tu64 ip4_src_flag : 1;\n+\t\tcvmx_pow_tag_type_t tcp6_tag_type : 2;\n+\t\tcvmx_pow_tag_type_t tcp4_tag_type : 2;\n+\t\tcvmx_pow_tag_type_t ip6_tag_type : 2;\n+\t\tcvmx_pow_tag_type_t ip4_tag_type : 2;\n+\t\tcvmx_pow_tag_type_t non_tag_type : 2;\n+\t\tu64 grp : 4;\n+\t} cn50xx;\n+\tstruct cvmx_pip_prt_tagx_cn50xx cn52xx;\n+\tstruct cvmx_pip_prt_tagx_cn50xx cn52xxp1;\n+\tstruct cvmx_pip_prt_tagx_cn50xx cn56xx;\n+\tstruct cvmx_pip_prt_tagx_cn50xx cn56xxp1;\n+\tstruct cvmx_pip_prt_tagx_cn30xx cn58xx;\n+\tstruct cvmx_pip_prt_tagx_cn30xx cn58xxp1;\n+\tstruct cvmx_pip_prt_tagx_cn50xx cn61xx;\n+\tstruct cvmx_pip_prt_tagx_cn50xx cn63xx;\n+\tstruct cvmx_pip_prt_tagx_cn50xx cn63xxp1;\n+\tstruct cvmx_pip_prt_tagx_cn50xx cn66xx;\n+\tstruct cvmx_pip_prt_tagx_s cn68xx;\n+\tstruct cvmx_pip_prt_tagx_s cn68xxp1;\n+\tstruct cvmx_pip_prt_tagx_cn50xx cn70xx;\n+\tstruct cvmx_pip_prt_tagx_cn50xx cn70xxp1;\n+\tstruct cvmx_pip_prt_tagx_cn50xx cnf71xx;\n+};\n+\n+typedef union cvmx_pip_prt_tagx cvmx_pip_prt_tagx_t;\n+\n+/**\n+ * cvmx_pip_qos_diff#\n+ *\n+ * PIP_QOS_DIFFX = QOS Diffserv Tables\n+ *\n+ */\n+union cvmx_pip_qos_diffx {\n+\tu64 u64;\n+\tstruct cvmx_pip_qos_diffx_s {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 qos : 3;\n+\t} s;\n+\tstruct cvmx_pip_qos_diffx_s cn30xx;\n+\tstruct cvmx_pip_qos_diffx_s cn31xx;\n+\tstruct cvmx_pip_qos_diffx_s cn38xx;\n+\tstruct cvmx_pip_qos_diffx_s cn38xxp2;\n+\tstruct cvmx_pip_qos_diffx_s cn50xx;\n+\tstruct cvmx_pip_qos_diffx_s cn52xx;\n+\tstruct cvmx_pip_qos_diffx_s cn52xxp1;\n+\tstruct cvmx_pip_qos_diffx_s cn56xx;\n+\tstruct cvmx_pip_qos_diffx_s cn56xxp1;\n+\tstruct cvmx_pip_qos_diffx_s cn58xx;\n+\tstruct cvmx_pip_qos_diffx_s cn58xxp1;\n+\tstruct cvmx_pip_qos_diffx_s cn61xx;\n+\tstruct cvmx_pip_qos_diffx_s cn63xx;\n+\tstruct cvmx_pip_qos_diffx_s cn63xxp1;\n+\tstruct cvmx_pip_qos_diffx_s cn66xx;\n+\tstruct cvmx_pip_qos_diffx_s cn70xx;\n+\tstruct cvmx_pip_qos_diffx_s cn70xxp1;\n+\tstruct cvmx_pip_qos_diffx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_qos_diffx cvmx_pip_qos_diffx_t;\n+\n+/**\n+ * cvmx_pip_qos_vlan#\n+ *\n+ * If the PIP indentifies a packet is DSA/VLAN tagged, then the QOS\n+ * can be set based on the DSA/VLAN user priority.  These eight register\n+ * comprise the QOS values for all DSA/VLAN user priority values.\n+ */\n+union cvmx_pip_qos_vlanx {\n+\tu64 u64;\n+\tstruct cvmx_pip_qos_vlanx_s {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 qos1 : 3;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 qos : 3;\n+\t} s;\n+\tstruct cvmx_pip_qos_vlanx_cn30xx {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 qos : 3;\n+\t} cn30xx;\n+\tstruct cvmx_pip_qos_vlanx_cn30xx cn31xx;\n+\tstruct cvmx_pip_qos_vlanx_cn30xx cn38xx;\n+\tstruct cvmx_pip_qos_vlanx_cn30xx cn38xxp2;\n+\tstruct cvmx_pip_qos_vlanx_cn30xx cn50xx;\n+\tstruct cvmx_pip_qos_vlanx_s cn52xx;\n+\tstruct cvmx_pip_qos_vlanx_s cn52xxp1;\n+\tstruct cvmx_pip_qos_vlanx_s cn56xx;\n+\tstruct cvmx_pip_qos_vlanx_cn30xx cn56xxp1;\n+\tstruct cvmx_pip_qos_vlanx_cn30xx cn58xx;\n+\tstruct cvmx_pip_qos_vlanx_cn30xx cn58xxp1;\n+\tstruct cvmx_pip_qos_vlanx_s cn61xx;\n+\tstruct cvmx_pip_qos_vlanx_s cn63xx;\n+\tstruct cvmx_pip_qos_vlanx_s cn63xxp1;\n+\tstruct cvmx_pip_qos_vlanx_s cn66xx;\n+\tstruct cvmx_pip_qos_vlanx_s cn70xx;\n+\tstruct cvmx_pip_qos_vlanx_s cn70xxp1;\n+\tstruct cvmx_pip_qos_vlanx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_qos_vlanx cvmx_pip_qos_vlanx_t;\n+\n+/**\n+ * cvmx_pip_qos_watch#\n+ *\n+ * Sets up the Configuration CSRs for the four QOS Watchers.\n+ * Each Watcher can be set to look for a specific protocol,\n+ * TCP/UDP destination port, or Ethertype to override the\n+ * default QOS value.\n+ */\n+union cvmx_pip_qos_watchx {\n+\tu64 u64;\n+\tstruct cvmx_pip_qos_watchx_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 mask : 16;\n+\t\tu64 reserved_30_31 : 2;\n+\t\tu64 grp : 6;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 qos : 3;\n+\t\tu64 reserved_16_19 : 4;\n+\t\tu64 match_value : 16;\n+\t} s;\n+\tstruct cvmx_pip_qos_watchx_cn30xx {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 mask : 16;\n+\t\tu64 reserved_28_31 : 4;\n+\t\tu64 grp : 4;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 qos : 3;\n+\t\tu64 reserved_18_19 : 2;\n+\n+\t\tcvmx_pip_qos_watch_types match_type : 2;\n+\t\tu64 match_value : 16;\n+\t} cn30xx;\n+\tstruct cvmx_pip_qos_watchx_cn30xx cn31xx;\n+\tstruct cvmx_pip_qos_watchx_cn30xx cn38xx;\n+\tstruct cvmx_pip_qos_watchx_cn30xx cn38xxp2;\n+\tstruct cvmx_pip_qos_watchx_cn50xx {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 mask : 16;\n+\t\tu64 reserved_28_31 : 4;\n+\t\tu64 grp : 4;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 qos : 3;\n+\t\tu64 reserved_19_19 : 1;\n+\n+\t\tcvmx_pip_qos_watch_types match_type : 3;\n+\t\tu64 match_value : 16;\n+\t} cn50xx;\n+\tstruct cvmx_pip_qos_watchx_cn50xx cn52xx;\n+\tstruct cvmx_pip_qos_watchx_cn50xx cn52xxp1;\n+\tstruct cvmx_pip_qos_watchx_cn50xx cn56xx;\n+\tstruct cvmx_pip_qos_watchx_cn50xx cn56xxp1;\n+\tstruct cvmx_pip_qos_watchx_cn30xx cn58xx;\n+\tstruct cvmx_pip_qos_watchx_cn30xx cn58xxp1;\n+\tstruct cvmx_pip_qos_watchx_cn50xx cn61xx;\n+\tstruct cvmx_pip_qos_watchx_cn50xx cn63xx;\n+\tstruct cvmx_pip_qos_watchx_cn50xx cn63xxp1;\n+\tstruct cvmx_pip_qos_watchx_cn50xx cn66xx;\n+\tstruct cvmx_pip_qos_watchx_cn68xx {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 mask : 16;\n+\t\tu64 reserved_30_31 : 2;\n+\t\tu64 grp : 6;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 qos : 3;\n+\t\tu64 reserved_19_19 : 1;\n+\n+\t\tcvmx_pip_qos_watch_types match_type : 3;\n+\t\tu64 match_value : 16;\n+\t} cn68xx;\n+\tstruct cvmx_pip_qos_watchx_cn68xx cn68xxp1;\n+\tstruct cvmx_pip_qos_watchx_cn70xx {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 mask : 16;\n+\t\tu64 reserved_28_31 : 4;\n+\t\tu64 grp : 4;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 qos : 3;\n+\t\tu64 reserved_19_19 : 1;\n+\t\tu64 typ : 3;\n+\t\tu64 match_value : 16;\n+\t} cn70xx;\n+\tstruct cvmx_pip_qos_watchx_cn70xx cn70xxp1;\n+\tstruct cvmx_pip_qos_watchx_cn50xx cnf71xx;\n+};\n+\n+typedef union cvmx_pip_qos_watchx cvmx_pip_qos_watchx_t;\n+\n+/**\n+ * cvmx_pip_raw_word\n+ *\n+ * The RAW Word2 to be inserted into the workQ entry of RAWFULL packets.\n+ *\n+ */\n+union cvmx_pip_raw_word {\n+\tu64 u64;\n+\tstruct cvmx_pip_raw_word_s {\n+\t\tu64 reserved_56_63 : 8;\n+\t\tu64 word : 56;\n+\t} s;\n+\tstruct cvmx_pip_raw_word_s cn30xx;\n+\tstruct cvmx_pip_raw_word_s cn31xx;\n+\tstruct cvmx_pip_raw_word_s cn38xx;\n+\tstruct cvmx_pip_raw_word_s cn38xxp2;\n+\tstruct cvmx_pip_raw_word_s cn50xx;\n+\tstruct cvmx_pip_raw_word_s cn52xx;\n+\tstruct cvmx_pip_raw_word_s cn52xxp1;\n+\tstruct cvmx_pip_raw_word_s cn56xx;\n+\tstruct cvmx_pip_raw_word_s cn56xxp1;\n+\tstruct cvmx_pip_raw_word_s cn58xx;\n+\tstruct cvmx_pip_raw_word_s cn58xxp1;\n+\tstruct cvmx_pip_raw_word_s cn61xx;\n+\tstruct cvmx_pip_raw_word_s cn63xx;\n+\tstruct cvmx_pip_raw_word_s cn63xxp1;\n+\tstruct cvmx_pip_raw_word_s cn66xx;\n+\tstruct cvmx_pip_raw_word_s cn68xx;\n+\tstruct cvmx_pip_raw_word_s cn68xxp1;\n+\tstruct cvmx_pip_raw_word_s cn70xx;\n+\tstruct cvmx_pip_raw_word_s cn70xxp1;\n+\tstruct cvmx_pip_raw_word_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_raw_word cvmx_pip_raw_word_t;\n+\n+/**\n+ * cvmx_pip_sft_rst\n+ *\n+ * When written to a '1', resets the pip block\n+ *\n+ */\n+union cvmx_pip_sft_rst {\n+\tu64 u64;\n+\tstruct cvmx_pip_sft_rst_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 rst : 1;\n+\t} s;\n+\tstruct cvmx_pip_sft_rst_s cn30xx;\n+\tstruct cvmx_pip_sft_rst_s cn31xx;\n+\tstruct cvmx_pip_sft_rst_s cn38xx;\n+\tstruct cvmx_pip_sft_rst_s cn50xx;\n+\tstruct cvmx_pip_sft_rst_s cn52xx;\n+\tstruct cvmx_pip_sft_rst_s cn52xxp1;\n+\tstruct cvmx_pip_sft_rst_s cn56xx;\n+\tstruct cvmx_pip_sft_rst_s cn56xxp1;\n+\tstruct cvmx_pip_sft_rst_s cn58xx;\n+\tstruct cvmx_pip_sft_rst_s cn58xxp1;\n+\tstruct cvmx_pip_sft_rst_s cn61xx;\n+\tstruct cvmx_pip_sft_rst_s cn63xx;\n+\tstruct cvmx_pip_sft_rst_s cn63xxp1;\n+\tstruct cvmx_pip_sft_rst_s cn66xx;\n+\tstruct cvmx_pip_sft_rst_s cn68xx;\n+\tstruct cvmx_pip_sft_rst_s cn68xxp1;\n+\tstruct cvmx_pip_sft_rst_s cn70xx;\n+\tstruct cvmx_pip_sft_rst_s cn70xxp1;\n+\tstruct cvmx_pip_sft_rst_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_sft_rst cvmx_pip_sft_rst_t;\n+\n+/**\n+ * cvmx_pip_stat0_#\n+ *\n+ * PIP Statistics Counters\n+ *\n+ * Note: special stat counter behavior\n+ *\n+ * 1) Read and write operations must arbitrate for the statistics resources\n+ *     along with the packet engines which are incrementing the counters.\n+ *     In order to not drop packet information, the packet HW is always a\n+ *     higher priority and the CSR requests will only be satisified when\n+ *     there are idle cycles.  This can potentially cause long delays if the\n+ *     system becomes full.\n+ *\n+ * 2) stat counters can be cleared in two ways.  If PIP_STAT_CTL[RDCLR] is\n+ *     set, then all read accesses will clear the register.  In addition,\n+ *     any write to a stats register will also reset the register to zero.\n+ *     Please note that the clearing operations must obey rule \\#1 above.\n+ *\n+ * 3) all counters are wrapping - software must ensure they are read periodically\n+ *\n+ * 4) The counters accumulate statistics for packets that are sent to PKI.  If\n+ *    PTP_MODE is enabled, the 8B timestamp is prepended to the packet.  This\n+ *    additional 8B of data is captured in the octet counts.\n+ *\n+ * 5) X represents either the packet's port-kind or backpressure ID as\n+ *    determined by PIP_STAT_CTL[MODE]\n+ * PIP_STAT0_X = PIP_STAT_DRP_PKTS / PIP_STAT_DRP_OCTS\n+ */\n+union cvmx_pip_stat0_x {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat0_x_s {\n+\t\tu64 drp_pkts : 32;\n+\t\tu64 drp_octs : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat0_x_s cn68xx;\n+\tstruct cvmx_pip_stat0_x_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat0_x cvmx_pip_stat0_x_t;\n+\n+/**\n+ * cvmx_pip_stat0_prt#\n+ *\n+ * \"PIP Statistics Counters\n+ * Note: special stat counter behavior\n+ * 1) Read and write operations must arbitrate for the statistics resources\n+ * along with the packet engines which are incrementing the counters.\n+ * In order to not drop packet information, the packet HW is always a\n+ * higher priority and the CSR requests will only be satisified when\n+ * there are idle cycles.  This can potentially cause long delays if the\n+ * system becomes full.\n+ * 2) stat counters can be cleared in two ways.  If PIP_STAT_CTL[RDCLR] is\n+ * set, then all read accesses will clear the register.  In addition,\n+ * any write to a stats register will also reset the register to zero.\n+ * Please note that the clearing operations must obey rule \\#1 above.\n+ * 3) all counters are wrapping - software must ensure they are read periodically\n+ * 4) The counters accumulate statistics for packets that are sent to PKI.  If\n+ * PTP_MODE is enabled, the 8B timestamp is prepended to the packet.  This\n+ * additional 8B of data is captured in the octet counts.\n+ * PIP_STAT0_PRT = PIP_STAT_DRP_PKTS / PIP_STAT_DRP_OCTS\"\n+ */\n+union cvmx_pip_stat0_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat0_prtx_s {\n+\t\tu64 drp_pkts : 32;\n+\t\tu64 drp_octs : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat0_prtx_s cn30xx;\n+\tstruct cvmx_pip_stat0_prtx_s cn31xx;\n+\tstruct cvmx_pip_stat0_prtx_s cn38xx;\n+\tstruct cvmx_pip_stat0_prtx_s cn38xxp2;\n+\tstruct cvmx_pip_stat0_prtx_s cn50xx;\n+\tstruct cvmx_pip_stat0_prtx_s cn52xx;\n+\tstruct cvmx_pip_stat0_prtx_s cn52xxp1;\n+\tstruct cvmx_pip_stat0_prtx_s cn56xx;\n+\tstruct cvmx_pip_stat0_prtx_s cn56xxp1;\n+\tstruct cvmx_pip_stat0_prtx_s cn58xx;\n+\tstruct cvmx_pip_stat0_prtx_s cn58xxp1;\n+\tstruct cvmx_pip_stat0_prtx_s cn61xx;\n+\tstruct cvmx_pip_stat0_prtx_s cn63xx;\n+\tstruct cvmx_pip_stat0_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_stat0_prtx_s cn66xx;\n+\tstruct cvmx_pip_stat0_prtx_s cn70xx;\n+\tstruct cvmx_pip_stat0_prtx_s cn70xxp1;\n+\tstruct cvmx_pip_stat0_prtx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat0_prtx cvmx_pip_stat0_prtx_t;\n+\n+/**\n+ * cvmx_pip_stat10_#\n+ *\n+ * PIP_STAT10_X = PIP_STAT_L2_MCAST / PIP_STAT_L2_BCAST\n+ *\n+ */\n+union cvmx_pip_stat10_x {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat10_x_s {\n+\t\tu64 bcast : 32;\n+\t\tu64 mcast : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat10_x_s cn68xx;\n+\tstruct cvmx_pip_stat10_x_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat10_x cvmx_pip_stat10_x_t;\n+\n+/**\n+ * cvmx_pip_stat10_prt#\n+ *\n+ * PIP_STAT10_PRTX = PIP_STAT_L2_MCAST / PIP_STAT_L2_BCAST\n+ *\n+ */\n+union cvmx_pip_stat10_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat10_prtx_s {\n+\t\tu64 bcast : 32;\n+\t\tu64 mcast : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat10_prtx_s cn52xx;\n+\tstruct cvmx_pip_stat10_prtx_s cn52xxp1;\n+\tstruct cvmx_pip_stat10_prtx_s cn56xx;\n+\tstruct cvmx_pip_stat10_prtx_s cn56xxp1;\n+\tstruct cvmx_pip_stat10_prtx_s cn61xx;\n+\tstruct cvmx_pip_stat10_prtx_s cn63xx;\n+\tstruct cvmx_pip_stat10_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_stat10_prtx_s cn66xx;\n+\tstruct cvmx_pip_stat10_prtx_s cn70xx;\n+\tstruct cvmx_pip_stat10_prtx_s cn70xxp1;\n+\tstruct cvmx_pip_stat10_prtx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat10_prtx cvmx_pip_stat10_prtx_t;\n+\n+/**\n+ * cvmx_pip_stat11_#\n+ *\n+ * PIP_STAT11_X = PIP_STAT_L3_MCAST / PIP_STAT_L3_BCAST\n+ *\n+ */\n+union cvmx_pip_stat11_x {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat11_x_s {\n+\t\tu64 bcast : 32;\n+\t\tu64 mcast : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat11_x_s cn68xx;\n+\tstruct cvmx_pip_stat11_x_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat11_x cvmx_pip_stat11_x_t;\n+\n+/**\n+ * cvmx_pip_stat11_prt#\n+ *\n+ * PIP_STAT11_PRTX = PIP_STAT_L3_MCAST / PIP_STAT_L3_BCAST\n+ *\n+ */\n+union cvmx_pip_stat11_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat11_prtx_s {\n+\t\tu64 bcast : 32;\n+\t\tu64 mcast : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat11_prtx_s cn52xx;\n+\tstruct cvmx_pip_stat11_prtx_s cn52xxp1;\n+\tstruct cvmx_pip_stat11_prtx_s cn56xx;\n+\tstruct cvmx_pip_stat11_prtx_s cn56xxp1;\n+\tstruct cvmx_pip_stat11_prtx_s cn61xx;\n+\tstruct cvmx_pip_stat11_prtx_s cn63xx;\n+\tstruct cvmx_pip_stat11_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_stat11_prtx_s cn66xx;\n+\tstruct cvmx_pip_stat11_prtx_s cn70xx;\n+\tstruct cvmx_pip_stat11_prtx_s cn70xxp1;\n+\tstruct cvmx_pip_stat11_prtx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat11_prtx cvmx_pip_stat11_prtx_t;\n+\n+/**\n+ * cvmx_pip_stat1_#\n+ *\n+ * PIP_STAT1_X = PIP_STAT_OCTS\n+ *\n+ */\n+union cvmx_pip_stat1_x {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat1_x_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 octs : 48;\n+\t} s;\n+\tstruct cvmx_pip_stat1_x_s cn68xx;\n+\tstruct cvmx_pip_stat1_x_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat1_x cvmx_pip_stat1_x_t;\n+\n+/**\n+ * cvmx_pip_stat1_prt#\n+ *\n+ * PIP_STAT1_PRTX = PIP_STAT_OCTS\n+ *\n+ */\n+union cvmx_pip_stat1_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat1_prtx_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 octs : 48;\n+\t} s;\n+\tstruct cvmx_pip_stat1_prtx_s cn30xx;\n+\tstruct cvmx_pip_stat1_prtx_s cn31xx;\n+\tstruct cvmx_pip_stat1_prtx_s cn38xx;\n+\tstruct cvmx_pip_stat1_prtx_s cn38xxp2;\n+\tstruct cvmx_pip_stat1_prtx_s cn50xx;\n+\tstruct cvmx_pip_stat1_prtx_s cn52xx;\n+\tstruct cvmx_pip_stat1_prtx_s cn52xxp1;\n+\tstruct cvmx_pip_stat1_prtx_s cn56xx;\n+\tstruct cvmx_pip_stat1_prtx_s cn56xxp1;\n+\tstruct cvmx_pip_stat1_prtx_s cn58xx;\n+\tstruct cvmx_pip_stat1_prtx_s cn58xxp1;\n+\tstruct cvmx_pip_stat1_prtx_s cn61xx;\n+\tstruct cvmx_pip_stat1_prtx_s cn63xx;\n+\tstruct cvmx_pip_stat1_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_stat1_prtx_s cn66xx;\n+\tstruct cvmx_pip_stat1_prtx_s cn70xx;\n+\tstruct cvmx_pip_stat1_prtx_s cn70xxp1;\n+\tstruct cvmx_pip_stat1_prtx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat1_prtx cvmx_pip_stat1_prtx_t;\n+\n+/**\n+ * cvmx_pip_stat2_#\n+ *\n+ * PIP_STAT2_X = PIP_STAT_PKTS     / PIP_STAT_RAW\n+ *\n+ */\n+union cvmx_pip_stat2_x {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat2_x_s {\n+\t\tu64 pkts : 32;\n+\t\tu64 raw : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat2_x_s cn68xx;\n+\tstruct cvmx_pip_stat2_x_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat2_x cvmx_pip_stat2_x_t;\n+\n+/**\n+ * cvmx_pip_stat2_prt#\n+ *\n+ * PIP_STAT2_PRTX = PIP_STAT_PKTS     / PIP_STAT_RAW\n+ *\n+ */\n+union cvmx_pip_stat2_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat2_prtx_s {\n+\t\tu64 pkts : 32;\n+\t\tu64 raw : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat2_prtx_s cn30xx;\n+\tstruct cvmx_pip_stat2_prtx_s cn31xx;\n+\tstruct cvmx_pip_stat2_prtx_s cn38xx;\n+\tstruct cvmx_pip_stat2_prtx_s cn38xxp2;\n+\tstruct cvmx_pip_stat2_prtx_s cn50xx;\n+\tstruct cvmx_pip_stat2_prtx_s cn52xx;\n+\tstruct cvmx_pip_stat2_prtx_s cn52xxp1;\n+\tstruct cvmx_pip_stat2_prtx_s cn56xx;\n+\tstruct cvmx_pip_stat2_prtx_s cn56xxp1;\n+\tstruct cvmx_pip_stat2_prtx_s cn58xx;\n+\tstruct cvmx_pip_stat2_prtx_s cn58xxp1;\n+\tstruct cvmx_pip_stat2_prtx_s cn61xx;\n+\tstruct cvmx_pip_stat2_prtx_s cn63xx;\n+\tstruct cvmx_pip_stat2_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_stat2_prtx_s cn66xx;\n+\tstruct cvmx_pip_stat2_prtx_s cn70xx;\n+\tstruct cvmx_pip_stat2_prtx_s cn70xxp1;\n+\tstruct cvmx_pip_stat2_prtx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat2_prtx cvmx_pip_stat2_prtx_t;\n+\n+/**\n+ * cvmx_pip_stat3_#\n+ *\n+ * PIP_STAT3_X = PIP_STAT_BCST     / PIP_STAT_MCST\n+ *\n+ */\n+union cvmx_pip_stat3_x {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat3_x_s {\n+\t\tu64 bcst : 32;\n+\t\tu64 mcst : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat3_x_s cn68xx;\n+\tstruct cvmx_pip_stat3_x_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat3_x cvmx_pip_stat3_x_t;\n+\n+/**\n+ * cvmx_pip_stat3_prt#\n+ *\n+ * PIP_STAT3_PRTX = PIP_STAT_BCST     / PIP_STAT_MCST\n+ *\n+ */\n+union cvmx_pip_stat3_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat3_prtx_s {\n+\t\tu64 bcst : 32;\n+\t\tu64 mcst : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat3_prtx_s cn30xx;\n+\tstruct cvmx_pip_stat3_prtx_s cn31xx;\n+\tstruct cvmx_pip_stat3_prtx_s cn38xx;\n+\tstruct cvmx_pip_stat3_prtx_s cn38xxp2;\n+\tstruct cvmx_pip_stat3_prtx_s cn50xx;\n+\tstruct cvmx_pip_stat3_prtx_s cn52xx;\n+\tstruct cvmx_pip_stat3_prtx_s cn52xxp1;\n+\tstruct cvmx_pip_stat3_prtx_s cn56xx;\n+\tstruct cvmx_pip_stat3_prtx_s cn56xxp1;\n+\tstruct cvmx_pip_stat3_prtx_s cn58xx;\n+\tstruct cvmx_pip_stat3_prtx_s cn58xxp1;\n+\tstruct cvmx_pip_stat3_prtx_s cn61xx;\n+\tstruct cvmx_pip_stat3_prtx_s cn63xx;\n+\tstruct cvmx_pip_stat3_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_stat3_prtx_s cn66xx;\n+\tstruct cvmx_pip_stat3_prtx_s cn70xx;\n+\tstruct cvmx_pip_stat3_prtx_s cn70xxp1;\n+\tstruct cvmx_pip_stat3_prtx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat3_prtx cvmx_pip_stat3_prtx_t;\n+\n+/**\n+ * cvmx_pip_stat4_#\n+ *\n+ * PIP_STAT4_X = PIP_STAT_HIST1    / PIP_STAT_HIST0\n+ *\n+ */\n+union cvmx_pip_stat4_x {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat4_x_s {\n+\t\tu64 h65to127 : 32;\n+\t\tu64 h64 : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat4_x_s cn68xx;\n+\tstruct cvmx_pip_stat4_x_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat4_x cvmx_pip_stat4_x_t;\n+\n+/**\n+ * cvmx_pip_stat4_prt#\n+ *\n+ * PIP_STAT4_PRTX = PIP_STAT_HIST1    / PIP_STAT_HIST0\n+ *\n+ */\n+union cvmx_pip_stat4_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat4_prtx_s {\n+\t\tu64 h65to127 : 32;\n+\t\tu64 h64 : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat4_prtx_s cn30xx;\n+\tstruct cvmx_pip_stat4_prtx_s cn31xx;\n+\tstruct cvmx_pip_stat4_prtx_s cn38xx;\n+\tstruct cvmx_pip_stat4_prtx_s cn38xxp2;\n+\tstruct cvmx_pip_stat4_prtx_s cn50xx;\n+\tstruct cvmx_pip_stat4_prtx_s cn52xx;\n+\tstruct cvmx_pip_stat4_prtx_s cn52xxp1;\n+\tstruct cvmx_pip_stat4_prtx_s cn56xx;\n+\tstruct cvmx_pip_stat4_prtx_s cn56xxp1;\n+\tstruct cvmx_pip_stat4_prtx_s cn58xx;\n+\tstruct cvmx_pip_stat4_prtx_s cn58xxp1;\n+\tstruct cvmx_pip_stat4_prtx_s cn61xx;\n+\tstruct cvmx_pip_stat4_prtx_s cn63xx;\n+\tstruct cvmx_pip_stat4_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_stat4_prtx_s cn66xx;\n+\tstruct cvmx_pip_stat4_prtx_s cn70xx;\n+\tstruct cvmx_pip_stat4_prtx_s cn70xxp1;\n+\tstruct cvmx_pip_stat4_prtx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat4_prtx cvmx_pip_stat4_prtx_t;\n+\n+/**\n+ * cvmx_pip_stat5_#\n+ *\n+ * PIP_STAT5_X = PIP_STAT_HIST3    / PIP_STAT_HIST2\n+ *\n+ */\n+union cvmx_pip_stat5_x {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat5_x_s {\n+\t\tu64 h256to511 : 32;\n+\t\tu64 h128to255 : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat5_x_s cn68xx;\n+\tstruct cvmx_pip_stat5_x_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat5_x cvmx_pip_stat5_x_t;\n+\n+/**\n+ * cvmx_pip_stat5_prt#\n+ *\n+ * PIP_STAT5_PRTX = PIP_STAT_HIST3    / PIP_STAT_HIST2\n+ *\n+ */\n+union cvmx_pip_stat5_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat5_prtx_s {\n+\t\tu64 h256to511 : 32;\n+\t\tu64 h128to255 : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat5_prtx_s cn30xx;\n+\tstruct cvmx_pip_stat5_prtx_s cn31xx;\n+\tstruct cvmx_pip_stat5_prtx_s cn38xx;\n+\tstruct cvmx_pip_stat5_prtx_s cn38xxp2;\n+\tstruct cvmx_pip_stat5_prtx_s cn50xx;\n+\tstruct cvmx_pip_stat5_prtx_s cn52xx;\n+\tstruct cvmx_pip_stat5_prtx_s cn52xxp1;\n+\tstruct cvmx_pip_stat5_prtx_s cn56xx;\n+\tstruct cvmx_pip_stat5_prtx_s cn56xxp1;\n+\tstruct cvmx_pip_stat5_prtx_s cn58xx;\n+\tstruct cvmx_pip_stat5_prtx_s cn58xxp1;\n+\tstruct cvmx_pip_stat5_prtx_s cn61xx;\n+\tstruct cvmx_pip_stat5_prtx_s cn63xx;\n+\tstruct cvmx_pip_stat5_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_stat5_prtx_s cn66xx;\n+\tstruct cvmx_pip_stat5_prtx_s cn70xx;\n+\tstruct cvmx_pip_stat5_prtx_s cn70xxp1;\n+\tstruct cvmx_pip_stat5_prtx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat5_prtx cvmx_pip_stat5_prtx_t;\n+\n+/**\n+ * cvmx_pip_stat6_#\n+ *\n+ * PIP_STAT6_X = PIP_STAT_HIST5    / PIP_STAT_HIST4\n+ *\n+ */\n+union cvmx_pip_stat6_x {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat6_x_s {\n+\t\tu64 h1024to1518 : 32;\n+\t\tu64 h512to1023 : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat6_x_s cn68xx;\n+\tstruct cvmx_pip_stat6_x_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat6_x cvmx_pip_stat6_x_t;\n+\n+/**\n+ * cvmx_pip_stat6_prt#\n+ *\n+ * PIP_STAT6_PRTX = PIP_STAT_HIST5    / PIP_STAT_HIST4\n+ *\n+ */\n+union cvmx_pip_stat6_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat6_prtx_s {\n+\t\tu64 h1024to1518 : 32;\n+\t\tu64 h512to1023 : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat6_prtx_s cn30xx;\n+\tstruct cvmx_pip_stat6_prtx_s cn31xx;\n+\tstruct cvmx_pip_stat6_prtx_s cn38xx;\n+\tstruct cvmx_pip_stat6_prtx_s cn38xxp2;\n+\tstruct cvmx_pip_stat6_prtx_s cn50xx;\n+\tstruct cvmx_pip_stat6_prtx_s cn52xx;\n+\tstruct cvmx_pip_stat6_prtx_s cn52xxp1;\n+\tstruct cvmx_pip_stat6_prtx_s cn56xx;\n+\tstruct cvmx_pip_stat6_prtx_s cn56xxp1;\n+\tstruct cvmx_pip_stat6_prtx_s cn58xx;\n+\tstruct cvmx_pip_stat6_prtx_s cn58xxp1;\n+\tstruct cvmx_pip_stat6_prtx_s cn61xx;\n+\tstruct cvmx_pip_stat6_prtx_s cn63xx;\n+\tstruct cvmx_pip_stat6_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_stat6_prtx_s cn66xx;\n+\tstruct cvmx_pip_stat6_prtx_s cn70xx;\n+\tstruct cvmx_pip_stat6_prtx_s cn70xxp1;\n+\tstruct cvmx_pip_stat6_prtx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat6_prtx cvmx_pip_stat6_prtx_t;\n+\n+/**\n+ * cvmx_pip_stat7_#\n+ *\n+ * PIP_STAT7_X = PIP_STAT_FCS      / PIP_STAT_HIST6\n+ *\n+ */\n+union cvmx_pip_stat7_x {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat7_x_s {\n+\t\tu64 fcs : 32;\n+\t\tu64 h1519 : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat7_x_s cn68xx;\n+\tstruct cvmx_pip_stat7_x_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat7_x cvmx_pip_stat7_x_t;\n+\n+/**\n+ * cvmx_pip_stat7_prt#\n+ *\n+ * PIP_STAT7_PRTX = PIP_STAT_FCS      / PIP_STAT_HIST6\n+ *\n+ *\n+ * Notes:\n+ * DPI does not check FCS, therefore FCS will never increment on DPI ports 32-35\n+ * sRIO does not check FCS, therefore FCS will never increment on sRIO ports 40-47\n+ */\n+union cvmx_pip_stat7_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat7_prtx_s {\n+\t\tu64 fcs : 32;\n+\t\tu64 h1519 : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat7_prtx_s cn30xx;\n+\tstruct cvmx_pip_stat7_prtx_s cn31xx;\n+\tstruct cvmx_pip_stat7_prtx_s cn38xx;\n+\tstruct cvmx_pip_stat7_prtx_s cn38xxp2;\n+\tstruct cvmx_pip_stat7_prtx_s cn50xx;\n+\tstruct cvmx_pip_stat7_prtx_s cn52xx;\n+\tstruct cvmx_pip_stat7_prtx_s cn52xxp1;\n+\tstruct cvmx_pip_stat7_prtx_s cn56xx;\n+\tstruct cvmx_pip_stat7_prtx_s cn56xxp1;\n+\tstruct cvmx_pip_stat7_prtx_s cn58xx;\n+\tstruct cvmx_pip_stat7_prtx_s cn58xxp1;\n+\tstruct cvmx_pip_stat7_prtx_s cn61xx;\n+\tstruct cvmx_pip_stat7_prtx_s cn63xx;\n+\tstruct cvmx_pip_stat7_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_stat7_prtx_s cn66xx;\n+\tstruct cvmx_pip_stat7_prtx_s cn70xx;\n+\tstruct cvmx_pip_stat7_prtx_s cn70xxp1;\n+\tstruct cvmx_pip_stat7_prtx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat7_prtx cvmx_pip_stat7_prtx_t;\n+\n+/**\n+ * cvmx_pip_stat8_#\n+ *\n+ * PIP_STAT8_X = PIP_STAT_FRAG     / PIP_STAT_UNDER\n+ *\n+ */\n+union cvmx_pip_stat8_x {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat8_x_s {\n+\t\tu64 frag : 32;\n+\t\tu64 undersz : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat8_x_s cn68xx;\n+\tstruct cvmx_pip_stat8_x_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat8_x cvmx_pip_stat8_x_t;\n+\n+/**\n+ * cvmx_pip_stat8_prt#\n+ *\n+ * PIP_STAT8_PRTX = PIP_STAT_FRAG     / PIP_STAT_UNDER\n+ *\n+ *\n+ * Notes:\n+ * DPI does not check FCS, therefore FRAG will never increment on DPI ports 32-35\n+ * sRIO does not check FCS, therefore FRAG will never increment on sRIO ports 40-47\n+ */\n+union cvmx_pip_stat8_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat8_prtx_s {\n+\t\tu64 frag : 32;\n+\t\tu64 undersz : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat8_prtx_s cn30xx;\n+\tstruct cvmx_pip_stat8_prtx_s cn31xx;\n+\tstruct cvmx_pip_stat8_prtx_s cn38xx;\n+\tstruct cvmx_pip_stat8_prtx_s cn38xxp2;\n+\tstruct cvmx_pip_stat8_prtx_s cn50xx;\n+\tstruct cvmx_pip_stat8_prtx_s cn52xx;\n+\tstruct cvmx_pip_stat8_prtx_s cn52xxp1;\n+\tstruct cvmx_pip_stat8_prtx_s cn56xx;\n+\tstruct cvmx_pip_stat8_prtx_s cn56xxp1;\n+\tstruct cvmx_pip_stat8_prtx_s cn58xx;\n+\tstruct cvmx_pip_stat8_prtx_s cn58xxp1;\n+\tstruct cvmx_pip_stat8_prtx_s cn61xx;\n+\tstruct cvmx_pip_stat8_prtx_s cn63xx;\n+\tstruct cvmx_pip_stat8_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_stat8_prtx_s cn66xx;\n+\tstruct cvmx_pip_stat8_prtx_s cn70xx;\n+\tstruct cvmx_pip_stat8_prtx_s cn70xxp1;\n+\tstruct cvmx_pip_stat8_prtx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat8_prtx cvmx_pip_stat8_prtx_t;\n+\n+/**\n+ * cvmx_pip_stat9_#\n+ *\n+ * PIP_STAT9_X = PIP_STAT_JABBER   / PIP_STAT_OVER\n+ *\n+ */\n+union cvmx_pip_stat9_x {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat9_x_s {\n+\t\tu64 jabber : 32;\n+\t\tu64 oversz : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat9_x_s cn68xx;\n+\tstruct cvmx_pip_stat9_x_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat9_x cvmx_pip_stat9_x_t;\n+\n+/**\n+ * cvmx_pip_stat9_prt#\n+ *\n+ * PIP_STAT9_PRTX = PIP_STAT_JABBER   / PIP_STAT_OVER\n+ *\n+ *\n+ * Notes:\n+ * DPI does not check FCS, therefore JABBER will never increment on DPI ports 32-35\n+ * sRIO does not check FCS, therefore JABBER will never increment on sRIO ports 40-47 due to FCS errors\n+ * sRIO does use the JABBER opcode to communicate sRIO error, therefore JABBER can increment under the sRIO error conditions\n+ */\n+union cvmx_pip_stat9_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat9_prtx_s {\n+\t\tu64 jabber : 32;\n+\t\tu64 oversz : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat9_prtx_s cn30xx;\n+\tstruct cvmx_pip_stat9_prtx_s cn31xx;\n+\tstruct cvmx_pip_stat9_prtx_s cn38xx;\n+\tstruct cvmx_pip_stat9_prtx_s cn38xxp2;\n+\tstruct cvmx_pip_stat9_prtx_s cn50xx;\n+\tstruct cvmx_pip_stat9_prtx_s cn52xx;\n+\tstruct cvmx_pip_stat9_prtx_s cn52xxp1;\n+\tstruct cvmx_pip_stat9_prtx_s cn56xx;\n+\tstruct cvmx_pip_stat9_prtx_s cn56xxp1;\n+\tstruct cvmx_pip_stat9_prtx_s cn58xx;\n+\tstruct cvmx_pip_stat9_prtx_s cn58xxp1;\n+\tstruct cvmx_pip_stat9_prtx_s cn61xx;\n+\tstruct cvmx_pip_stat9_prtx_s cn63xx;\n+\tstruct cvmx_pip_stat9_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_stat9_prtx_s cn66xx;\n+\tstruct cvmx_pip_stat9_prtx_s cn70xx;\n+\tstruct cvmx_pip_stat9_prtx_s cn70xxp1;\n+\tstruct cvmx_pip_stat9_prtx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat9_prtx cvmx_pip_stat9_prtx_t;\n+\n+/**\n+ * cvmx_pip_stat_ctl\n+ *\n+ * Controls how the PIP statistics counters are handled.\n+ *\n+ */\n+union cvmx_pip_stat_ctl {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat_ctl_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 mode : 1;\n+\t\tu64 reserved_1_7 : 7;\n+\t\tu64 rdclr : 1;\n+\t} s;\n+\tstruct cvmx_pip_stat_ctl_cn30xx {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 rdclr : 1;\n+\t} cn30xx;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn31xx;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn38xx;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn38xxp2;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn50xx;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn52xx;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn52xxp1;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn56xx;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn56xxp1;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn58xx;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn58xxp1;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn61xx;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn63xx;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn63xxp1;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn66xx;\n+\tstruct cvmx_pip_stat_ctl_s cn68xx;\n+\tstruct cvmx_pip_stat_ctl_s cn68xxp1;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn70xx;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cn70xxp1;\n+\tstruct cvmx_pip_stat_ctl_cn30xx cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat_ctl cvmx_pip_stat_ctl_t;\n+\n+/**\n+ * cvmx_pip_stat_inb_errs#\n+ *\n+ * Inbound stats collect all data sent to PIP from all packet interfaces.\n+ * Its the raw counts of everything that comes into the block.  The counts\n+ * will reflect all error packets and packets dropped by the PKI RED engine.\n+ * These counts are intended for system debug, but could convey useful\n+ * information in production systems.\n+ */\n+union cvmx_pip_stat_inb_errsx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat_inb_errsx_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 errs : 16;\n+\t} s;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn30xx;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn31xx;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn38xx;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn38xxp2;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn50xx;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn52xx;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn52xxp1;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn56xx;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn56xxp1;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn58xx;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn58xxp1;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn61xx;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn63xx;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn63xxp1;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn66xx;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn70xx;\n+\tstruct cvmx_pip_stat_inb_errsx_s cn70xxp1;\n+\tstruct cvmx_pip_stat_inb_errsx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat_inb_errsx cvmx_pip_stat_inb_errsx_t;\n+\n+/**\n+ * cvmx_pip_stat_inb_errs_pknd#\n+ *\n+ * PIP_STAT_INB_ERRS_PKNDX = Inbound error packets received by PIP per pkind\n+ *\n+ * Inbound stats collect all data sent to PIP from all packet interfaces.\n+ * Its the raw counts of everything that comes into the block.  The counts\n+ * will reflect all error packets and packets dropped by the PKI RED engine.\n+ * These counts are intended for system debug, but could convey useful\n+ * information in production systems.\n+ */\n+union cvmx_pip_stat_inb_errs_pkndx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat_inb_errs_pkndx_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 errs : 16;\n+\t} s;\n+\tstruct cvmx_pip_stat_inb_errs_pkndx_s cn68xx;\n+\tstruct cvmx_pip_stat_inb_errs_pkndx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat_inb_errs_pkndx cvmx_pip_stat_inb_errs_pkndx_t;\n+\n+/**\n+ * cvmx_pip_stat_inb_octs#\n+ *\n+ * Inbound stats collect all data sent to PIP from all packet interfaces.\n+ * Its the raw counts of everything that comes into the block.  The counts\n+ * will reflect all error packets and packets dropped by the PKI RED engine.\n+ * These counts are intended for system debug, but could convey useful\n+ * information in production systems. The OCTS will include the bytes from\n+ * timestamp fields in PTP_MODE.\n+ */\n+union cvmx_pip_stat_inb_octsx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat_inb_octsx_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 octs : 48;\n+\t} s;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn30xx;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn31xx;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn38xx;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn38xxp2;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn50xx;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn52xx;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn52xxp1;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn56xx;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn56xxp1;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn58xx;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn58xxp1;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn61xx;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn63xx;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn63xxp1;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn66xx;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn70xx;\n+\tstruct cvmx_pip_stat_inb_octsx_s cn70xxp1;\n+\tstruct cvmx_pip_stat_inb_octsx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat_inb_octsx cvmx_pip_stat_inb_octsx_t;\n+\n+/**\n+ * cvmx_pip_stat_inb_octs_pknd#\n+ *\n+ * PIP_STAT_INB_OCTS_PKNDX = Inbound octets received by PIP per pkind\n+ *\n+ * Inbound stats collect all data sent to PIP from all packet interfaces.\n+ * Its the raw counts of everything that comes into the block.  The counts\n+ * will reflect all error packets and packets dropped by the PKI RED engine.\n+ * These counts are intended for system debug, but could convey useful\n+ * information in production systems. The OCTS will include the bytes from\n+ * timestamp fields in PTP_MODE.\n+ */\n+union cvmx_pip_stat_inb_octs_pkndx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat_inb_octs_pkndx_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 octs : 48;\n+\t} s;\n+\tstruct cvmx_pip_stat_inb_octs_pkndx_s cn68xx;\n+\tstruct cvmx_pip_stat_inb_octs_pkndx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat_inb_octs_pkndx cvmx_pip_stat_inb_octs_pkndx_t;\n+\n+/**\n+ * cvmx_pip_stat_inb_pkts#\n+ *\n+ * Inbound stats collect all data sent to PIP from all packet interfaces.\n+ * Its the raw counts of everything that comes into the block.  The counts\n+ * will reflect all error packets and packets dropped by the PKI RED engine.\n+ * These counts are intended for system debug, but could convey useful\n+ * information in production systems.\n+ */\n+union cvmx_pip_stat_inb_pktsx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat_inb_pktsx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 pkts : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn30xx;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn31xx;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn38xx;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn38xxp2;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn50xx;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn52xx;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn52xxp1;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn56xx;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn56xxp1;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn58xx;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn58xxp1;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn61xx;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn63xx;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn63xxp1;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn66xx;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn70xx;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cn70xxp1;\n+\tstruct cvmx_pip_stat_inb_pktsx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_stat_inb_pktsx cvmx_pip_stat_inb_pktsx_t;\n+\n+/**\n+ * cvmx_pip_stat_inb_pkts_pknd#\n+ *\n+ * PIP_STAT_INB_PKTS_PKNDX = Inbound packets received by PIP per pkind\n+ *\n+ * Inbound stats collect all data sent to PIP from all packet interfaces.\n+ * Its the raw counts of everything that comes into the block.  The counts\n+ * will reflect all error packets and packets dropped by the PKI RED engine.\n+ * These counts are intended for system debug, but could convey useful\n+ * information in production systems.\n+ */\n+union cvmx_pip_stat_inb_pkts_pkndx {\n+\tu64 u64;\n+\tstruct cvmx_pip_stat_inb_pkts_pkndx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 pkts : 32;\n+\t} s;\n+\tstruct cvmx_pip_stat_inb_pkts_pkndx_s cn68xx;\n+\tstruct cvmx_pip_stat_inb_pkts_pkndx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_stat_inb_pkts_pkndx cvmx_pip_stat_inb_pkts_pkndx_t;\n+\n+/**\n+ * cvmx_pip_sub_pkind_fcs#\n+ */\n+union cvmx_pip_sub_pkind_fcsx {\n+\tu64 u64;\n+\tstruct cvmx_pip_sub_pkind_fcsx_s {\n+\t\tu64 port_bit : 64;\n+\t} s;\n+\tstruct cvmx_pip_sub_pkind_fcsx_s cn68xx;\n+\tstruct cvmx_pip_sub_pkind_fcsx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_pip_sub_pkind_fcsx cvmx_pip_sub_pkind_fcsx_t;\n+\n+/**\n+ * cvmx_pip_tag_inc#\n+ *\n+ * # $PIP_TAG_INCX = 0x300+X X=(0..63) RegType=(RSL) RtlReg=(pip_tag_inc_csr_direct_TestbuilderTask)\n+ *\n+ */\n+union cvmx_pip_tag_incx {\n+\tu64 u64;\n+\tstruct cvmx_pip_tag_incx_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 en : 8;\n+\t} s;\n+\tstruct cvmx_pip_tag_incx_s cn30xx;\n+\tstruct cvmx_pip_tag_incx_s cn31xx;\n+\tstruct cvmx_pip_tag_incx_s cn38xx;\n+\tstruct cvmx_pip_tag_incx_s cn38xxp2;\n+\tstruct cvmx_pip_tag_incx_s cn50xx;\n+\tstruct cvmx_pip_tag_incx_s cn52xx;\n+\tstruct cvmx_pip_tag_incx_s cn52xxp1;\n+\tstruct cvmx_pip_tag_incx_s cn56xx;\n+\tstruct cvmx_pip_tag_incx_s cn56xxp1;\n+\tstruct cvmx_pip_tag_incx_s cn58xx;\n+\tstruct cvmx_pip_tag_incx_s cn58xxp1;\n+\tstruct cvmx_pip_tag_incx_s cn61xx;\n+\tstruct cvmx_pip_tag_incx_s cn63xx;\n+\tstruct cvmx_pip_tag_incx_s cn63xxp1;\n+\tstruct cvmx_pip_tag_incx_s cn66xx;\n+\tstruct cvmx_pip_tag_incx_s cn68xx;\n+\tstruct cvmx_pip_tag_incx_s cn68xxp1;\n+\tstruct cvmx_pip_tag_incx_s cn70xx;\n+\tstruct cvmx_pip_tag_incx_s cn70xxp1;\n+\tstruct cvmx_pip_tag_incx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_tag_incx cvmx_pip_tag_incx_t;\n+\n+/**\n+ * cvmx_pip_tag_mask\n+ *\n+ * PIP_TAG_MASK = Mask bit in the tag generation\n+ *\n+ */\n+union cvmx_pip_tag_mask {\n+\tu64 u64;\n+\tstruct cvmx_pip_tag_mask_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 mask : 16;\n+\t} s;\n+\tstruct cvmx_pip_tag_mask_s cn30xx;\n+\tstruct cvmx_pip_tag_mask_s cn31xx;\n+\tstruct cvmx_pip_tag_mask_s cn38xx;\n+\tstruct cvmx_pip_tag_mask_s cn38xxp2;\n+\tstruct cvmx_pip_tag_mask_s cn50xx;\n+\tstruct cvmx_pip_tag_mask_s cn52xx;\n+\tstruct cvmx_pip_tag_mask_s cn52xxp1;\n+\tstruct cvmx_pip_tag_mask_s cn56xx;\n+\tstruct cvmx_pip_tag_mask_s cn56xxp1;\n+\tstruct cvmx_pip_tag_mask_s cn58xx;\n+\tstruct cvmx_pip_tag_mask_s cn58xxp1;\n+\tstruct cvmx_pip_tag_mask_s cn61xx;\n+\tstruct cvmx_pip_tag_mask_s cn63xx;\n+\tstruct cvmx_pip_tag_mask_s cn63xxp1;\n+\tstruct cvmx_pip_tag_mask_s cn66xx;\n+\tstruct cvmx_pip_tag_mask_s cn68xx;\n+\tstruct cvmx_pip_tag_mask_s cn68xxp1;\n+\tstruct cvmx_pip_tag_mask_s cn70xx;\n+\tstruct cvmx_pip_tag_mask_s cn70xxp1;\n+\tstruct cvmx_pip_tag_mask_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_tag_mask cvmx_pip_tag_mask_t;\n+\n+/**\n+ * cvmx_pip_tag_secret\n+ *\n+ * The source and destination IV's provide a mechanism for each Octeon to be unique.\n+ *\n+ */\n+union cvmx_pip_tag_secret {\n+\tu64 u64;\n+\tstruct cvmx_pip_tag_secret_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 dst : 16;\n+\t\tu64 src : 16;\n+\t} s;\n+\tstruct cvmx_pip_tag_secret_s cn30xx;\n+\tstruct cvmx_pip_tag_secret_s cn31xx;\n+\tstruct cvmx_pip_tag_secret_s cn38xx;\n+\tstruct cvmx_pip_tag_secret_s cn38xxp2;\n+\tstruct cvmx_pip_tag_secret_s cn50xx;\n+\tstruct cvmx_pip_tag_secret_s cn52xx;\n+\tstruct cvmx_pip_tag_secret_s cn52xxp1;\n+\tstruct cvmx_pip_tag_secret_s cn56xx;\n+\tstruct cvmx_pip_tag_secret_s cn56xxp1;\n+\tstruct cvmx_pip_tag_secret_s cn58xx;\n+\tstruct cvmx_pip_tag_secret_s cn58xxp1;\n+\tstruct cvmx_pip_tag_secret_s cn61xx;\n+\tstruct cvmx_pip_tag_secret_s cn63xx;\n+\tstruct cvmx_pip_tag_secret_s cn63xxp1;\n+\tstruct cvmx_pip_tag_secret_s cn66xx;\n+\tstruct cvmx_pip_tag_secret_s cn68xx;\n+\tstruct cvmx_pip_tag_secret_s cn68xxp1;\n+\tstruct cvmx_pip_tag_secret_s cn70xx;\n+\tstruct cvmx_pip_tag_secret_s cn70xxp1;\n+\tstruct cvmx_pip_tag_secret_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_tag_secret cvmx_pip_tag_secret_t;\n+\n+/**\n+ * cvmx_pip_todo_entry\n+ *\n+ * Summary of the current packet that has completed and waiting to be processed\n+ *\n+ */\n+union cvmx_pip_todo_entry {\n+\tu64 u64;\n+\tstruct cvmx_pip_todo_entry_s {\n+\t\tu64 val : 1;\n+\t\tu64 reserved_62_62 : 1;\n+\t\tu64 entry : 62;\n+\t} s;\n+\tstruct cvmx_pip_todo_entry_s cn30xx;\n+\tstruct cvmx_pip_todo_entry_s cn31xx;\n+\tstruct cvmx_pip_todo_entry_s cn38xx;\n+\tstruct cvmx_pip_todo_entry_s cn38xxp2;\n+\tstruct cvmx_pip_todo_entry_s cn50xx;\n+\tstruct cvmx_pip_todo_entry_s cn52xx;\n+\tstruct cvmx_pip_todo_entry_s cn52xxp1;\n+\tstruct cvmx_pip_todo_entry_s cn56xx;\n+\tstruct cvmx_pip_todo_entry_s cn56xxp1;\n+\tstruct cvmx_pip_todo_entry_s cn58xx;\n+\tstruct cvmx_pip_todo_entry_s cn58xxp1;\n+\tstruct cvmx_pip_todo_entry_s cn61xx;\n+\tstruct cvmx_pip_todo_entry_s cn63xx;\n+\tstruct cvmx_pip_todo_entry_s cn63xxp1;\n+\tstruct cvmx_pip_todo_entry_s cn66xx;\n+\tstruct cvmx_pip_todo_entry_s cn68xx;\n+\tstruct cvmx_pip_todo_entry_s cn68xxp1;\n+\tstruct cvmx_pip_todo_entry_s cn70xx;\n+\tstruct cvmx_pip_todo_entry_s cn70xxp1;\n+\tstruct cvmx_pip_todo_entry_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_todo_entry cvmx_pip_todo_entry_t;\n+\n+/**\n+ * cvmx_pip_vlan_etypes#\n+ */\n+union cvmx_pip_vlan_etypesx {\n+\tu64 u64;\n+\tstruct cvmx_pip_vlan_etypesx_s {\n+\t\tu64 type3 : 16;\n+\t\tu64 type2 : 16;\n+\t\tu64 type1 : 16;\n+\t\tu64 type0 : 16;\n+\t} s;\n+\tstruct cvmx_pip_vlan_etypesx_s cn61xx;\n+\tstruct cvmx_pip_vlan_etypesx_s cn66xx;\n+\tstruct cvmx_pip_vlan_etypesx_s cn68xx;\n+\tstruct cvmx_pip_vlan_etypesx_s cn70xx;\n+\tstruct cvmx_pip_vlan_etypesx_s cn70xxp1;\n+\tstruct cvmx_pip_vlan_etypesx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pip_vlan_etypesx cvmx_pip_vlan_etypesx_t;\n+\n+/**\n+ * cvmx_pip_xstat0_prt#\n+ *\n+ * PIP_XSTAT0_PRT = PIP_XSTAT_DRP_PKTS / PIP_XSTAT_DRP_OCTS\n+ *\n+ */\n+union cvmx_pip_xstat0_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_xstat0_prtx_s {\n+\t\tu64 drp_pkts : 32;\n+\t\tu64 drp_octs : 32;\n+\t} s;\n+\tstruct cvmx_pip_xstat0_prtx_s cn63xx;\n+\tstruct cvmx_pip_xstat0_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_xstat0_prtx_s cn66xx;\n+};\n+\n+typedef union cvmx_pip_xstat0_prtx cvmx_pip_xstat0_prtx_t;\n+\n+/**\n+ * cvmx_pip_xstat10_prt#\n+ *\n+ * PIP_XSTAT10_PRTX = PIP_XSTAT_L2_MCAST / PIP_XSTAT_L2_BCAST\n+ *\n+ */\n+union cvmx_pip_xstat10_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_xstat10_prtx_s {\n+\t\tu64 bcast : 32;\n+\t\tu64 mcast : 32;\n+\t} s;\n+\tstruct cvmx_pip_xstat10_prtx_s cn63xx;\n+\tstruct cvmx_pip_xstat10_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_xstat10_prtx_s cn66xx;\n+};\n+\n+typedef union cvmx_pip_xstat10_prtx cvmx_pip_xstat10_prtx_t;\n+\n+/**\n+ * cvmx_pip_xstat11_prt#\n+ *\n+ * PIP_XSTAT11_PRTX = PIP_XSTAT_L3_MCAST / PIP_XSTAT_L3_BCAST\n+ *\n+ */\n+union cvmx_pip_xstat11_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_xstat11_prtx_s {\n+\t\tu64 bcast : 32;\n+\t\tu64 mcast : 32;\n+\t} s;\n+\tstruct cvmx_pip_xstat11_prtx_s cn63xx;\n+\tstruct cvmx_pip_xstat11_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_xstat11_prtx_s cn66xx;\n+};\n+\n+typedef union cvmx_pip_xstat11_prtx cvmx_pip_xstat11_prtx_t;\n+\n+/**\n+ * cvmx_pip_xstat1_prt#\n+ *\n+ * PIP_XSTAT1_PRTX = PIP_XSTAT_OCTS\n+ *\n+ */\n+union cvmx_pip_xstat1_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_xstat1_prtx_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 octs : 48;\n+\t} s;\n+\tstruct cvmx_pip_xstat1_prtx_s cn63xx;\n+\tstruct cvmx_pip_xstat1_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_xstat1_prtx_s cn66xx;\n+};\n+\n+typedef union cvmx_pip_xstat1_prtx cvmx_pip_xstat1_prtx_t;\n+\n+/**\n+ * cvmx_pip_xstat2_prt#\n+ *\n+ * PIP_XSTAT2_PRTX = PIP_XSTAT_PKTS     / PIP_XSTAT_RAW\n+ *\n+ */\n+union cvmx_pip_xstat2_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_xstat2_prtx_s {\n+\t\tu64 pkts : 32;\n+\t\tu64 raw : 32;\n+\t} s;\n+\tstruct cvmx_pip_xstat2_prtx_s cn63xx;\n+\tstruct cvmx_pip_xstat2_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_xstat2_prtx_s cn66xx;\n+};\n+\n+typedef union cvmx_pip_xstat2_prtx cvmx_pip_xstat2_prtx_t;\n+\n+/**\n+ * cvmx_pip_xstat3_prt#\n+ *\n+ * PIP_XSTAT3_PRTX = PIP_XSTAT_BCST     / PIP_XSTAT_MCST\n+ *\n+ */\n+union cvmx_pip_xstat3_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_xstat3_prtx_s {\n+\t\tu64 bcst : 32;\n+\t\tu64 mcst : 32;\n+\t} s;\n+\tstruct cvmx_pip_xstat3_prtx_s cn63xx;\n+\tstruct cvmx_pip_xstat3_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_xstat3_prtx_s cn66xx;\n+};\n+\n+typedef union cvmx_pip_xstat3_prtx cvmx_pip_xstat3_prtx_t;\n+\n+/**\n+ * cvmx_pip_xstat4_prt#\n+ *\n+ * PIP_XSTAT4_PRTX = PIP_XSTAT_HIST1    / PIP_XSTAT_HIST0\n+ *\n+ */\n+union cvmx_pip_xstat4_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_xstat4_prtx_s {\n+\t\tu64 h65to127 : 32;\n+\t\tu64 h64 : 32;\n+\t} s;\n+\tstruct cvmx_pip_xstat4_prtx_s cn63xx;\n+\tstruct cvmx_pip_xstat4_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_xstat4_prtx_s cn66xx;\n+};\n+\n+typedef union cvmx_pip_xstat4_prtx cvmx_pip_xstat4_prtx_t;\n+\n+/**\n+ * cvmx_pip_xstat5_prt#\n+ *\n+ * PIP_XSTAT5_PRTX = PIP_XSTAT_HIST3    / PIP_XSTAT_HIST2\n+ *\n+ */\n+union cvmx_pip_xstat5_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_xstat5_prtx_s {\n+\t\tu64 h256to511 : 32;\n+\t\tu64 h128to255 : 32;\n+\t} s;\n+\tstruct cvmx_pip_xstat5_prtx_s cn63xx;\n+\tstruct cvmx_pip_xstat5_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_xstat5_prtx_s cn66xx;\n+};\n+\n+typedef union cvmx_pip_xstat5_prtx cvmx_pip_xstat5_prtx_t;\n+\n+/**\n+ * cvmx_pip_xstat6_prt#\n+ *\n+ * PIP_XSTAT6_PRTX = PIP_XSTAT_HIST5    / PIP_XSTAT_HIST4\n+ *\n+ */\n+union cvmx_pip_xstat6_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_xstat6_prtx_s {\n+\t\tu64 h1024to1518 : 32;\n+\t\tu64 h512to1023 : 32;\n+\t} s;\n+\tstruct cvmx_pip_xstat6_prtx_s cn63xx;\n+\tstruct cvmx_pip_xstat6_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_xstat6_prtx_s cn66xx;\n+};\n+\n+typedef union cvmx_pip_xstat6_prtx cvmx_pip_xstat6_prtx_t;\n+\n+/**\n+ * cvmx_pip_xstat7_prt#\n+ *\n+ * PIP_XSTAT7_PRTX = PIP_XSTAT_FCS      / PIP_XSTAT_HIST6\n+ *\n+ *\n+ * Notes:\n+ * DPI does not check FCS, therefore FCS will never increment on DPI ports 32-35\n+ * sRIO does not check FCS, therefore FCS will never increment on sRIO ports 40-47\n+ */\n+union cvmx_pip_xstat7_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_xstat7_prtx_s {\n+\t\tu64 fcs : 32;\n+\t\tu64 h1519 : 32;\n+\t} s;\n+\tstruct cvmx_pip_xstat7_prtx_s cn63xx;\n+\tstruct cvmx_pip_xstat7_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_xstat7_prtx_s cn66xx;\n+};\n+\n+typedef union cvmx_pip_xstat7_prtx cvmx_pip_xstat7_prtx_t;\n+\n+/**\n+ * cvmx_pip_xstat8_prt#\n+ *\n+ * PIP_XSTAT8_PRTX = PIP_XSTAT_FRAG     / PIP_XSTAT_UNDER\n+ *\n+ *\n+ * Notes:\n+ * DPI does not check FCS, therefore FRAG will never increment on DPI ports 32-35\n+ * sRIO does not check FCS, therefore FRAG will never increment on sRIO ports 40-47\n+ */\n+union cvmx_pip_xstat8_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_xstat8_prtx_s {\n+\t\tu64 frag : 32;\n+\t\tu64 undersz : 32;\n+\t} s;\n+\tstruct cvmx_pip_xstat8_prtx_s cn63xx;\n+\tstruct cvmx_pip_xstat8_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_xstat8_prtx_s cn66xx;\n+};\n+\n+typedef union cvmx_pip_xstat8_prtx cvmx_pip_xstat8_prtx_t;\n+\n+/**\n+ * cvmx_pip_xstat9_prt#\n+ *\n+ * PIP_XSTAT9_PRTX = PIP_XSTAT_JABBER   / PIP_XSTAT_OVER\n+ *\n+ *\n+ * Notes:\n+ * DPI does not check FCS, therefore JABBER will never increment on DPI ports 32-35\n+ * sRIO does not check FCS, therefore JABBER will never increment on sRIO ports 40-47 due to FCS errors\n+ * sRIO does use the JABBER opcode to communicate sRIO error, therefore JABBER can increment under the sRIO error conditions\n+ */\n+union cvmx_pip_xstat9_prtx {\n+\tu64 u64;\n+\tstruct cvmx_pip_xstat9_prtx_s {\n+\t\tu64 jabber : 32;\n+\t\tu64 oversz : 32;\n+\t} s;\n+\tstruct cvmx_pip_xstat9_prtx_s cn63xx;\n+\tstruct cvmx_pip_xstat9_prtx_s cn63xxp1;\n+\tstruct cvmx_pip_xstat9_prtx_s cn66xx;\n+};\n+\n+typedef union cvmx_pip_xstat9_prtx cvmx_pip_xstat9_prtx_t;\n+\n+#endif\n",
    "prefixes": [
        "v1",
        "22/50"
    ]
}