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GET /api/patches/1415002/?format=api
{ "id": 1415002, "url": "http://patchwork.ozlabs.org/api/patches/1415002/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-26-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-26-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:47", "name": "[v1,25/50] mips: octeon: Add cvmx-pow-defs.h header file", "commit_ref": "f56633987c3b2333eb42ece5889d8161c290b203", "pull_url": null, "state": "accepted", "archived": false, "hash": "f35aeda789e9cf4917c7493655a09e77c57a241b", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-26-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1415002/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1415002/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=uhC4RkC0;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4CswlG3slTz9sSs\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:11:38 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id BE1948271D;\n\tFri, 11 Dec 2020 17:08:18 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 60F0A8279F; Fri, 11 Dec 2020 17:07:40 +0100 (CET)", "from mx2.mailbox.org (mx2a.mailbox.org\n [IPv6:2001:67c:2050:104:0:2:25:2])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 34C8B82673\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:26 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org\n [IPv6:2001:67c:2050:105:465:1:1:0])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id 5E666A0E58;\n Fri, 11 Dec 2020 17:06:25 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter05.heinlein-hosting.de (spamfilter05.heinlein-hosting.de\n [80.241.56.123]) (amavisd-new, port 10030)\n with ESMTP id YhleorWk8XlN; Fri, 11 Dec 2020 17:06:21 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702899;\n\tbh=ZxwuqGUloYf39ZtnfXUTnql0JNDLxQRYx1iFa77Ju5I=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=uhC4RkC07B/XUyfARuqSiLqXNo2Dke2b18MuYjx4brAFO0EzQYa0cg/wAFX2EC2To\n\t mNGBNfKc2R5+2uYIbpBh7xUTxvUsspW3nkmpPR/VVUYHp2i91WLmqy+e0vF5fXgZkL\n\t wnw07YANAv2a3FclXYCB18YWgv95wBTDvpb+9HxwmVJOkuAq0dWkc2vfOOCGhJF/dQ\n\t j7SdD7rim4lnCvwomenCL4/F6MlDl5JVDXbPBqMuIPWIzIPf2auQzZtCfLA5g9hoJT\n\t bDOpHryark1h1Mk4TQdHOgnZfg36Mh9LogdZvnDVxkfcs3VynDbtE3NoDQoZ/XljEz\n\t 0oN3Ouo+77lKw==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 25/50] mips: octeon: Add cvmx-pow-defs.h header file", "Date": "Fri, 11 Dec 2020 17:05:47 +0100", "Message-Id": "<20201211160612.1498780-26-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-0.73 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "4DE311870", "X-Rspamd-UID": "f231cd", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-pow-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-pow-defs.h | 1135 +++++++++++++++++\n 1 file changed, 1135 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pow-defs.h", "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pow-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-pow-defs.h\nnew file mode 100644\nindex 0000000000..92e3723eb3\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-pow-defs.h\n@@ -0,0 +1,1135 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon pow.\n+ */\n+\n+#ifndef __CVMX_POW_DEFS_H__\n+#define __CVMX_POW_DEFS_H__\n+\n+#define CVMX_POW_BIST_STAT\t (0x00016700000003F8ull)\n+#define CVMX_POW_DS_PC\t\t (0x0001670000000398ull)\n+#define CVMX_POW_ECC_ERR\t (0x0001670000000218ull)\n+#define CVMX_POW_IQ_CNTX(offset) (0x0001670000000340ull + ((offset) & 7) * 8)\n+#define CVMX_POW_IQ_COM_CNT\t (0x0001670000000388ull)\n+#define CVMX_POW_IQ_INT\t\t (0x0001670000000238ull)\n+#define CVMX_POW_IQ_INT_EN\t (0x0001670000000240ull)\n+#define CVMX_POW_IQ_THRX(offset) (0x00016700000003A0ull + ((offset) & 7) * 8)\n+#define CVMX_POW_NOS_CNT\t (0x0001670000000228ull)\n+#define CVMX_POW_NW_TIM\t\t (0x0001670000000210ull)\n+#define CVMX_POW_PF_RST_MSK\t (0x0001670000000230ull)\n+#define CVMX_POW_PP_GRP_MSKX(offset) (0x0001670000000000ull + ((offset) & 15) * 8)\n+#define CVMX_POW_QOS_RNDX(offset) (0x00016700000001C0ull + ((offset) & 7) * 8)\n+#define CVMX_POW_QOS_THRX(offset) (0x0001670000000180ull + ((offset) & 7) * 8)\n+#define CVMX_POW_TS_PC\t\t (0x0001670000000390ull)\n+#define CVMX_POW_WA_COM_PC\t (0x0001670000000380ull)\n+#define CVMX_POW_WA_PCX(offset)\t (0x0001670000000300ull + ((offset) & 7) * 8)\n+#define CVMX_POW_WQ_INT\t\t (0x0001670000000200ull)\n+#define CVMX_POW_WQ_INT_CNTX(offset) (0x0001670000000100ull + ((offset) & 15) * 8)\n+#define CVMX_POW_WQ_INT_PC\t (0x0001670000000208ull)\n+#define CVMX_POW_WQ_INT_THRX(offset) (0x0001670000000080ull + ((offset) & 15) * 8)\n+#define CVMX_POW_WS_PCX(offset)\t (0x0001670000000280ull + ((offset) & 15) * 8)\n+\n+/**\n+ * cvmx_pow_bist_stat\n+ *\n+ * Contains the BIST status for the POW memories ('0' = pass, '1' = fail).\n+ *\n+ */\n+union cvmx_pow_bist_stat {\n+\tu64 u64;\n+\tstruct cvmx_pow_bist_stat_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 pp : 16;\n+\t\tu64 reserved_0_15 : 16;\n+\t} s;\n+\tstruct cvmx_pow_bist_stat_cn30xx {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 pp : 1;\n+\t\tu64 reserved_9_15 : 7;\n+\t\tu64 cam : 1;\n+\t\tu64 nbt1 : 1;\n+\t\tu64 nbt0 : 1;\n+\t\tu64 index : 1;\n+\t\tu64 fidx : 1;\n+\t\tu64 nbr1 : 1;\n+\t\tu64 nbr0 : 1;\n+\t\tu64 pend : 1;\n+\t\tu64 adr : 1;\n+\t} cn30xx;\n+\tstruct cvmx_pow_bist_stat_cn31xx {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 pp : 2;\n+\t\tu64 reserved_9_15 : 7;\n+\t\tu64 cam : 1;\n+\t\tu64 nbt1 : 1;\n+\t\tu64 nbt0 : 1;\n+\t\tu64 index : 1;\n+\t\tu64 fidx : 1;\n+\t\tu64 nbr1 : 1;\n+\t\tu64 nbr0 : 1;\n+\t\tu64 pend : 1;\n+\t\tu64 adr : 1;\n+\t} cn31xx;\n+\tstruct cvmx_pow_bist_stat_cn38xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 pp : 16;\n+\t\tu64 reserved_10_15 : 6;\n+\t\tu64 cam : 1;\n+\t\tu64 nbt : 1;\n+\t\tu64 index : 1;\n+\t\tu64 fidx : 1;\n+\t\tu64 nbr1 : 1;\n+\t\tu64 nbr0 : 1;\n+\t\tu64 pend1 : 1;\n+\t\tu64 pend0 : 1;\n+\t\tu64 adr1 : 1;\n+\t\tu64 adr0 : 1;\n+\t} cn38xx;\n+\tstruct cvmx_pow_bist_stat_cn38xx cn38xxp2;\n+\tstruct cvmx_pow_bist_stat_cn31xx cn50xx;\n+\tstruct cvmx_pow_bist_stat_cn52xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 pp : 4;\n+\t\tu64 reserved_9_15 : 7;\n+\t\tu64 cam : 1;\n+\t\tu64 nbt1 : 1;\n+\t\tu64 nbt0 : 1;\n+\t\tu64 index : 1;\n+\t\tu64 fidx : 1;\n+\t\tu64 nbr1 : 1;\n+\t\tu64 nbr0 : 1;\n+\t\tu64 pend : 1;\n+\t\tu64 adr : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pow_bist_stat_cn52xx cn52xxp1;\n+\tstruct cvmx_pow_bist_stat_cn56xx {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 pp : 12;\n+\t\tu64 reserved_10_15 : 6;\n+\t\tu64 cam : 1;\n+\t\tu64 nbt : 1;\n+\t\tu64 index : 1;\n+\t\tu64 fidx : 1;\n+\t\tu64 nbr1 : 1;\n+\t\tu64 nbr0 : 1;\n+\t\tu64 pend1 : 1;\n+\t\tu64 pend0 : 1;\n+\t\tu64 adr1 : 1;\n+\t\tu64 adr0 : 1;\n+\t} cn56xx;\n+\tstruct cvmx_pow_bist_stat_cn56xx cn56xxp1;\n+\tstruct cvmx_pow_bist_stat_cn38xx cn58xx;\n+\tstruct cvmx_pow_bist_stat_cn38xx cn58xxp1;\n+\tstruct cvmx_pow_bist_stat_cn61xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 pp : 4;\n+\t\tu64 reserved_12_15 : 4;\n+\t\tu64 cam : 1;\n+\t\tu64 nbr : 3;\n+\t\tu64 nbt : 4;\n+\t\tu64 index : 1;\n+\t\tu64 fidx : 1;\n+\t\tu64 pend : 1;\n+\t\tu64 adr : 1;\n+\t} cn61xx;\n+\tstruct cvmx_pow_bist_stat_cn63xx {\n+\t\tu64 reserved_22_63 : 42;\n+\t\tu64 pp : 6;\n+\t\tu64 reserved_12_15 : 4;\n+\t\tu64 cam : 1;\n+\t\tu64 nbr : 3;\n+\t\tu64 nbt : 4;\n+\t\tu64 index : 1;\n+\t\tu64 fidx : 1;\n+\t\tu64 pend : 1;\n+\t\tu64 adr : 1;\n+\t} cn63xx;\n+\tstruct cvmx_pow_bist_stat_cn63xx cn63xxp1;\n+\tstruct cvmx_pow_bist_stat_cn66xx {\n+\t\tu64 reserved_26_63 : 38;\n+\t\tu64 pp : 10;\n+\t\tu64 reserved_12_15 : 4;\n+\t\tu64 cam : 1;\n+\t\tu64 nbr : 3;\n+\t\tu64 nbt : 4;\n+\t\tu64 index : 1;\n+\t\tu64 fidx : 1;\n+\t\tu64 pend : 1;\n+\t\tu64 adr : 1;\n+\t} cn66xx;\n+\tstruct cvmx_pow_bist_stat_cn70xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 cam : 1;\n+\t\tu64 reserved_10_10 : 1;\n+\t\tu64 nbr : 2;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 nbt : 2;\n+\t\tu64 index : 1;\n+\t\tu64 fidx : 1;\n+\t\tu64 pend : 1;\n+\t\tu64 adr : 1;\n+\t} cn70xx;\n+\tstruct cvmx_pow_bist_stat_cn70xx cn70xxp1;\n+\tstruct cvmx_pow_bist_stat_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_pow_bist_stat cvmx_pow_bist_stat_t;\n+\n+/**\n+ * cvmx_pow_ds_pc\n+ *\n+ * Counts the number of de-schedule requests. Write to clear.\n+ *\n+ */\n+union cvmx_pow_ds_pc {\n+\tu64 u64;\n+\tstruct cvmx_pow_ds_pc_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 ds_pc : 32;\n+\t} s;\n+\tstruct cvmx_pow_ds_pc_s cn30xx;\n+\tstruct cvmx_pow_ds_pc_s cn31xx;\n+\tstruct cvmx_pow_ds_pc_s cn38xx;\n+\tstruct cvmx_pow_ds_pc_s cn38xxp2;\n+\tstruct cvmx_pow_ds_pc_s cn50xx;\n+\tstruct cvmx_pow_ds_pc_s cn52xx;\n+\tstruct cvmx_pow_ds_pc_s cn52xxp1;\n+\tstruct cvmx_pow_ds_pc_s cn56xx;\n+\tstruct cvmx_pow_ds_pc_s cn56xxp1;\n+\tstruct cvmx_pow_ds_pc_s cn58xx;\n+\tstruct cvmx_pow_ds_pc_s cn58xxp1;\n+\tstruct cvmx_pow_ds_pc_s cn61xx;\n+\tstruct cvmx_pow_ds_pc_s cn63xx;\n+\tstruct cvmx_pow_ds_pc_s cn63xxp1;\n+\tstruct cvmx_pow_ds_pc_s cn66xx;\n+\tstruct cvmx_pow_ds_pc_s cn70xx;\n+\tstruct cvmx_pow_ds_pc_s cn70xxp1;\n+\tstruct cvmx_pow_ds_pc_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_ds_pc cvmx_pow_ds_pc_t;\n+\n+/**\n+ * cvmx_pow_ecc_err\n+ *\n+ * Contains the single and double error bits and the corresponding interrupt enables for the ECC-\n+ * protected POW index memory. Also contains the syndrome value in the event of an ECC error.\n+ * Also contains the remote pointer error bit and interrupt enable. RPE is set when the POW\n+ * detected\n+ * corruption on one or more of the input queue lists in L2/DRAM (POW's local copy of the tail\n+ * pointer\n+ * for the L2/DRAM input queue did not match the last entry on the the list). This is caused by\n+ * L2/DRAM corruption, and is generally a fatal error because it likely caused POW to load bad\n+ * work\n+ * queue entries.\n+ * This register also contains the illegal operation error bits and the corresponding interrupt\n+ * enables as follows:\n+ * <0> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state\n+ * <1> Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state\n+ * <2> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED\n+ * or ATOMIC\n+ * <3> Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL\n+ * <4> Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL\n+ * <5> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with\n+ * GET_WORK pending\n+ * <6> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD\n+ * pending\n+ * <7> Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending\n+ * <8> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with\n+ * CLR_NSCHED pending\n+ * <9> Received illegal opcode\n+ * <10> Received ADD_WORK with tag specified as NULL_NULL\n+ * <11> Received DBG load from PP with DBG load pending\n+ * <12> Received CSR load from PP with CSR load pending\n+ */\n+union cvmx_pow_ecc_err {\n+\tu64 u64;\n+\tstruct cvmx_pow_ecc_err_s {\n+\t\tu64 reserved_45_63 : 19;\n+\t\tu64 iop_ie : 13;\n+\t\tu64 reserved_29_31 : 3;\n+\t\tu64 iop : 13;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 rpe_ie : 1;\n+\t\tu64 rpe : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 syn : 5;\n+\t\tu64 dbe_ie : 1;\n+\t\tu64 sbe_ie : 1;\n+\t\tu64 dbe : 1;\n+\t\tu64 sbe : 1;\n+\t} s;\n+\tstruct cvmx_pow_ecc_err_s cn30xx;\n+\tstruct cvmx_pow_ecc_err_cn31xx {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 rpe_ie : 1;\n+\t\tu64 rpe : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 syn : 5;\n+\t\tu64 dbe_ie : 1;\n+\t\tu64 sbe_ie : 1;\n+\t\tu64 dbe : 1;\n+\t\tu64 sbe : 1;\n+\t} cn31xx;\n+\tstruct cvmx_pow_ecc_err_s cn38xx;\n+\tstruct cvmx_pow_ecc_err_cn31xx cn38xxp2;\n+\tstruct cvmx_pow_ecc_err_s cn50xx;\n+\tstruct cvmx_pow_ecc_err_s cn52xx;\n+\tstruct cvmx_pow_ecc_err_s cn52xxp1;\n+\tstruct cvmx_pow_ecc_err_s cn56xx;\n+\tstruct cvmx_pow_ecc_err_s cn56xxp1;\n+\tstruct cvmx_pow_ecc_err_s cn58xx;\n+\tstruct cvmx_pow_ecc_err_s cn58xxp1;\n+\tstruct cvmx_pow_ecc_err_s cn61xx;\n+\tstruct cvmx_pow_ecc_err_s cn63xx;\n+\tstruct cvmx_pow_ecc_err_s cn63xxp1;\n+\tstruct cvmx_pow_ecc_err_s cn66xx;\n+\tstruct cvmx_pow_ecc_err_s cn70xx;\n+\tstruct cvmx_pow_ecc_err_s cn70xxp1;\n+\tstruct cvmx_pow_ecc_err_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_ecc_err cvmx_pow_ecc_err_t;\n+\n+/**\n+ * cvmx_pow_iq_cnt#\n+ *\n+ * Contains a read-only count of the number of work queue entries for each QOS level.\n+ *\n+ */\n+union cvmx_pow_iq_cntx {\n+\tu64 u64;\n+\tstruct cvmx_pow_iq_cntx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 iq_cnt : 32;\n+\t} s;\n+\tstruct cvmx_pow_iq_cntx_s cn30xx;\n+\tstruct cvmx_pow_iq_cntx_s cn31xx;\n+\tstruct cvmx_pow_iq_cntx_s cn38xx;\n+\tstruct cvmx_pow_iq_cntx_s cn38xxp2;\n+\tstruct cvmx_pow_iq_cntx_s cn50xx;\n+\tstruct cvmx_pow_iq_cntx_s cn52xx;\n+\tstruct cvmx_pow_iq_cntx_s cn52xxp1;\n+\tstruct cvmx_pow_iq_cntx_s cn56xx;\n+\tstruct cvmx_pow_iq_cntx_s cn56xxp1;\n+\tstruct cvmx_pow_iq_cntx_s cn58xx;\n+\tstruct cvmx_pow_iq_cntx_s cn58xxp1;\n+\tstruct cvmx_pow_iq_cntx_s cn61xx;\n+\tstruct cvmx_pow_iq_cntx_s cn63xx;\n+\tstruct cvmx_pow_iq_cntx_s cn63xxp1;\n+\tstruct cvmx_pow_iq_cntx_s cn66xx;\n+\tstruct cvmx_pow_iq_cntx_s cn70xx;\n+\tstruct cvmx_pow_iq_cntx_s cn70xxp1;\n+\tstruct cvmx_pow_iq_cntx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_iq_cntx cvmx_pow_iq_cntx_t;\n+\n+/**\n+ * cvmx_pow_iq_com_cnt\n+ *\n+ * Contains a read-only count of the total number of work queue entries in all QOS levels.\n+ *\n+ */\n+union cvmx_pow_iq_com_cnt {\n+\tu64 u64;\n+\tstruct cvmx_pow_iq_com_cnt_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 iq_cnt : 32;\n+\t} s;\n+\tstruct cvmx_pow_iq_com_cnt_s cn30xx;\n+\tstruct cvmx_pow_iq_com_cnt_s cn31xx;\n+\tstruct cvmx_pow_iq_com_cnt_s cn38xx;\n+\tstruct cvmx_pow_iq_com_cnt_s cn38xxp2;\n+\tstruct cvmx_pow_iq_com_cnt_s cn50xx;\n+\tstruct cvmx_pow_iq_com_cnt_s cn52xx;\n+\tstruct cvmx_pow_iq_com_cnt_s cn52xxp1;\n+\tstruct cvmx_pow_iq_com_cnt_s cn56xx;\n+\tstruct cvmx_pow_iq_com_cnt_s cn56xxp1;\n+\tstruct cvmx_pow_iq_com_cnt_s cn58xx;\n+\tstruct cvmx_pow_iq_com_cnt_s cn58xxp1;\n+\tstruct cvmx_pow_iq_com_cnt_s cn61xx;\n+\tstruct cvmx_pow_iq_com_cnt_s cn63xx;\n+\tstruct cvmx_pow_iq_com_cnt_s cn63xxp1;\n+\tstruct cvmx_pow_iq_com_cnt_s cn66xx;\n+\tstruct cvmx_pow_iq_com_cnt_s cn70xx;\n+\tstruct cvmx_pow_iq_com_cnt_s cn70xxp1;\n+\tstruct cvmx_pow_iq_com_cnt_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_iq_com_cnt cvmx_pow_iq_com_cnt_t;\n+\n+/**\n+ * cvmx_pow_iq_int\n+ *\n+ * \"Contains the bits (1 per QOS level) that can trigger the input queue interrupt. An IQ_INT\n+ * bit\n+ * will be set if POW_IQ_CNT#QOS# changes and the resulting value is equal to POW_IQ_THR#QOS#.\"\n+ */\n+union cvmx_pow_iq_int {\n+\tu64 u64;\n+\tstruct cvmx_pow_iq_int_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 iq_int : 8;\n+\t} s;\n+\tstruct cvmx_pow_iq_int_s cn52xx;\n+\tstruct cvmx_pow_iq_int_s cn52xxp1;\n+\tstruct cvmx_pow_iq_int_s cn56xx;\n+\tstruct cvmx_pow_iq_int_s cn56xxp1;\n+\tstruct cvmx_pow_iq_int_s cn61xx;\n+\tstruct cvmx_pow_iq_int_s cn63xx;\n+\tstruct cvmx_pow_iq_int_s cn63xxp1;\n+\tstruct cvmx_pow_iq_int_s cn66xx;\n+\tstruct cvmx_pow_iq_int_s cn70xx;\n+\tstruct cvmx_pow_iq_int_s cn70xxp1;\n+\tstruct cvmx_pow_iq_int_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_iq_int cvmx_pow_iq_int_t;\n+\n+/**\n+ * cvmx_pow_iq_int_en\n+ *\n+ * Contains the bits (1 per QOS level) that enable the input queue interrupt.\n+ *\n+ */\n+union cvmx_pow_iq_int_en {\n+\tu64 u64;\n+\tstruct cvmx_pow_iq_int_en_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 int_en : 8;\n+\t} s;\n+\tstruct cvmx_pow_iq_int_en_s cn52xx;\n+\tstruct cvmx_pow_iq_int_en_s cn52xxp1;\n+\tstruct cvmx_pow_iq_int_en_s cn56xx;\n+\tstruct cvmx_pow_iq_int_en_s cn56xxp1;\n+\tstruct cvmx_pow_iq_int_en_s cn61xx;\n+\tstruct cvmx_pow_iq_int_en_s cn63xx;\n+\tstruct cvmx_pow_iq_int_en_s cn63xxp1;\n+\tstruct cvmx_pow_iq_int_en_s cn66xx;\n+\tstruct cvmx_pow_iq_int_en_s cn70xx;\n+\tstruct cvmx_pow_iq_int_en_s cn70xxp1;\n+\tstruct cvmx_pow_iq_int_en_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_iq_int_en cvmx_pow_iq_int_en_t;\n+\n+/**\n+ * cvmx_pow_iq_thr#\n+ *\n+ * Threshold value for triggering input queue interrupts.\n+ *\n+ */\n+union cvmx_pow_iq_thrx {\n+\tu64 u64;\n+\tstruct cvmx_pow_iq_thrx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 iq_thr : 32;\n+\t} s;\n+\tstruct cvmx_pow_iq_thrx_s cn52xx;\n+\tstruct cvmx_pow_iq_thrx_s cn52xxp1;\n+\tstruct cvmx_pow_iq_thrx_s cn56xx;\n+\tstruct cvmx_pow_iq_thrx_s cn56xxp1;\n+\tstruct cvmx_pow_iq_thrx_s cn61xx;\n+\tstruct cvmx_pow_iq_thrx_s cn63xx;\n+\tstruct cvmx_pow_iq_thrx_s cn63xxp1;\n+\tstruct cvmx_pow_iq_thrx_s cn66xx;\n+\tstruct cvmx_pow_iq_thrx_s cn70xx;\n+\tstruct cvmx_pow_iq_thrx_s cn70xxp1;\n+\tstruct cvmx_pow_iq_thrx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_iq_thrx cvmx_pow_iq_thrx_t;\n+\n+/**\n+ * cvmx_pow_nos_cnt\n+ *\n+ * Contains the number of work queue entries on the no-schedule list.\n+ *\n+ */\n+union cvmx_pow_nos_cnt {\n+\tu64 u64;\n+\tstruct cvmx_pow_nos_cnt_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 nos_cnt : 12;\n+\t} s;\n+\tstruct cvmx_pow_nos_cnt_cn30xx {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 nos_cnt : 7;\n+\t} cn30xx;\n+\tstruct cvmx_pow_nos_cnt_cn31xx {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 nos_cnt : 9;\n+\t} cn31xx;\n+\tstruct cvmx_pow_nos_cnt_s cn38xx;\n+\tstruct cvmx_pow_nos_cnt_s cn38xxp2;\n+\tstruct cvmx_pow_nos_cnt_cn31xx cn50xx;\n+\tstruct cvmx_pow_nos_cnt_cn52xx {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 nos_cnt : 10;\n+\t} cn52xx;\n+\tstruct cvmx_pow_nos_cnt_cn52xx cn52xxp1;\n+\tstruct cvmx_pow_nos_cnt_s cn56xx;\n+\tstruct cvmx_pow_nos_cnt_s cn56xxp1;\n+\tstruct cvmx_pow_nos_cnt_s cn58xx;\n+\tstruct cvmx_pow_nos_cnt_s cn58xxp1;\n+\tstruct cvmx_pow_nos_cnt_cn52xx cn61xx;\n+\tstruct cvmx_pow_nos_cnt_cn63xx {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 nos_cnt : 11;\n+\t} cn63xx;\n+\tstruct cvmx_pow_nos_cnt_cn63xx cn63xxp1;\n+\tstruct cvmx_pow_nos_cnt_cn63xx cn66xx;\n+\tstruct cvmx_pow_nos_cnt_cn52xx cn70xx;\n+\tstruct cvmx_pow_nos_cnt_cn52xx cn70xxp1;\n+\tstruct cvmx_pow_nos_cnt_cn52xx cnf71xx;\n+};\n+\n+typedef union cvmx_pow_nos_cnt cvmx_pow_nos_cnt_t;\n+\n+/**\n+ * cvmx_pow_nw_tim\n+ *\n+ * Sets the minimum period for a new work request timeout. Period is specified in n-1 notation\n+ * where the increment value is 1024 clock cycles. Thus, a value of 0x0 in this register\n+ * translates\n+ * to 1024 cycles, 0x1 translates to 2048 cycles, 0x2 translates to 3072 cycles, etc... Note:\n+ * the\n+ * maximum period for a new work request timeout is 2 times the minimum period. Note: the new\n+ * work\n+ * request timeout counter is reset when this register is written.\n+ * There are two new work request timeout cases:\n+ * - WAIT bit clear. The new work request can timeout if the timer expires before the pre-fetch\n+ * engine has reached the end of all work queues. This can occur if the executable work queue\n+ * entry is deep in the queue and the pre-fetch engine is subject to many resets (i.e. high\n+ * switch,\n+ * de-schedule, or new work load from other PP's). Thus, it is possible for a PP to receive a\n+ * work\n+ * response with the NO_WORK bit set even though there was at least one executable entry in the\n+ * work queues. The other (and typical) scenario for receiving a NO_WORK response with the\n+ * WAIT\n+ * bit clear is that the pre-fetch engine has reached the end of all work queues without\n+ * finding\n+ * executable work.\n+ * - WAIT bit set. The new work request can timeout if the timer expires before the pre-fetch\n+ * engine has found executable work. In this case, the only scenario where the PP will receive\n+ * a\n+ * work response with the NO_WORK bit set is if the timer expires. Note: it is still possible\n+ * for\n+ * a PP to receive a NO_WORK response even though there was at least one executable entry in\n+ * the\n+ * work queues.\n+ * In either case, it's important to note that switches and de-schedules are higher priority\n+ * operations that can cause the pre-fetch engine to reset. Thus in a system with many switches\n+ * or\n+ * de-schedules occurring, it's possible for the new work timer to expire (resulting in NO_WORK\n+ * responses) before the pre-fetch engine is able to get very deep into the work queues.\n+ */\n+union cvmx_pow_nw_tim {\n+\tu64 u64;\n+\tstruct cvmx_pow_nw_tim_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 nw_tim : 10;\n+\t} s;\n+\tstruct cvmx_pow_nw_tim_s cn30xx;\n+\tstruct cvmx_pow_nw_tim_s cn31xx;\n+\tstruct cvmx_pow_nw_tim_s cn38xx;\n+\tstruct cvmx_pow_nw_tim_s cn38xxp2;\n+\tstruct cvmx_pow_nw_tim_s cn50xx;\n+\tstruct cvmx_pow_nw_tim_s cn52xx;\n+\tstruct cvmx_pow_nw_tim_s cn52xxp1;\n+\tstruct cvmx_pow_nw_tim_s cn56xx;\n+\tstruct cvmx_pow_nw_tim_s cn56xxp1;\n+\tstruct cvmx_pow_nw_tim_s cn58xx;\n+\tstruct cvmx_pow_nw_tim_s cn58xxp1;\n+\tstruct cvmx_pow_nw_tim_s cn61xx;\n+\tstruct cvmx_pow_nw_tim_s cn63xx;\n+\tstruct cvmx_pow_nw_tim_s cn63xxp1;\n+\tstruct cvmx_pow_nw_tim_s cn66xx;\n+\tstruct cvmx_pow_nw_tim_s cn70xx;\n+\tstruct cvmx_pow_nw_tim_s cn70xxp1;\n+\tstruct cvmx_pow_nw_tim_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_nw_tim cvmx_pow_nw_tim_t;\n+\n+/**\n+ * cvmx_pow_pf_rst_msk\n+ *\n+ * Resets the work prefetch engine when work is stored in an internal buffer (either when the add\n+ * work arrives or when the work is reloaded from an external buffer) for an enabled QOS level\n+ * (1 bit per QOS level).\n+ */\n+union cvmx_pow_pf_rst_msk {\n+\tu64 u64;\n+\tstruct cvmx_pow_pf_rst_msk_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 rst_msk : 8;\n+\t} s;\n+\tstruct cvmx_pow_pf_rst_msk_s cn50xx;\n+\tstruct cvmx_pow_pf_rst_msk_s cn52xx;\n+\tstruct cvmx_pow_pf_rst_msk_s cn52xxp1;\n+\tstruct cvmx_pow_pf_rst_msk_s cn56xx;\n+\tstruct cvmx_pow_pf_rst_msk_s cn56xxp1;\n+\tstruct cvmx_pow_pf_rst_msk_s cn58xx;\n+\tstruct cvmx_pow_pf_rst_msk_s cn58xxp1;\n+\tstruct cvmx_pow_pf_rst_msk_s cn61xx;\n+\tstruct cvmx_pow_pf_rst_msk_s cn63xx;\n+\tstruct cvmx_pow_pf_rst_msk_s cn63xxp1;\n+\tstruct cvmx_pow_pf_rst_msk_s cn66xx;\n+\tstruct cvmx_pow_pf_rst_msk_s cn70xx;\n+\tstruct cvmx_pow_pf_rst_msk_s cn70xxp1;\n+\tstruct cvmx_pow_pf_rst_msk_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_pf_rst_msk cvmx_pow_pf_rst_msk_t;\n+\n+/**\n+ * cvmx_pow_pp_grp_msk#\n+ *\n+ * Selects which group(s) a PP belongs to. A '1' in any bit position sets the PP's membership in\n+ * the corresponding group. A value of 0x0 will prevent the PP from receiving new work. Note:\n+ * disabled or non-existent PP's should have this field set to 0xffff (the reset value) in order\n+ * to\n+ * maximize POW performance.\n+ * Also contains the QOS level priorities for each PP. 0x0 is highest priority, and 0x7 the\n+ * lowest.\n+ * Setting the priority to 0xf will prevent that PP from receiving work from that QOS level.\n+ * Priority values 0x8 through 0xe are reserved and should not be used. For a given PP,\n+ * priorities\n+ * should begin at 0x0 and remain contiguous throughout the range.\n+ */\n+union cvmx_pow_pp_grp_mskx {\n+\tu64 u64;\n+\tstruct cvmx_pow_pp_grp_mskx_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 qos7_pri : 4;\n+\t\tu64 qos6_pri : 4;\n+\t\tu64 qos5_pri : 4;\n+\t\tu64 qos4_pri : 4;\n+\t\tu64 qos3_pri : 4;\n+\t\tu64 qos2_pri : 4;\n+\t\tu64 qos1_pri : 4;\n+\t\tu64 qos0_pri : 4;\n+\t\tu64 grp_msk : 16;\n+\t} s;\n+\tstruct cvmx_pow_pp_grp_mskx_cn30xx {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 grp_msk : 16;\n+\t} cn30xx;\n+\tstruct cvmx_pow_pp_grp_mskx_cn30xx cn31xx;\n+\tstruct cvmx_pow_pp_grp_mskx_cn30xx cn38xx;\n+\tstruct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2;\n+\tstruct cvmx_pow_pp_grp_mskx_s cn50xx;\n+\tstruct cvmx_pow_pp_grp_mskx_s cn52xx;\n+\tstruct cvmx_pow_pp_grp_mskx_s cn52xxp1;\n+\tstruct cvmx_pow_pp_grp_mskx_s cn56xx;\n+\tstruct cvmx_pow_pp_grp_mskx_s cn56xxp1;\n+\tstruct cvmx_pow_pp_grp_mskx_s cn58xx;\n+\tstruct cvmx_pow_pp_grp_mskx_s cn58xxp1;\n+\tstruct cvmx_pow_pp_grp_mskx_s cn61xx;\n+\tstruct cvmx_pow_pp_grp_mskx_s cn63xx;\n+\tstruct cvmx_pow_pp_grp_mskx_s cn63xxp1;\n+\tstruct cvmx_pow_pp_grp_mskx_s cn66xx;\n+\tstruct cvmx_pow_pp_grp_mskx_s cn70xx;\n+\tstruct cvmx_pow_pp_grp_mskx_s cn70xxp1;\n+\tstruct cvmx_pow_pp_grp_mskx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_pp_grp_mskx cvmx_pow_pp_grp_mskx_t;\n+\n+/**\n+ * cvmx_pow_qos_rnd#\n+ *\n+ * Contains the round definitions for issuing new work. Each round consists of 8 bits with each\n+ * bit\n+ * corresponding to a QOS level. There are 4 rounds contained in each register for a total of 32\n+ * rounds. The issue logic traverses through the rounds sequentially (lowest round to highest\n+ * round)\n+ * in an attempt to find new work for each PP. Within each round, the issue logic traverses\n+ * through\n+ * the QOS levels sequentially (highest QOS to lowest QOS) skipping over each QOS level with a\n+ * clear\n+ * bit in the round mask. Note: setting a QOS level to all zeroes in all issue round registers\n+ * will\n+ * prevent work from being issued from that QOS level.\n+ */\n+union cvmx_pow_qos_rndx {\n+\tu64 u64;\n+\tstruct cvmx_pow_qos_rndx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 rnd_p3 : 8;\n+\t\tu64 rnd_p2 : 8;\n+\t\tu64 rnd_p1 : 8;\n+\t\tu64 rnd : 8;\n+\t} s;\n+\tstruct cvmx_pow_qos_rndx_s cn30xx;\n+\tstruct cvmx_pow_qos_rndx_s cn31xx;\n+\tstruct cvmx_pow_qos_rndx_s cn38xx;\n+\tstruct cvmx_pow_qos_rndx_s cn38xxp2;\n+\tstruct cvmx_pow_qos_rndx_s cn50xx;\n+\tstruct cvmx_pow_qos_rndx_s cn52xx;\n+\tstruct cvmx_pow_qos_rndx_s cn52xxp1;\n+\tstruct cvmx_pow_qos_rndx_s cn56xx;\n+\tstruct cvmx_pow_qos_rndx_s cn56xxp1;\n+\tstruct cvmx_pow_qos_rndx_s cn58xx;\n+\tstruct cvmx_pow_qos_rndx_s cn58xxp1;\n+\tstruct cvmx_pow_qos_rndx_s cn61xx;\n+\tstruct cvmx_pow_qos_rndx_s cn63xx;\n+\tstruct cvmx_pow_qos_rndx_s cn63xxp1;\n+\tstruct cvmx_pow_qos_rndx_s cn66xx;\n+\tstruct cvmx_pow_qos_rndx_s cn70xx;\n+\tstruct cvmx_pow_qos_rndx_s cn70xxp1;\n+\tstruct cvmx_pow_qos_rndx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_qos_rndx cvmx_pow_qos_rndx_t;\n+\n+/**\n+ * cvmx_pow_qos_thr#\n+ *\n+ * Contains the thresholds for allocating POW internal storage buffers. If the number of\n+ * remaining\n+ * free buffers drops below the minimum threshold (MIN_THR) or the number of allocated buffers\n+ * for\n+ * this QOS level rises above the maximum threshold (MAX_THR), future incoming work queue entries\n+ * will be buffered externally rather than internally. This register also contains a read-only\n+ * count\n+ * of the current number of free buffers (FREE_CNT), the number of internal buffers currently\n+ * allocated to this QOS level (BUF_CNT), and the total number of buffers on the de-schedule list\n+ * (DES_CNT) (which is not the same as the total number of de-scheduled buffers).\n+ */\n+union cvmx_pow_qos_thrx {\n+\tu64 u64;\n+\tstruct cvmx_pow_qos_thrx_s {\n+\t\tu64 reserved_60_63 : 4;\n+\t\tu64 des_cnt : 12;\n+\t\tu64 buf_cnt : 12;\n+\t\tu64 free_cnt : 12;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 max_thr : 11;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 min_thr : 11;\n+\t} s;\n+\tstruct cvmx_pow_qos_thrx_cn30xx {\n+\t\tu64 reserved_55_63 : 9;\n+\t\tu64 des_cnt : 7;\n+\t\tu64 reserved_43_47 : 5;\n+\t\tu64 buf_cnt : 7;\n+\t\tu64 reserved_31_35 : 5;\n+\t\tu64 free_cnt : 7;\n+\t\tu64 reserved_18_23 : 6;\n+\t\tu64 max_thr : 6;\n+\t\tu64 reserved_6_11 : 6;\n+\t\tu64 min_thr : 6;\n+\t} cn30xx;\n+\tstruct cvmx_pow_qos_thrx_cn31xx {\n+\t\tu64 reserved_57_63 : 7;\n+\t\tu64 des_cnt : 9;\n+\t\tu64 reserved_45_47 : 3;\n+\t\tu64 buf_cnt : 9;\n+\t\tu64 reserved_33_35 : 3;\n+\t\tu64 free_cnt : 9;\n+\t\tu64 reserved_20_23 : 4;\n+\t\tu64 max_thr : 8;\n+\t\tu64 reserved_8_11 : 4;\n+\t\tu64 min_thr : 8;\n+\t} cn31xx;\n+\tstruct cvmx_pow_qos_thrx_s cn38xx;\n+\tstruct cvmx_pow_qos_thrx_s cn38xxp2;\n+\tstruct cvmx_pow_qos_thrx_cn31xx cn50xx;\n+\tstruct cvmx_pow_qos_thrx_cn52xx {\n+\t\tu64 reserved_58_63 : 6;\n+\t\tu64 des_cnt : 10;\n+\t\tu64 reserved_46_47 : 2;\n+\t\tu64 buf_cnt : 10;\n+\t\tu64 reserved_34_35 : 2;\n+\t\tu64 free_cnt : 10;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 max_thr : 9;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 min_thr : 9;\n+\t} cn52xx;\n+\tstruct cvmx_pow_qos_thrx_cn52xx cn52xxp1;\n+\tstruct cvmx_pow_qos_thrx_s cn56xx;\n+\tstruct cvmx_pow_qos_thrx_s cn56xxp1;\n+\tstruct cvmx_pow_qos_thrx_s cn58xx;\n+\tstruct cvmx_pow_qos_thrx_s cn58xxp1;\n+\tstruct cvmx_pow_qos_thrx_cn52xx cn61xx;\n+\tstruct cvmx_pow_qos_thrx_cn63xx {\n+\t\tu64 reserved_59_63 : 5;\n+\t\tu64 des_cnt : 11;\n+\t\tu64 reserved_47_47 : 1;\n+\t\tu64 buf_cnt : 11;\n+\t\tu64 reserved_35_35 : 1;\n+\t\tu64 free_cnt : 11;\n+\t\tu64 reserved_22_23 : 2;\n+\t\tu64 max_thr : 10;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tu64 min_thr : 10;\n+\t} cn63xx;\n+\tstruct cvmx_pow_qos_thrx_cn63xx cn63xxp1;\n+\tstruct cvmx_pow_qos_thrx_cn63xx cn66xx;\n+\tstruct cvmx_pow_qos_thrx_cn52xx cn70xx;\n+\tstruct cvmx_pow_qos_thrx_cn52xx cn70xxp1;\n+\tstruct cvmx_pow_qos_thrx_cn52xx cnf71xx;\n+};\n+\n+typedef union cvmx_pow_qos_thrx cvmx_pow_qos_thrx_t;\n+\n+/**\n+ * cvmx_pow_ts_pc\n+ *\n+ * Counts the number of tag switch requests. Write to clear.\n+ *\n+ */\n+union cvmx_pow_ts_pc {\n+\tu64 u64;\n+\tstruct cvmx_pow_ts_pc_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 ts_pc : 32;\n+\t} s;\n+\tstruct cvmx_pow_ts_pc_s cn30xx;\n+\tstruct cvmx_pow_ts_pc_s cn31xx;\n+\tstruct cvmx_pow_ts_pc_s cn38xx;\n+\tstruct cvmx_pow_ts_pc_s cn38xxp2;\n+\tstruct cvmx_pow_ts_pc_s cn50xx;\n+\tstruct cvmx_pow_ts_pc_s cn52xx;\n+\tstruct cvmx_pow_ts_pc_s cn52xxp1;\n+\tstruct cvmx_pow_ts_pc_s cn56xx;\n+\tstruct cvmx_pow_ts_pc_s cn56xxp1;\n+\tstruct cvmx_pow_ts_pc_s cn58xx;\n+\tstruct cvmx_pow_ts_pc_s cn58xxp1;\n+\tstruct cvmx_pow_ts_pc_s cn61xx;\n+\tstruct cvmx_pow_ts_pc_s cn63xx;\n+\tstruct cvmx_pow_ts_pc_s cn63xxp1;\n+\tstruct cvmx_pow_ts_pc_s cn66xx;\n+\tstruct cvmx_pow_ts_pc_s cn70xx;\n+\tstruct cvmx_pow_ts_pc_s cn70xxp1;\n+\tstruct cvmx_pow_ts_pc_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_ts_pc cvmx_pow_ts_pc_t;\n+\n+/**\n+ * cvmx_pow_wa_com_pc\n+ *\n+ * Counts the number of add new work requests for all QOS levels. Write to clear.\n+ *\n+ */\n+union cvmx_pow_wa_com_pc {\n+\tu64 u64;\n+\tstruct cvmx_pow_wa_com_pc_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 wa_pc : 32;\n+\t} s;\n+\tstruct cvmx_pow_wa_com_pc_s cn30xx;\n+\tstruct cvmx_pow_wa_com_pc_s cn31xx;\n+\tstruct cvmx_pow_wa_com_pc_s cn38xx;\n+\tstruct cvmx_pow_wa_com_pc_s cn38xxp2;\n+\tstruct cvmx_pow_wa_com_pc_s cn50xx;\n+\tstruct cvmx_pow_wa_com_pc_s cn52xx;\n+\tstruct cvmx_pow_wa_com_pc_s cn52xxp1;\n+\tstruct cvmx_pow_wa_com_pc_s cn56xx;\n+\tstruct cvmx_pow_wa_com_pc_s cn56xxp1;\n+\tstruct cvmx_pow_wa_com_pc_s cn58xx;\n+\tstruct cvmx_pow_wa_com_pc_s cn58xxp1;\n+\tstruct cvmx_pow_wa_com_pc_s cn61xx;\n+\tstruct cvmx_pow_wa_com_pc_s cn63xx;\n+\tstruct cvmx_pow_wa_com_pc_s cn63xxp1;\n+\tstruct cvmx_pow_wa_com_pc_s cn66xx;\n+\tstruct cvmx_pow_wa_com_pc_s cn70xx;\n+\tstruct cvmx_pow_wa_com_pc_s cn70xxp1;\n+\tstruct cvmx_pow_wa_com_pc_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_wa_com_pc cvmx_pow_wa_com_pc_t;\n+\n+/**\n+ * cvmx_pow_wa_pc#\n+ *\n+ * Counts the number of add new work requests for each QOS level. Write to clear.\n+ *\n+ */\n+union cvmx_pow_wa_pcx {\n+\tu64 u64;\n+\tstruct cvmx_pow_wa_pcx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 wa_pc : 32;\n+\t} s;\n+\tstruct cvmx_pow_wa_pcx_s cn30xx;\n+\tstruct cvmx_pow_wa_pcx_s cn31xx;\n+\tstruct cvmx_pow_wa_pcx_s cn38xx;\n+\tstruct cvmx_pow_wa_pcx_s cn38xxp2;\n+\tstruct cvmx_pow_wa_pcx_s cn50xx;\n+\tstruct cvmx_pow_wa_pcx_s cn52xx;\n+\tstruct cvmx_pow_wa_pcx_s cn52xxp1;\n+\tstruct cvmx_pow_wa_pcx_s cn56xx;\n+\tstruct cvmx_pow_wa_pcx_s cn56xxp1;\n+\tstruct cvmx_pow_wa_pcx_s cn58xx;\n+\tstruct cvmx_pow_wa_pcx_s cn58xxp1;\n+\tstruct cvmx_pow_wa_pcx_s cn61xx;\n+\tstruct cvmx_pow_wa_pcx_s cn63xx;\n+\tstruct cvmx_pow_wa_pcx_s cn63xxp1;\n+\tstruct cvmx_pow_wa_pcx_s cn66xx;\n+\tstruct cvmx_pow_wa_pcx_s cn70xx;\n+\tstruct cvmx_pow_wa_pcx_s cn70xxp1;\n+\tstruct cvmx_pow_wa_pcx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_wa_pcx cvmx_pow_wa_pcx_t;\n+\n+/**\n+ * cvmx_pow_wq_int\n+ *\n+ * Contains the bits (1 per group) that set work queue interrupts and are used to clear these\n+ * interrupts. Also contains the input queue interrupt temporary disable bits (1 per group). For\n+ * more information regarding this register, see the interrupt section.\n+ */\n+union cvmx_pow_wq_int {\n+\tu64 u64;\n+\tstruct cvmx_pow_wq_int_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 iq_dis : 16;\n+\t\tu64 wq_int : 16;\n+\t} s;\n+\tstruct cvmx_pow_wq_int_s cn30xx;\n+\tstruct cvmx_pow_wq_int_s cn31xx;\n+\tstruct cvmx_pow_wq_int_s cn38xx;\n+\tstruct cvmx_pow_wq_int_s cn38xxp2;\n+\tstruct cvmx_pow_wq_int_s cn50xx;\n+\tstruct cvmx_pow_wq_int_s cn52xx;\n+\tstruct cvmx_pow_wq_int_s cn52xxp1;\n+\tstruct cvmx_pow_wq_int_s cn56xx;\n+\tstruct cvmx_pow_wq_int_s cn56xxp1;\n+\tstruct cvmx_pow_wq_int_s cn58xx;\n+\tstruct cvmx_pow_wq_int_s cn58xxp1;\n+\tstruct cvmx_pow_wq_int_s cn61xx;\n+\tstruct cvmx_pow_wq_int_s cn63xx;\n+\tstruct cvmx_pow_wq_int_s cn63xxp1;\n+\tstruct cvmx_pow_wq_int_s cn66xx;\n+\tstruct cvmx_pow_wq_int_s cn70xx;\n+\tstruct cvmx_pow_wq_int_s cn70xxp1;\n+\tstruct cvmx_pow_wq_int_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_wq_int cvmx_pow_wq_int_t;\n+\n+/**\n+ * cvmx_pow_wq_int_cnt#\n+ *\n+ * Contains a read-only copy of the counts used to trigger work queue interrupts. For more\n+ * information regarding this register, see the interrupt section.\n+ */\n+union cvmx_pow_wq_int_cntx {\n+\tu64 u64;\n+\tstruct cvmx_pow_wq_int_cntx_s {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 tc_cnt : 4;\n+\t\tu64 ds_cnt : 12;\n+\t\tu64 iq_cnt : 12;\n+\t} s;\n+\tstruct cvmx_pow_wq_int_cntx_cn30xx {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 tc_cnt : 4;\n+\t\tu64 reserved_19_23 : 5;\n+\t\tu64 ds_cnt : 7;\n+\t\tu64 reserved_7_11 : 5;\n+\t\tu64 iq_cnt : 7;\n+\t} cn30xx;\n+\tstruct cvmx_pow_wq_int_cntx_cn31xx {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 tc_cnt : 4;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 ds_cnt : 9;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 iq_cnt : 9;\n+\t} cn31xx;\n+\tstruct cvmx_pow_wq_int_cntx_s cn38xx;\n+\tstruct cvmx_pow_wq_int_cntx_s cn38xxp2;\n+\tstruct cvmx_pow_wq_int_cntx_cn31xx cn50xx;\n+\tstruct cvmx_pow_wq_int_cntx_cn52xx {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 tc_cnt : 4;\n+\t\tu64 reserved_22_23 : 2;\n+\t\tu64 ds_cnt : 10;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tu64 iq_cnt : 10;\n+\t} cn52xx;\n+\tstruct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1;\n+\tstruct cvmx_pow_wq_int_cntx_s cn56xx;\n+\tstruct cvmx_pow_wq_int_cntx_s cn56xxp1;\n+\tstruct cvmx_pow_wq_int_cntx_s cn58xx;\n+\tstruct cvmx_pow_wq_int_cntx_s cn58xxp1;\n+\tstruct cvmx_pow_wq_int_cntx_cn52xx cn61xx;\n+\tstruct cvmx_pow_wq_int_cntx_cn63xx {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 tc_cnt : 4;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 ds_cnt : 11;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 iq_cnt : 11;\n+\t} cn63xx;\n+\tstruct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1;\n+\tstruct cvmx_pow_wq_int_cntx_cn63xx cn66xx;\n+\tstruct cvmx_pow_wq_int_cntx_cn52xx cn70xx;\n+\tstruct cvmx_pow_wq_int_cntx_cn52xx cn70xxp1;\n+\tstruct cvmx_pow_wq_int_cntx_cn52xx cnf71xx;\n+};\n+\n+typedef union cvmx_pow_wq_int_cntx cvmx_pow_wq_int_cntx_t;\n+\n+/**\n+ * cvmx_pow_wq_int_pc\n+ *\n+ * Contains the threshold value for the work queue interrupt periodic counter and also a read-\n+ * only\n+ * copy of the periodic counter. For more information regarding this register, see the interrupt\n+ * section.\n+ */\n+union cvmx_pow_wq_int_pc {\n+\tu64 u64;\n+\tstruct cvmx_pow_wq_int_pc_s {\n+\t\tu64 reserved_60_63 : 4;\n+\t\tu64 pc : 28;\n+\t\tu64 reserved_28_31 : 4;\n+\t\tu64 pc_thr : 20;\n+\t\tu64 reserved_0_7 : 8;\n+\t} s;\n+\tstruct cvmx_pow_wq_int_pc_s cn30xx;\n+\tstruct cvmx_pow_wq_int_pc_s cn31xx;\n+\tstruct cvmx_pow_wq_int_pc_s cn38xx;\n+\tstruct cvmx_pow_wq_int_pc_s cn38xxp2;\n+\tstruct cvmx_pow_wq_int_pc_s cn50xx;\n+\tstruct cvmx_pow_wq_int_pc_s cn52xx;\n+\tstruct cvmx_pow_wq_int_pc_s cn52xxp1;\n+\tstruct cvmx_pow_wq_int_pc_s cn56xx;\n+\tstruct cvmx_pow_wq_int_pc_s cn56xxp1;\n+\tstruct cvmx_pow_wq_int_pc_s cn58xx;\n+\tstruct cvmx_pow_wq_int_pc_s cn58xxp1;\n+\tstruct cvmx_pow_wq_int_pc_s cn61xx;\n+\tstruct cvmx_pow_wq_int_pc_s cn63xx;\n+\tstruct cvmx_pow_wq_int_pc_s cn63xxp1;\n+\tstruct cvmx_pow_wq_int_pc_s cn66xx;\n+\tstruct cvmx_pow_wq_int_pc_s cn70xx;\n+\tstruct cvmx_pow_wq_int_pc_s cn70xxp1;\n+\tstruct cvmx_pow_wq_int_pc_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_wq_int_pc cvmx_pow_wq_int_pc_t;\n+\n+/**\n+ * cvmx_pow_wq_int_thr#\n+ *\n+ * Contains the thresholds for enabling and setting work queue interrupts. For more information\n+ * regarding this register, see the interrupt section.\n+ * Note: Up to 4 of the POW's internal storage buffers can be allocated for hardware use and are\n+ * therefore not available for incoming work queue entries. Additionally, any PP that is not in\n+ * the\n+ * NULL_NULL state consumes a buffer. Thus in a 4 PP system, it is not advisable to set either\n+ * IQ_THR or DS_THR to greater than 512 - 4 - 4 = 504. Doing so may prevent the interrupt from\n+ * ever triggering.\n+ */\n+union cvmx_pow_wq_int_thrx {\n+\tu64 u64;\n+\tstruct cvmx_pow_wq_int_thrx_s {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 tc_en : 1;\n+\t\tu64 tc_thr : 4;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 ds_thr : 11;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 iq_thr : 11;\n+\t} s;\n+\tstruct cvmx_pow_wq_int_thrx_cn30xx {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 tc_en : 1;\n+\t\tu64 tc_thr : 4;\n+\t\tu64 reserved_18_23 : 6;\n+\t\tu64 ds_thr : 6;\n+\t\tu64 reserved_6_11 : 6;\n+\t\tu64 iq_thr : 6;\n+\t} cn30xx;\n+\tstruct cvmx_pow_wq_int_thrx_cn31xx {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 tc_en : 1;\n+\t\tu64 tc_thr : 4;\n+\t\tu64 reserved_20_23 : 4;\n+\t\tu64 ds_thr : 8;\n+\t\tu64 reserved_8_11 : 4;\n+\t\tu64 iq_thr : 8;\n+\t} cn31xx;\n+\tstruct cvmx_pow_wq_int_thrx_s cn38xx;\n+\tstruct cvmx_pow_wq_int_thrx_s cn38xxp2;\n+\tstruct cvmx_pow_wq_int_thrx_cn31xx cn50xx;\n+\tstruct cvmx_pow_wq_int_thrx_cn52xx {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 tc_en : 1;\n+\t\tu64 tc_thr : 4;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 ds_thr : 9;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 iq_thr : 9;\n+\t} cn52xx;\n+\tstruct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1;\n+\tstruct cvmx_pow_wq_int_thrx_s cn56xx;\n+\tstruct cvmx_pow_wq_int_thrx_s cn56xxp1;\n+\tstruct cvmx_pow_wq_int_thrx_s cn58xx;\n+\tstruct cvmx_pow_wq_int_thrx_s cn58xxp1;\n+\tstruct cvmx_pow_wq_int_thrx_cn52xx cn61xx;\n+\tstruct cvmx_pow_wq_int_thrx_cn63xx {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 tc_en : 1;\n+\t\tu64 tc_thr : 4;\n+\t\tu64 reserved_22_23 : 2;\n+\t\tu64 ds_thr : 10;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tu64 iq_thr : 10;\n+\t} cn63xx;\n+\tstruct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1;\n+\tstruct cvmx_pow_wq_int_thrx_cn63xx cn66xx;\n+\tstruct cvmx_pow_wq_int_thrx_cn52xx cn70xx;\n+\tstruct cvmx_pow_wq_int_thrx_cn52xx cn70xxp1;\n+\tstruct cvmx_pow_wq_int_thrx_cn52xx cnf71xx;\n+};\n+\n+typedef union cvmx_pow_wq_int_thrx cvmx_pow_wq_int_thrx_t;\n+\n+/**\n+ * cvmx_pow_ws_pc#\n+ *\n+ * Counts the number of work schedules for each group. Write to clear.\n+ *\n+ */\n+union cvmx_pow_ws_pcx {\n+\tu64 u64;\n+\tstruct cvmx_pow_ws_pcx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 ws_pc : 32;\n+\t} s;\n+\tstruct cvmx_pow_ws_pcx_s cn30xx;\n+\tstruct cvmx_pow_ws_pcx_s cn31xx;\n+\tstruct cvmx_pow_ws_pcx_s cn38xx;\n+\tstruct cvmx_pow_ws_pcx_s cn38xxp2;\n+\tstruct cvmx_pow_ws_pcx_s cn50xx;\n+\tstruct cvmx_pow_ws_pcx_s cn52xx;\n+\tstruct cvmx_pow_ws_pcx_s cn52xxp1;\n+\tstruct cvmx_pow_ws_pcx_s cn56xx;\n+\tstruct cvmx_pow_ws_pcx_s cn56xxp1;\n+\tstruct cvmx_pow_ws_pcx_s cn58xx;\n+\tstruct cvmx_pow_ws_pcx_s cn58xxp1;\n+\tstruct cvmx_pow_ws_pcx_s cn61xx;\n+\tstruct cvmx_pow_ws_pcx_s cn63xx;\n+\tstruct cvmx_pow_ws_pcx_s cn63xxp1;\n+\tstruct cvmx_pow_ws_pcx_s cn66xx;\n+\tstruct cvmx_pow_ws_pcx_s cn70xx;\n+\tstruct cvmx_pow_ws_pcx_s cn70xxp1;\n+\tstruct cvmx_pow_ws_pcx_s cnf71xx;\n+};\n+\n+typedef union cvmx_pow_ws_pcx cvmx_pow_ws_pcx_t;\n+\n+#endif\n", "prefixes": [ "v1", "25/50" ] }