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{
    "id": 1414999,
    "url": "http://patchwork.ozlabs.org/api/patches/1414999/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-20-sr@denx.de/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
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        "list_archive_url": "",
        "list_archive_url_format": "",
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    },
    "msgid": "<20201211160612.1498780-20-sr@denx.de>",
    "list_archive_url": null,
    "date": "2020-12-11T16:05:41",
    "name": "[v1,19/50] mips: octeon: Add cvmx-pcsx-defs.h header file",
    "commit_ref": "def92cec9e1e82325a3c9552653a55127f5c159a",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "b67674140cb8ea9f5b70363f18ebe979c3995606",
    "submitter": {
        "id": 13,
        "url": "http://patchwork.ozlabs.org/api/people/13/?format=api",
        "name": "Stefan Roese",
        "email": "sr@denx.de"
    },
    "delegate": {
        "id": 4307,
        "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api",
        "username": "danielschwierzeck",
        "first_name": "Daniel",
        "last_name": "Schwierzeck",
        "email": "daniel.schwierzeck@googlemail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-20-sr@denx.de/mbox/",
    "series": [
        {
            "id": 220054,
            "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054",
            "date": "2020-12-11T16:05:23",
            "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1414999/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1414999/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Stefan Roese <sr@denx.de>",
        "To": "u-boot@lists.denx.de",
        "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com",
        "Subject": "[PATCH v1 19/50] mips: octeon: Add cvmx-pcsx-defs.h header file",
        "Date": "Fri, 11 Dec 2020 17:05:41 +0100",
        "Message-Id": "<20201211160612.1498780-20-sr@denx.de>",
        "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>",
        "References": "<20201211160612.1498780-1-sr@denx.de>",
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    "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-pcsx-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-pcsx-defs.h | 1005 +++++++++++++++++\n 1 file changed, 1005 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pcsx-defs.h",
    "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pcsx-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-pcsx-defs.h\nnew file mode 100644\nindex 0000000000..e534b6711d\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-pcsx-defs.h\n@@ -0,0 +1,1005 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon pcsx.\n+ */\n+\n+#ifndef __CVMX_PCSX_DEFS_H__\n+#define __CVMX_PCSX_DEFS_H__\n+\n+static inline u64 CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001010ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001010ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001010ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001010ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001028ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001028ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001028ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001028ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001018ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001018ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001018ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001018ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001020ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001020ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001020ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001020ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001088ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001088ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001088ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001088ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001080ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001080ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001080ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001080ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001040ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001040ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001040ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001040ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001090ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001090ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001090ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001090ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+#define CVMX_PCSX_MAC_CRDT_CNTX_REG(offset, block_id)                                              \\\n+\t(0x00011800B00010B0ull + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)\n+static inline u64 CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001078ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001078ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001078ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001078ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001000ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001000ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001000ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001000ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001008ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001008ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001008ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001008ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001058ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001058ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001058ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001058ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001050ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001050ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001050ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001050ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+#define CVMX_PCSX_SERDES_CRDT_CNTX_REG(offset, block_id)                                           \\\n+\t(0x00011800B00010A0ull + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024)\n+static inline u64 CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001068ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001068ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001068ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001068ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001070ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001070ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001070ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001070ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001060ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001060ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001060ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001060ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+static inline u64 CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001048ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001048ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800B0001048ull + ((offset) + (block_id) * 0x4000ull) * 1024;\n+\t}\n+\treturn 0x00011800B0001048ull + ((offset) + (block_id) * 0x20000ull) * 1024;\n+}\n+\n+/**\n+ * cvmx_pcs#_an#_adv_reg\n+ *\n+ * Bits [15:9] in the Status Register indicate ability to operate as per those signalling specification,\n+ * when misc ctl reg MAC_PHY bit is set to MAC mode. Bits [15:9] will all, always read 1'b0, indicating\n+ * that the chip cannot operate in the corresponding modes.\n+ *\n+ * Bit [4] RM_FLT is a don't care when the selected mode is SGMII.\n+ *\n+ *\n+ *\n+ * PCS_AN_ADV_REG = AN Advertisement Register4\n+ */\n+union cvmx_pcsx_anx_adv_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_anx_adv_reg_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 np : 1;\n+\t\tu64 reserved_14_14 : 1;\n+\t\tu64 rem_flt : 2;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 pause : 2;\n+\t\tu64 hfd : 1;\n+\t\tu64 fd : 1;\n+\t\tu64 reserved_0_4 : 5;\n+\t} s;\n+\tstruct cvmx_pcsx_anx_adv_reg_s cn52xx;\n+\tstruct cvmx_pcsx_anx_adv_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_anx_adv_reg_s cn56xx;\n+\tstruct cvmx_pcsx_anx_adv_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_anx_adv_reg_s cn61xx;\n+\tstruct cvmx_pcsx_anx_adv_reg_s cn63xx;\n+\tstruct cvmx_pcsx_anx_adv_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_anx_adv_reg_s cn66xx;\n+\tstruct cvmx_pcsx_anx_adv_reg_s cn68xx;\n+\tstruct cvmx_pcsx_anx_adv_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_anx_adv_reg_s cn70xx;\n+\tstruct cvmx_pcsx_anx_adv_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_anx_adv_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_anx_adv_reg cvmx_pcsx_anx_adv_reg_t;\n+\n+/**\n+ * cvmx_pcs#_an#_ext_st_reg\n+ *\n+ * as per IEEE802.3 Clause 22\n+ *\n+ */\n+union cvmx_pcsx_anx_ext_st_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 thou_xfd : 1;\n+\t\tu64 thou_xhd : 1;\n+\t\tu64 thou_tfd : 1;\n+\t\tu64 thou_thd : 1;\n+\t\tu64 reserved_0_11 : 12;\n+\t} s;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_s cn52xx;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_s cn56xx;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_s cn61xx;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_s cn63xx;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_s cn66xx;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_s cn68xx;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_cn70xx {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 thou_xfd : 1;\n+\t\tu64 thou_xhd : 1;\n+\t\tu64 thou_tfd : 1;\n+\t\tu64 thou_thd : 1;\n+\t\tu64 reserved_11_0 : 12;\n+\t} cn70xx;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_cn70xx cn70xxp1;\n+\tstruct cvmx_pcsx_anx_ext_st_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_anx_ext_st_reg cvmx_pcsx_anx_ext_st_reg_t;\n+\n+/**\n+ * cvmx_pcs#_an#_lp_abil_reg\n+ *\n+ * as per IEEE802.3 Clause 37\n+ *\n+ */\n+union cvmx_pcsx_anx_lp_abil_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 np : 1;\n+\t\tu64 ack : 1;\n+\t\tu64 rem_flt : 2;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 pause : 2;\n+\t\tu64 hfd : 1;\n+\t\tu64 fd : 1;\n+\t\tu64 reserved_0_4 : 5;\n+\t} s;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s cn61xx;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s cn63xx;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s cn66xx;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s cn68xx;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s cn70xx;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_anx_lp_abil_reg cvmx_pcsx_anx_lp_abil_reg_t;\n+\n+/**\n+ * cvmx_pcs#_an#_results_reg\n+ *\n+ * NOTE:\n+ * an_results_reg is don't care when AN_OVRD is set to 1. If AN_OVRD=0 and AN_CPT=1\n+ * the an_results_reg is valid.\n+ */\n+union cvmx_pcsx_anx_results_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_anx_results_reg_s {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 pause : 2;\n+\t\tu64 spd : 2;\n+\t\tu64 an_cpt : 1;\n+\t\tu64 dup : 1;\n+\t\tu64 link_ok : 1;\n+\t} s;\n+\tstruct cvmx_pcsx_anx_results_reg_s cn52xx;\n+\tstruct cvmx_pcsx_anx_results_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_anx_results_reg_s cn56xx;\n+\tstruct cvmx_pcsx_anx_results_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_anx_results_reg_s cn61xx;\n+\tstruct cvmx_pcsx_anx_results_reg_s cn63xx;\n+\tstruct cvmx_pcsx_anx_results_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_anx_results_reg_s cn66xx;\n+\tstruct cvmx_pcsx_anx_results_reg_s cn68xx;\n+\tstruct cvmx_pcsx_anx_results_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_anx_results_reg_s cn70xx;\n+\tstruct cvmx_pcsx_anx_results_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_anx_results_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_anx_results_reg cvmx_pcsx_anx_results_reg_t;\n+\n+/**\n+ * cvmx_pcs#_int#_en_reg\n+ *\n+ * PCS Interrupt Enable Register\n+ *\n+ */\n+union cvmx_pcsx_intx_en_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_intx_en_reg_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 dbg_sync_en : 1;\n+\t\tu64 dup : 1;\n+\t\tu64 sync_bad_en : 1;\n+\t\tu64 an_bad_en : 1;\n+\t\tu64 rxlock_en : 1;\n+\t\tu64 rxbad_en : 1;\n+\t\tu64 rxerr_en : 1;\n+\t\tu64 txbad_en : 1;\n+\t\tu64 txfifo_en : 1;\n+\t\tu64 txfifu_en : 1;\n+\t\tu64 an_err_en : 1;\n+\t\tu64 xmit_en : 1;\n+\t\tu64 lnkspd_en : 1;\n+\t} s;\n+\tstruct cvmx_pcsx_intx_en_reg_cn52xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 dup : 1;\n+\t\tu64 sync_bad_en : 1;\n+\t\tu64 an_bad_en : 1;\n+\t\tu64 rxlock_en : 1;\n+\t\tu64 rxbad_en : 1;\n+\t\tu64 rxerr_en : 1;\n+\t\tu64 txbad_en : 1;\n+\t\tu64 txfifo_en : 1;\n+\t\tu64 txfifu_en : 1;\n+\t\tu64 an_err_en : 1;\n+\t\tu64 xmit_en : 1;\n+\t\tu64 lnkspd_en : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1;\n+\tstruct cvmx_pcsx_intx_en_reg_cn52xx cn56xx;\n+\tstruct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1;\n+\tstruct cvmx_pcsx_intx_en_reg_s cn61xx;\n+\tstruct cvmx_pcsx_intx_en_reg_s cn63xx;\n+\tstruct cvmx_pcsx_intx_en_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_intx_en_reg_s cn66xx;\n+\tstruct cvmx_pcsx_intx_en_reg_s cn68xx;\n+\tstruct cvmx_pcsx_intx_en_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_intx_en_reg_s cn70xx;\n+\tstruct cvmx_pcsx_intx_en_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_intx_en_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_intx_en_reg cvmx_pcsx_intx_en_reg_t;\n+\n+/**\n+ * cvmx_pcs#_int#_reg\n+ *\n+ * PCS Interrupt Register\n+ * NOTE: RXERR and TXERR conditions to be discussed with Dan before finalising\n+ * DBG_SYNC interrupt fires when code group synchronization state machine makes a transition from\n+ * SYNC_ACQUIRED_1 state to SYNC_ACQUIRED_2 state(See IEEE 802.3-2005 figure 37-9). It is an\n+ * indication that a bad code group\n+ * was received after code group synchronizaton was achieved. This interrupt should be disabled\n+ * during normal link operation.\n+ * Use it as a debug help feature only.\n+ */\n+union cvmx_pcsx_intx_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_intx_reg_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 dbg_sync : 1;\n+\t\tu64 dup : 1;\n+\t\tu64 sync_bad : 1;\n+\t\tu64 an_bad : 1;\n+\t\tu64 rxlock : 1;\n+\t\tu64 rxbad : 1;\n+\t\tu64 rxerr : 1;\n+\t\tu64 txbad : 1;\n+\t\tu64 txfifo : 1;\n+\t\tu64 txfifu : 1;\n+\t\tu64 an_err : 1;\n+\t\tu64 xmit : 1;\n+\t\tu64 lnkspd : 1;\n+\t} s;\n+\tstruct cvmx_pcsx_intx_reg_cn52xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 dup : 1;\n+\t\tu64 sync_bad : 1;\n+\t\tu64 an_bad : 1;\n+\t\tu64 rxlock : 1;\n+\t\tu64 rxbad : 1;\n+\t\tu64 rxerr : 1;\n+\t\tu64 txbad : 1;\n+\t\tu64 txfifo : 1;\n+\t\tu64 txfifu : 1;\n+\t\tu64 an_err : 1;\n+\t\tu64 xmit : 1;\n+\t\tu64 lnkspd : 1;\n+\t} cn52xx;\n+\tstruct cvmx_pcsx_intx_reg_cn52xx cn52xxp1;\n+\tstruct cvmx_pcsx_intx_reg_cn52xx cn56xx;\n+\tstruct cvmx_pcsx_intx_reg_cn52xx cn56xxp1;\n+\tstruct cvmx_pcsx_intx_reg_s cn61xx;\n+\tstruct cvmx_pcsx_intx_reg_s cn63xx;\n+\tstruct cvmx_pcsx_intx_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_intx_reg_s cn66xx;\n+\tstruct cvmx_pcsx_intx_reg_s cn68xx;\n+\tstruct cvmx_pcsx_intx_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_intx_reg_s cn70xx;\n+\tstruct cvmx_pcsx_intx_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_intx_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_intx_reg cvmx_pcsx_intx_reg_t;\n+\n+/**\n+ * cvmx_pcs#_link#_timer_count_reg\n+ *\n+ * PCS_LINK_TIMER_COUNT_REG = 1.6ms nominal link timer register\n+ *\n+ */\n+union cvmx_pcsx_linkx_timer_count_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 count : 16;\n+\t} s;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s cn61xx;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s cn63xx;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s cn66xx;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s cn68xx;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s cn70xx;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_linkx_timer_count_reg cvmx_pcsx_linkx_timer_count_reg_t;\n+\n+/**\n+ * cvmx_pcs#_log_anl#_reg\n+ *\n+ * PCS Logic Analyzer Register\n+ * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is\n+ * effective only when LA_EN=1\n+ * For normal operation(sgmii or 1000Base-X), this bit must be 0.\n+ * See pcsx.csr for xaui logic analyzer mode.\n+ * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt\n+ */\n+union cvmx_pcsx_log_anlx_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_log_anlx_reg_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 lafifovfl : 1;\n+\t\tu64 la_en : 1;\n+\t\tu64 pkt_sz : 2;\n+\t} s;\n+\tstruct cvmx_pcsx_log_anlx_reg_s cn52xx;\n+\tstruct cvmx_pcsx_log_anlx_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_log_anlx_reg_s cn56xx;\n+\tstruct cvmx_pcsx_log_anlx_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_log_anlx_reg_s cn61xx;\n+\tstruct cvmx_pcsx_log_anlx_reg_s cn63xx;\n+\tstruct cvmx_pcsx_log_anlx_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_log_anlx_reg_s cn66xx;\n+\tstruct cvmx_pcsx_log_anlx_reg_s cn68xx;\n+\tstruct cvmx_pcsx_log_anlx_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_log_anlx_reg_s cn70xx;\n+\tstruct cvmx_pcsx_log_anlx_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_log_anlx_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_log_anlx_reg cvmx_pcsx_log_anlx_reg_t;\n+\n+/**\n+ * cvmx_pcs#_mac_crdt_cnt#_reg\n+ *\n+ * PCS MAC Credit Count\n+ *\n+ */\n+union cvmx_pcsx_mac_crdt_cntx_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_mac_crdt_cntx_reg_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 cnt : 5;\n+\t} s;\n+\tstruct cvmx_pcsx_mac_crdt_cntx_reg_s cn70xx;\n+\tstruct cvmx_pcsx_mac_crdt_cntx_reg_s cn70xxp1;\n+};\n+\n+typedef union cvmx_pcsx_mac_crdt_cntx_reg cvmx_pcsx_mac_crdt_cntx_reg_t;\n+\n+/**\n+ * cvmx_pcs#_misc#_ctl_reg\n+ *\n+ * SGMII Misc Control Register\n+ * SGMII bit [12] is really a misnomer, it is a decode  of pi_qlm_cfg pins to indicate SGMII or\n+ * 1000Base-X modes.\n+ * Note: MODE bit\n+ * When MODE=1,  1000Base-X mode is selected. Auto negotiation will follow IEEE 802.3 clause 37.\n+ * When MODE=0,  SGMII mode is selected and the following note will apply.\n+ * Repeat note from SGM_AN_ADV register\n+ * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the\n+ * MAC_PHY mode bit in misc_ctl_reg\n+ * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit\n+ * and [0] is always 1.\n+ * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results.\n+ */\n+union cvmx_pcsx_miscx_ctl_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 sgmii : 1;\n+\t\tu64 gmxeno : 1;\n+\t\tu64 loopbck2 : 1;\n+\t\tu64 mac_phy : 1;\n+\t\tu64 mode : 1;\n+\t\tu64 an_ovrd : 1;\n+\t\tu64 samp_pt : 7;\n+\t} s;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_s cn52xx;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_s cn56xx;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_s cn61xx;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_s cn63xx;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_s cn66xx;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_s cn68xx;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_cn70xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 gmxeno : 1;\n+\t\tu64 loopbck2 : 1;\n+\t\tu64 mac_phy : 1;\n+\t\tu64 mode : 1;\n+\t\tu64 an_ovrd : 1;\n+\t\tu64 samp_pt : 7;\n+\t} cn70xx;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_cn70xx cn70xxp1;\n+\tstruct cvmx_pcsx_miscx_ctl_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_miscx_ctl_reg cvmx_pcsx_miscx_ctl_reg_t;\n+\n+/**\n+ * cvmx_pcs#_mr#_control_reg\n+ *\n+ * NOTE:\n+ * Whenever AN_EN bit[12] is set, Auto negotiation is allowed to happen. The results\n+ * of the auto negotiation process set the fields in the AN_RESULTS reg. When AN_EN is not set,\n+ * AN_RESULTS reg is don't care. The effective SPD, DUP etc.. get their values\n+ * from the pcs_mr_ctrl reg.\n+ */\n+union cvmx_pcsx_mrx_control_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_mrx_control_reg_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 reset : 1;\n+\t\tu64 loopbck1 : 1;\n+\t\tu64 spdlsb : 1;\n+\t\tu64 an_en : 1;\n+\t\tu64 pwr_dn : 1;\n+\t\tu64 reserved_10_10 : 1;\n+\t\tu64 rst_an : 1;\n+\t\tu64 dup : 1;\n+\t\tu64 coltst : 1;\n+\t\tu64 spdmsb : 1;\n+\t\tu64 uni : 1;\n+\t\tu64 reserved_0_4 : 5;\n+\t} s;\n+\tstruct cvmx_pcsx_mrx_control_reg_s cn52xx;\n+\tstruct cvmx_pcsx_mrx_control_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_mrx_control_reg_s cn56xx;\n+\tstruct cvmx_pcsx_mrx_control_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_mrx_control_reg_s cn61xx;\n+\tstruct cvmx_pcsx_mrx_control_reg_s cn63xx;\n+\tstruct cvmx_pcsx_mrx_control_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_mrx_control_reg_s cn66xx;\n+\tstruct cvmx_pcsx_mrx_control_reg_s cn68xx;\n+\tstruct cvmx_pcsx_mrx_control_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_mrx_control_reg_s cn70xx;\n+\tstruct cvmx_pcsx_mrx_control_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_mrx_control_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_mrx_control_reg cvmx_pcsx_mrx_control_reg_t;\n+\n+/**\n+ * cvmx_pcs#_mr#_status_reg\n+ *\n+ * Bits [15:9] in the Status Register indicate ability to operate as per those signalling\n+ * specification,\n+ * when misc ctl reg MAC_PHY bit is set to MAC mode. Bits [15:9] will all, always read 1'b0,\n+ * indicating\n+ * that the chip cannot operate in the corresponding modes.\n+ * Bit [4] RM_FLT is a don't care when the selected mode is SGMII.\n+ */\n+union cvmx_pcsx_mrx_status_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_mrx_status_reg_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 hun_t4 : 1;\n+\t\tu64 hun_xfd : 1;\n+\t\tu64 hun_xhd : 1;\n+\t\tu64 ten_fd : 1;\n+\t\tu64 ten_hd : 1;\n+\t\tu64 hun_t2fd : 1;\n+\t\tu64 hun_t2hd : 1;\n+\t\tu64 ext_st : 1;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 prb_sup : 1;\n+\t\tu64 an_cpt : 1;\n+\t\tu64 rm_flt : 1;\n+\t\tu64 an_abil : 1;\n+\t\tu64 lnk_st : 1;\n+\t\tu64 reserved_1_1 : 1;\n+\t\tu64 extnd : 1;\n+\t} s;\n+\tstruct cvmx_pcsx_mrx_status_reg_s cn52xx;\n+\tstruct cvmx_pcsx_mrx_status_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_mrx_status_reg_s cn56xx;\n+\tstruct cvmx_pcsx_mrx_status_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_mrx_status_reg_s cn61xx;\n+\tstruct cvmx_pcsx_mrx_status_reg_s cn63xx;\n+\tstruct cvmx_pcsx_mrx_status_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_mrx_status_reg_s cn66xx;\n+\tstruct cvmx_pcsx_mrx_status_reg_s cn68xx;\n+\tstruct cvmx_pcsx_mrx_status_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_mrx_status_reg_s cn70xx;\n+\tstruct cvmx_pcsx_mrx_status_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_mrx_status_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_mrx_status_reg cvmx_pcsx_mrx_status_reg_t;\n+\n+/**\n+ * cvmx_pcs#_rx#_states_reg\n+ *\n+ * PCS_RX_STATES_REG = RX State Machines states register\n+ *\n+ */\n+union cvmx_pcsx_rxx_states_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_rxx_states_reg_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 rx_bad : 1;\n+\t\tu64 rx_st : 5;\n+\t\tu64 sync_bad : 1;\n+\t\tu64 sync : 4;\n+\t\tu64 an_bad : 1;\n+\t\tu64 an_st : 4;\n+\t} s;\n+\tstruct cvmx_pcsx_rxx_states_reg_s cn52xx;\n+\tstruct cvmx_pcsx_rxx_states_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_rxx_states_reg_s cn56xx;\n+\tstruct cvmx_pcsx_rxx_states_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_rxx_states_reg_s cn61xx;\n+\tstruct cvmx_pcsx_rxx_states_reg_s cn63xx;\n+\tstruct cvmx_pcsx_rxx_states_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_rxx_states_reg_s cn66xx;\n+\tstruct cvmx_pcsx_rxx_states_reg_s cn68xx;\n+\tstruct cvmx_pcsx_rxx_states_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_rxx_states_reg_s cn70xx;\n+\tstruct cvmx_pcsx_rxx_states_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_rxx_states_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_rxx_states_reg cvmx_pcsx_rxx_states_reg_t;\n+\n+/**\n+ * cvmx_pcs#_rx#_sync_reg\n+ *\n+ * Note:\n+ * r_tx_rx_polarity_reg bit [2] will show correct polarity needed on the link receive path after code grp synchronization is achieved.\n+ *\n+ *\n+ *  PCS_RX_SYNC_REG = Code Group synchronization reg\n+ */\n+union cvmx_pcsx_rxx_sync_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 sync : 1;\n+\t\tu64 bit_lock : 1;\n+\t} s;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s cn52xx;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s cn56xx;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s cn61xx;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s cn63xx;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s cn66xx;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s cn68xx;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s cn70xx;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_rxx_sync_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_rxx_sync_reg cvmx_pcsx_rxx_sync_reg_t;\n+\n+/**\n+ * cvmx_pcs#_serdes_crdt_cnt#_reg\n+ *\n+ * PCS SERDES Credit Count\n+ *\n+ */\n+union cvmx_pcsx_serdes_crdt_cntx_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_serdes_crdt_cntx_reg_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 cnt : 5;\n+\t} s;\n+\tstruct cvmx_pcsx_serdes_crdt_cntx_reg_s cn70xx;\n+\tstruct cvmx_pcsx_serdes_crdt_cntx_reg_s cn70xxp1;\n+};\n+\n+typedef union cvmx_pcsx_serdes_crdt_cntx_reg cvmx_pcsx_serdes_crdt_cntx_reg_t;\n+\n+/**\n+ * cvmx_pcs#_sgm#_an_adv_reg\n+ *\n+ * SGMII AN Advertisement Register (sent out as tx_config_reg)\n+ * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the\n+ * MAC_PHY mode bit in misc_ctl_reg\n+ * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit\n+ * and [0] is always 1.\n+ * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results.\n+ */\n+union cvmx_pcsx_sgmx_an_adv_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 link : 1;\n+\t\tu64 ack : 1;\n+\t\tu64 reserved_13_13 : 1;\n+\t\tu64 dup : 1;\n+\t\tu64 speed : 2;\n+\t\tu64 reserved_1_9 : 9;\n+\t\tu64 one : 1;\n+\t} s;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s cn70xx;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_sgmx_an_adv_reg cvmx_pcsx_sgmx_an_adv_reg_t;\n+\n+/**\n+ * cvmx_pcs#_sgm#_lp_adv_reg\n+ *\n+ * SGMII LP Advertisement Register (received as rx_config_reg)\n+ *\n+ */\n+union cvmx_pcsx_sgmx_lp_adv_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 link : 1;\n+\t\tu64 reserved_13_14 : 2;\n+\t\tu64 dup : 1;\n+\t\tu64 speed : 2;\n+\t\tu64 reserved_1_9 : 9;\n+\t\tu64 one : 1;\n+\t} s;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s cn70xx;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_sgmx_lp_adv_reg cvmx_pcsx_sgmx_lp_adv_reg_t;\n+\n+/**\n+ * cvmx_pcs#_tx#_states_reg\n+ *\n+ * PCS_TX_STATES_REG = TX State Machines states register\n+ *\n+ */\n+union cvmx_pcsx_txx_states_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_txx_states_reg_s {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 xmit : 2;\n+\t\tu64 tx_bad : 1;\n+\t\tu64 ord_st : 4;\n+\t} s;\n+\tstruct cvmx_pcsx_txx_states_reg_s cn52xx;\n+\tstruct cvmx_pcsx_txx_states_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_txx_states_reg_s cn56xx;\n+\tstruct cvmx_pcsx_txx_states_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_txx_states_reg_s cn61xx;\n+\tstruct cvmx_pcsx_txx_states_reg_s cn63xx;\n+\tstruct cvmx_pcsx_txx_states_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_txx_states_reg_s cn66xx;\n+\tstruct cvmx_pcsx_txx_states_reg_s cn68xx;\n+\tstruct cvmx_pcsx_txx_states_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_txx_states_reg_s cn70xx;\n+\tstruct cvmx_pcsx_txx_states_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_txx_states_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_txx_states_reg cvmx_pcsx_txx_states_reg_t;\n+\n+/**\n+ * cvmx_pcs#_tx_rx#_polarity_reg\n+ *\n+ * Note:\n+ * r_tx_rx_polarity_reg bit [2] will show correct polarity needed on the link receive path after\n+ * code grp synchronization is achieved.\n+ */\n+union cvmx_pcsx_tx_rxx_polarity_reg {\n+\tu64 u64;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 rxovrd : 1;\n+\t\tu64 autorxpl : 1;\n+\t\tu64 rxplrt : 1;\n+\t\tu64 txplrt : 1;\n+\t} s;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s cn70xx;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s cn70xxp1;\n+\tstruct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx;\n+};\n+\n+typedef union cvmx_pcsx_tx_rxx_polarity_reg cvmx_pcsx_tx_rxx_polarity_reg_t;\n+\n+#endif\n",
    "prefixes": [
        "v1",
        "19/50"
    ]
}