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GET /api/patches/1414997/?format=api
{ "id": 1414997, "url": "http://patchwork.ozlabs.org/api/patches/1414997/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-30-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-30-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:51", "name": "[v1,29/50] mips: octeon: Add cvmx-smix-defs.h header file", "commit_ref": "fa84c78f74402254f28a101f72bf04913f3b287c", "pull_url": null, "state": "accepted", "archived": false, "hash": "b61a5d733e63823af146b830ecbe80497685e70f", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-30-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1414997/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1414997/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=ucNacvbZ;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4Cswjv64dwz9sSs\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:10:27 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 3D79E827A2;\n\tFri, 11 Dec 2020 17:07:47 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 448A482785; Fri, 11 Dec 2020 17:07:15 +0100 (CET)", "from mx2.mailbox.org (mx2.mailbox.org [80.241.60.215])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 575D182729\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:26 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org\n [IPv6:2001:67c:2050:105:465:1:1:0])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id BC8D4A0B4B;\n Fri, 11 Dec 2020 17:06:25 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter01.heinlein-hosting.de (spamfilter01.heinlein-hosting.de\n [80.241.56.115]) (amavisd-new, port 10030)\n with ESMTP id wJZFAREWqCSY; Fri, 11 Dec 2020 17:06:22 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702867;\n\tbh=Dwxn/M+qV6Vp4HriKNDMoSmZZk5gApQDnoX97ctdkzQ=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=ucNacvbZ4Am3EyPKnfvTDDU4IRPXkPhZAQyZgGMcsWTJlL8WxyHO3xmF1LGpYWFEQ\n\t hETX3QPnHcmCz3ikvU8nbzMTsJTbqOhOQckEzCVML3C8xCscvqAL5A74dXB3xyp5g6\n\t aubu4JmUvPM0ppxnfM1SdRL0MvGLM90WECm2aAOhFB/xnlDhtiVffsh1uC/063IH6d\n\t EFZIL8TVnozcvV61wnrlK690xjpmBQHyaTK3iJ3aXzva3g6tSYtHgUnEolZxPb+thw\n\t UnagFupJD2ZvIMdV7KbtenbNi54H5A1ORON4lh0GaCmnXeu7QW6JKWf9YPRSMDlUEa\n\t Vx4CYdwKWxIDQ==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 29/50] mips: octeon: Add cvmx-smix-defs.h header file", "Date": "Fri, 11 Dec 2020 17:05:51 +0100", "Message-Id": "<20201211160612.1498780-30-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-0.76 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "9B0111893", "X-Rspamd-UID": "143beb", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-smix-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-smix-defs.h | 360 ++++++++++++++++++\n 1 file changed, 360 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h", "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h\nnew file mode 100644\nindex 0000000000..c51d71b38f\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h\n@@ -0,0 +1,360 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon smix.\n+ */\n+\n+#ifndef __CVMX_SMIX_DEFS_H__\n+#define __CVMX_SMIX_DEFS_H__\n+\n+static inline u64 CVMX_SMIX_CLK(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000001818ull + (offset) * 256;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0001180000003818ull + (offset) * 128;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0001180000003818ull + (offset) * 128;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000003818ull + (offset) * 128;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000003818ull + (offset) * 128;\n+\t}\n+\treturn 0x0001180000003818ull + (offset) * 128;\n+}\n+\n+static inline u64 CVMX_SMIX_CMD(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000001800ull + (offset) * 256;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0001180000003800ull + (offset) * 128;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0001180000003800ull + (offset) * 128;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000003800ull + (offset) * 128;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000003800ull + (offset) * 128;\n+\t}\n+\treturn 0x0001180000003800ull + (offset) * 128;\n+}\n+\n+static inline u64 CVMX_SMIX_EN(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000001820ull + (offset) * 256;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0001180000003820ull + (offset) * 128;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0001180000003820ull + (offset) * 128;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000003820ull + (offset) * 128;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000003820ull + (offset) * 128;\n+\t}\n+\treturn 0x0001180000003820ull + (offset) * 128;\n+}\n+\n+static inline u64 CVMX_SMIX_RD_DAT(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000001810ull + (offset) * 256;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0001180000003810ull + (offset) * 128;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0001180000003810ull + (offset) * 128;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000003810ull + (offset) * 128;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000003810ull + (offset) * 128;\n+\t}\n+\treturn 0x0001180000003810ull + (offset) * 128;\n+}\n+\n+static inline u64 CVMX_SMIX_WR_DAT(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000001808ull + (offset) * 256;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0001180000003808ull + (offset) * 128;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0001180000003808ull + (offset) * 128;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000003808ull + (offset) * 128;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180000003808ull + (offset) * 128;\n+\t}\n+\treturn 0x0001180000003808ull + (offset) * 128;\n+}\n+\n+/**\n+ * cvmx_smi#_clk\n+ *\n+ * This register determines the SMI timing characteristics.\n+ * If software wants to change SMI CLK timing parameters ([SAMPLE]/[SAMPLE_HI]), software\n+ * must delay the SMI_()_CLK CSR write by at least 512 coprocessor-clock cycles after the\n+ * previous SMI operation is finished.\n+ */\n+union cvmx_smix_clk {\n+\tu64 u64;\n+\tstruct cvmx_smix_clk_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 mode : 1;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 sample_hi : 5;\n+\t\tu64 sample_mode : 1;\n+\t\tu64 reserved_14_14 : 1;\n+\t\tu64 clk_idle : 1;\n+\t\tu64 preamble : 1;\n+\t\tu64 sample : 4;\n+\t\tu64 phase : 8;\n+\t} s;\n+\tstruct cvmx_smix_clk_cn30xx {\n+\t\tu64 reserved_21_63 : 43;\n+\t\tu64 sample_hi : 5;\n+\t\tu64 sample_mode : 1;\n+\t\tu64 reserved_14_14 : 1;\n+\t\tu64 clk_idle : 1;\n+\t\tu64 preamble : 1;\n+\t\tu64 sample : 4;\n+\t\tu64 phase : 8;\n+\t} cn30xx;\n+\tstruct cvmx_smix_clk_cn30xx cn31xx;\n+\tstruct cvmx_smix_clk_cn30xx cn38xx;\n+\tstruct cvmx_smix_clk_cn30xx cn38xxp2;\n+\tstruct cvmx_smix_clk_s cn50xx;\n+\tstruct cvmx_smix_clk_s cn52xx;\n+\tstruct cvmx_smix_clk_s cn52xxp1;\n+\tstruct cvmx_smix_clk_s cn56xx;\n+\tstruct cvmx_smix_clk_s cn56xxp1;\n+\tstruct cvmx_smix_clk_cn30xx cn58xx;\n+\tstruct cvmx_smix_clk_cn30xx cn58xxp1;\n+\tstruct cvmx_smix_clk_s cn61xx;\n+\tstruct cvmx_smix_clk_s cn63xx;\n+\tstruct cvmx_smix_clk_s cn63xxp1;\n+\tstruct cvmx_smix_clk_s cn66xx;\n+\tstruct cvmx_smix_clk_s cn68xx;\n+\tstruct cvmx_smix_clk_s cn68xxp1;\n+\tstruct cvmx_smix_clk_s cn70xx;\n+\tstruct cvmx_smix_clk_s cn70xxp1;\n+\tstruct cvmx_smix_clk_s cn73xx;\n+\tstruct cvmx_smix_clk_s cn78xx;\n+\tstruct cvmx_smix_clk_s cn78xxp1;\n+\tstruct cvmx_smix_clk_s cnf71xx;\n+\tstruct cvmx_smix_clk_s cnf75xx;\n+};\n+\n+typedef union cvmx_smix_clk cvmx_smix_clk_t;\n+\n+/**\n+ * cvmx_smi#_cmd\n+ *\n+ * This register forces a read or write command to the PHY. Write operations to this register\n+ * create SMI transactions. Software will poll (depending on the transaction type).\n+ */\n+union cvmx_smix_cmd {\n+\tu64 u64;\n+\tstruct cvmx_smix_cmd_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 phy_op : 2;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 phy_adr : 5;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 reg_adr : 5;\n+\t} s;\n+\tstruct cvmx_smix_cmd_cn30xx {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 phy_op : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 phy_adr : 5;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 reg_adr : 5;\n+\t} cn30xx;\n+\tstruct cvmx_smix_cmd_cn30xx cn31xx;\n+\tstruct cvmx_smix_cmd_cn30xx cn38xx;\n+\tstruct cvmx_smix_cmd_cn30xx cn38xxp2;\n+\tstruct cvmx_smix_cmd_s cn50xx;\n+\tstruct cvmx_smix_cmd_s cn52xx;\n+\tstruct cvmx_smix_cmd_s cn52xxp1;\n+\tstruct cvmx_smix_cmd_s cn56xx;\n+\tstruct cvmx_smix_cmd_s cn56xxp1;\n+\tstruct cvmx_smix_cmd_cn30xx cn58xx;\n+\tstruct cvmx_smix_cmd_cn30xx cn58xxp1;\n+\tstruct cvmx_smix_cmd_s cn61xx;\n+\tstruct cvmx_smix_cmd_s cn63xx;\n+\tstruct cvmx_smix_cmd_s cn63xxp1;\n+\tstruct cvmx_smix_cmd_s cn66xx;\n+\tstruct cvmx_smix_cmd_s cn68xx;\n+\tstruct cvmx_smix_cmd_s cn68xxp1;\n+\tstruct cvmx_smix_cmd_s cn70xx;\n+\tstruct cvmx_smix_cmd_s cn70xxp1;\n+\tstruct cvmx_smix_cmd_s cn73xx;\n+\tstruct cvmx_smix_cmd_s cn78xx;\n+\tstruct cvmx_smix_cmd_s cn78xxp1;\n+\tstruct cvmx_smix_cmd_s cnf71xx;\n+\tstruct cvmx_smix_cmd_s cnf75xx;\n+};\n+\n+typedef union cvmx_smix_cmd cvmx_smix_cmd_t;\n+\n+/**\n+ * cvmx_smi#_en\n+ *\n+ * Enables the SMI interface.\n+ *\n+ */\n+union cvmx_smix_en {\n+\tu64 u64;\n+\tstruct cvmx_smix_en_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 en : 1;\n+\t} s;\n+\tstruct cvmx_smix_en_s cn30xx;\n+\tstruct cvmx_smix_en_s cn31xx;\n+\tstruct cvmx_smix_en_s cn38xx;\n+\tstruct cvmx_smix_en_s cn38xxp2;\n+\tstruct cvmx_smix_en_s cn50xx;\n+\tstruct cvmx_smix_en_s cn52xx;\n+\tstruct cvmx_smix_en_s cn52xxp1;\n+\tstruct cvmx_smix_en_s cn56xx;\n+\tstruct cvmx_smix_en_s cn56xxp1;\n+\tstruct cvmx_smix_en_s cn58xx;\n+\tstruct cvmx_smix_en_s cn58xxp1;\n+\tstruct cvmx_smix_en_s cn61xx;\n+\tstruct cvmx_smix_en_s cn63xx;\n+\tstruct cvmx_smix_en_s cn63xxp1;\n+\tstruct cvmx_smix_en_s cn66xx;\n+\tstruct cvmx_smix_en_s cn68xx;\n+\tstruct cvmx_smix_en_s cn68xxp1;\n+\tstruct cvmx_smix_en_s cn70xx;\n+\tstruct cvmx_smix_en_s cn70xxp1;\n+\tstruct cvmx_smix_en_s cn73xx;\n+\tstruct cvmx_smix_en_s cn78xx;\n+\tstruct cvmx_smix_en_s cn78xxp1;\n+\tstruct cvmx_smix_en_s cnf71xx;\n+\tstruct cvmx_smix_en_s cnf75xx;\n+};\n+\n+typedef union cvmx_smix_en cvmx_smix_en_t;\n+\n+/**\n+ * cvmx_smi#_rd_dat\n+ *\n+ * This register contains the data in a read operation.\n+ *\n+ */\n+union cvmx_smix_rd_dat {\n+\tu64 u64;\n+\tstruct cvmx_smix_rd_dat_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 pending : 1;\n+\t\tu64 val : 1;\n+\t\tu64 dat : 16;\n+\t} s;\n+\tstruct cvmx_smix_rd_dat_s cn30xx;\n+\tstruct cvmx_smix_rd_dat_s cn31xx;\n+\tstruct cvmx_smix_rd_dat_s cn38xx;\n+\tstruct cvmx_smix_rd_dat_s cn38xxp2;\n+\tstruct cvmx_smix_rd_dat_s cn50xx;\n+\tstruct cvmx_smix_rd_dat_s cn52xx;\n+\tstruct cvmx_smix_rd_dat_s cn52xxp1;\n+\tstruct cvmx_smix_rd_dat_s cn56xx;\n+\tstruct cvmx_smix_rd_dat_s cn56xxp1;\n+\tstruct cvmx_smix_rd_dat_s cn58xx;\n+\tstruct cvmx_smix_rd_dat_s cn58xxp1;\n+\tstruct cvmx_smix_rd_dat_s cn61xx;\n+\tstruct cvmx_smix_rd_dat_s cn63xx;\n+\tstruct cvmx_smix_rd_dat_s cn63xxp1;\n+\tstruct cvmx_smix_rd_dat_s cn66xx;\n+\tstruct cvmx_smix_rd_dat_s cn68xx;\n+\tstruct cvmx_smix_rd_dat_s cn68xxp1;\n+\tstruct cvmx_smix_rd_dat_s cn70xx;\n+\tstruct cvmx_smix_rd_dat_s cn70xxp1;\n+\tstruct cvmx_smix_rd_dat_s cn73xx;\n+\tstruct cvmx_smix_rd_dat_s cn78xx;\n+\tstruct cvmx_smix_rd_dat_s cn78xxp1;\n+\tstruct cvmx_smix_rd_dat_s cnf71xx;\n+\tstruct cvmx_smix_rd_dat_s cnf75xx;\n+};\n+\n+typedef union cvmx_smix_rd_dat cvmx_smix_rd_dat_t;\n+\n+/**\n+ * cvmx_smi#_wr_dat\n+ *\n+ * This register provides the data for a write operation.\n+ *\n+ */\n+union cvmx_smix_wr_dat {\n+\tu64 u64;\n+\tstruct cvmx_smix_wr_dat_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 pending : 1;\n+\t\tu64 val : 1;\n+\t\tu64 dat : 16;\n+\t} s;\n+\tstruct cvmx_smix_wr_dat_s cn30xx;\n+\tstruct cvmx_smix_wr_dat_s cn31xx;\n+\tstruct cvmx_smix_wr_dat_s cn38xx;\n+\tstruct cvmx_smix_wr_dat_s cn38xxp2;\n+\tstruct cvmx_smix_wr_dat_s cn50xx;\n+\tstruct cvmx_smix_wr_dat_s cn52xx;\n+\tstruct cvmx_smix_wr_dat_s cn52xxp1;\n+\tstruct cvmx_smix_wr_dat_s cn56xx;\n+\tstruct cvmx_smix_wr_dat_s cn56xxp1;\n+\tstruct cvmx_smix_wr_dat_s cn58xx;\n+\tstruct cvmx_smix_wr_dat_s cn58xxp1;\n+\tstruct cvmx_smix_wr_dat_s cn61xx;\n+\tstruct cvmx_smix_wr_dat_s cn63xx;\n+\tstruct cvmx_smix_wr_dat_s cn63xxp1;\n+\tstruct cvmx_smix_wr_dat_s cn66xx;\n+\tstruct cvmx_smix_wr_dat_s cn68xx;\n+\tstruct cvmx_smix_wr_dat_s cn68xxp1;\n+\tstruct cvmx_smix_wr_dat_s cn70xx;\n+\tstruct cvmx_smix_wr_dat_s cn70xxp1;\n+\tstruct cvmx_smix_wr_dat_s cn73xx;\n+\tstruct cvmx_smix_wr_dat_s cn78xx;\n+\tstruct cvmx_smix_wr_dat_s cn78xxp1;\n+\tstruct cvmx_smix_wr_dat_s cnf71xx;\n+\tstruct cvmx_smix_wr_dat_s cnf75xx;\n+};\n+\n+typedef union cvmx_smix_wr_dat cvmx_smix_wr_dat_t;\n+\n+#endif\n", "prefixes": [ "v1", "29/50" ] }