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GET /api/patches/1414995/?format=api
{ "id": 1414995, "url": "http://patchwork.ozlabs.org/api/patches/1414995/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-31-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-31-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:52", "name": "[v1,30/50] mips: octeon: Add cvmx-sriomaintx-defs.h header file", "commit_ref": "1374315375f40141f51896c10716179acdf4361c", "pull_url": null, "state": "accepted", "archived": false, "hash": "d4712bfc2705b428c77886e69f4488cc051b66aa", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-31-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1414995/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1414995/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=S2vBPBbX;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4Cswj31VzBz9sSs\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:09:43 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 5C32F82790;\n\tFri, 11 Dec 2020 17:07:28 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id E88B58278C; Fri, 11 Dec 2020 17:07:10 +0100 (CET)", "from mx2.mailbox.org (mx2.mailbox.org [80.241.60.215])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id F276B8266B\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:25 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id 87CF9A01AD;\n Fri, 11 Dec 2020 17:06:25 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter06.heinlein-hosting.de (spamfilter06.heinlein-hosting.de\n [80.241.56.125]) (amavisd-new, port 10030)\n with ESMTP id jq1mdcvOUQ58; Fri, 11 Dec 2020 17:06:22 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702848;\n\tbh=YIkGYC53vbolESNAa719afVv87pHuKJrrTUpp3vUPLI=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=S2vBPBbXGklfBh+bE4ARDVh5DjMtsENFdBWC8obWUTcKx5haRcXe8voD/CFstg4Je\n\t hw9yX/RYcIf5WfNYmrHUFflwHwaHoFp5wZgsb40Z/iLbD3oyr7SvjmYi9AbDdebbVX\n\t woosZ7DcwK0oewVhou4Xl37ozFVWcXXOvS/Rfs1wB3ypLRCcbv2QssmQ7vIF/Tzhwk\n\t 4+SJ7XGlFi3Z11FwtxltrLr3I6TdA3tcJhrvxnXPG2c81/Gbg5FwapxzQqe+QnqZiZ\n\t OsqYO5v6jCkMm9mWBSZ0SC0lSQ7qex4UwbReNhYLk4l04VsODllnvDs8eTxvIwMxo8\n\t whL85TMnzz95g==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 30/50] mips: octeon: Add cvmx-sriomaintx-defs.h header file", "Date": "Fri, 11 Dec 2020 17:05:52 +0100", "Message-Id": "<20201211160612.1498780-31-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-0.74 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "887861878", "X-Rspamd-UID": "ef5274", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-sriomaintx-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../include/mach/cvmx-sriomaintx-defs.h | 61 +++++++++++++++++++\n 1 file changed, 61 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-sriomaintx-defs.h", "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-sriomaintx-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-sriomaintx-defs.h\nnew file mode 100644\nindex 0000000000..2558e7b2fd\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-sriomaintx-defs.h\n@@ -0,0 +1,61 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ */\n+\n+#ifndef __CVMX_SRIOMAINTX_DEFS_H__\n+#define __CVMX_SRIOMAINTX_DEFS_H__\n+\n+static inline u64 CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000010000000154ull + (offset) * 0x100000000ull;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000154ull;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0000000000000154ull + (offset) * 0x100000000ull;\n+\t}\n+\treturn 0x0000010000000154ull + (offset) * 0x100000000ull;\n+}\n+\n+/**\n+ * cvmx_sriomaint#_port_0_ctl2\n+ *\n+ * These registers are accessed when a local processor or an external\n+ * device wishes to examine the port baudrate information. The automatic\n+ * baud rate feature is not available on this device. The SUP_* and ENB_*\n+ * fields are set directly by the SRIO()_STATUS_REG[SPD] bits as a\n+ * reference but otherwise have no effect.\n+ *\n+ * WARNING!! Writes to this register will reinitialize the SRIO link.\n+ */\n+union cvmx_sriomaintx_port_0_ctl2 {\n+\tu32 u32;\n+\tstruct cvmx_sriomaintx_port_0_ctl2_s {\n+\t\tu32 sel_baud : 4;\n+\t\tu32 baud_sup : 1;\n+\t\tu32 baud_enb : 1;\n+\t\tu32 sup_125g : 1;\n+\t\tu32 enb_125g : 1;\n+\t\tu32 sup_250g : 1;\n+\t\tu32 enb_250g : 1;\n+\t\tu32 sup_312g : 1;\n+\t\tu32 enb_312g : 1;\n+\t\tu32 sub_500g : 1;\n+\t\tu32 enb_500g : 1;\n+\t\tu32 sup_625g : 1;\n+\t\tu32 enb_625g : 1;\n+\t\tu32 reserved_2_15 : 14;\n+\t\tu32 tx_emph : 1;\n+\t\tu32 emph_en : 1;\n+\t} s;\n+\tstruct cvmx_sriomaintx_port_0_ctl2_s cn63xx;\n+\tstruct cvmx_sriomaintx_port_0_ctl2_s cn63xxp1;\n+\tstruct cvmx_sriomaintx_port_0_ctl2_s cn66xx;\n+\tstruct cvmx_sriomaintx_port_0_ctl2_s cnf75xx;\n+};\n+\n+typedef union cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_ctl2_t;\n+\n+#endif\n", "prefixes": [ "v1", "30/50" ] }