Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1414994/?format=api
{ "id": 1414994, "url": "http://patchwork.ozlabs.org/api/patches/1414994/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-28-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-28-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:49", "name": "[v1,27/50] mips: octeon: Add cvmx-sata-defs.h header file", "commit_ref": "0e686b39d54bc8dff5d56f45f06e871c108fd0ef", "pull_url": null, "state": "accepted", "archived": false, "hash": "95bdf79f70548e45a337be6b3c48282edc9104eb", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-28-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1414994/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1414994/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=wI8JpHeH;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4Cswhm2BMsz9sSs\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:09:28 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 4E5BE82745;\n\tFri, 11 Dec 2020 17:07:25 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 278AC82679; Fri, 11 Dec 2020 17:07:09 +0100 (CET)", "from mx2.mailbox.org (mx2a.mailbox.org\n [IPv6:2001:67c:2050:104:0:2:25:2])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id C5EF082679\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:25 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org\n [IPv6:2001:67c:2050:105:465:1:1:0])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id 0902BA0118;\n Fri, 11 Dec 2020 17:06:25 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter03.heinlein-hosting.de (spamfilter03.heinlein-hosting.de\n [80.241.56.117]) (amavisd-new, port 10030)\n with ESMTP id z91wXVSN729S; Fri, 11 Dec 2020 17:06:21 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702845;\n\tbh=iKn28x1Dj0d3oZY76pe4Slilbt1zwE8YbGMAVRsEWL4=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=wI8JpHeHZ6f/wqvrYxlhsiWeLxBdzrXzYiej3e/DQnloqkqnwIma88OX9AoAHAOOx\n\t uDtfXqGBz9m49765jB7gXjgqLtABXXKExmg3JO64hg5roR+/Nuoq3JG+37jwBR+ODl\n\t 7IbMG2kGrN8CTryRvHcZDSO9/2y3cQoIKV4HDti3r3OeMGL5f3X4Iau5IONML6sSdf\n\t 8OvTCylhkwHzfm0YQ/fZ2UatU8RvtrErW4lUxwUNoAWcRWPEdn4BFuE6Ea8lYaQCQE\n\t 2Za3BzVw9bb1CkBjVmamlbEMcXRkGxjx6xJNi2cRm4s9kqfF0d1jnNxorAtXRK30uU\n\t oKMrHc0sMea7g==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 27/50] mips: octeon: Add cvmx-sata-defs.h header file", "Date": "Fri, 11 Dec 2020 17:05:49 +0100", "Message-Id": "<20201211160612.1498780-28-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-0.48 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "11DD6187A", "X-Rspamd-UID": "93e49e", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-sata-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-sata-defs.h | 311 ++++++++++++++++++\n 1 file changed, 311 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-sata-defs.h", "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-sata-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-sata-defs.h\nnew file mode 100644\nindex 0000000000..77af0e3f83\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-sata-defs.h\n@@ -0,0 +1,311 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ */\n+\n+#ifndef __CVMX_SATA_DEFS_H__\n+#define __CVMX_SATA_DEFS_H__\n+\n+#define CVMX_SATA_UCTL_CTL\t (0x000118006C000000ull)\n+#define CVMX_SATA_UCTL_SHIM_CFG\t (0x000118006C0000E8ull)\n+#define CVMX_SATA_UCTL_BIST_STATUS (0x000118006C000008ull)\n+\n+#define CVMX_SATA_UAHC_GBL_PI\t (0x00016C000000000Cull)\n+#define CVMX_SATA_UAHC_GBL_TIMER1MS (0x00016C00000000E0ull)\n+#define CVMX_SATA_UAHC_GBL_CAP\t (0x00016C0000000000ull)\n+\n+#define CVMX_SATA_UAHC_PX_CMD(offset) (0x00016C0000000118ull + ((offset) & 1) * 128)\n+#define CVMX_SATA_UAHC_PX_SCTL(offset) (0x00016C000000012Cull + ((offset) & 1) * 128)\n+#define CVMX_SATA_UAHC_PX_SERR(offset) (0x00016C0000000130ull + ((offset) & 1) * 128)\n+#define CVMX_SATA_UAHC_PX_IS(offset) (0x00016C0000000110ull + ((offset) & 1) * 128)\n+#define CVMX_SATA_UAHC_PX_SSTS(offset) (0x00016C0000000128ull + ((offset) & 1) * 128)\n+#define CVMX_SATA_UAHC_PX_TFD(offset) (0x00016C0000000120ull + ((offset) & 1) * 128)\n+\n+/**\n+ * cvmx_sata_uctl_ctl\n+ *\n+ * This register controls clocks, resets, power, and BIST for the SATA.\n+ *\n+ * Accessible always.\n+ *\n+ * Reset by IOI reset.\n+ */\n+union cvmx_sata_uctl_ctl {\n+\tu64 u64;\n+\tstruct cvmx_sata_uctl_ctl_s {\n+\t\tu64 clear_bist : 1;\n+\t\tu64 start_bist : 1;\n+\t\tu64 reserved_31_61 : 31;\n+\t\tu64 a_clk_en : 1;\n+\t\tu64 a_clk_byp_sel : 1;\n+\t\tu64 a_clkdiv_rst : 1;\n+\t\tu64 reserved_27_27 : 1;\n+\t\tu64 a_clkdiv_sel : 3;\n+\t\tu64 reserved_5_23 : 19;\n+\t\tu64 csclk_en : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 sata_uahc_rst : 1;\n+\t\tu64 sata_uctl_rst : 1;\n+\t} s;\n+\tstruct cvmx_sata_uctl_ctl_s cn70xx;\n+\tstruct cvmx_sata_uctl_ctl_s cn70xxp1;\n+\tstruct cvmx_sata_uctl_ctl_s cn73xx;\n+};\n+\n+typedef union cvmx_sata_uctl_ctl cvmx_sata_uctl_ctl_t;\n+\n+/**\n+ * cvmx_sata_uctl_bist_status\n+ *\n+ * Results from BIST runs of SATA's memories.\n+ * Wait for NDONE==0, then look at defect indication.\n+ *\n+ * Accessible always.\n+ *\n+ * Reset by IOI reset.\n+ */\n+union cvmx_sata_uctl_bist_status {\n+\tu64 u64;\n+\tstruct cvmx_sata_uctl_bist_status_s {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 uctl_xm_r_bist_ndone : 1;\n+\t\tu64 uctl_xm_w_bist_ndone : 1;\n+\t\tu64 reserved_36_39 : 4;\n+\t\tu64 uahc_p0_rxram_bist_ndone : 1;\n+\t\tu64 uahc_p1_rxram_bist_ndone : 1;\n+\t\tu64 uahc_p0_txram_bist_ndone : 1;\n+\t\tu64 uahc_p1_txram_bist_ndone : 1;\n+\t\tu64 reserved_10_31 : 22;\n+\t\tu64 uctl_xm_r_bist_status : 1;\n+\t\tu64 uctl_xm_w_bist_status : 1;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 uahc_p0_rxram_bist_status : 1;\n+\t\tu64 uahc_p1_rxram_bist_status : 1;\n+\t\tu64 uahc_p0_txram_bist_status : 1;\n+\t\tu64 uahc_p1_txram_bist_status : 1;\n+\t} s;\n+\tstruct cvmx_sata_uctl_bist_status_s cn70xx;\n+\tstruct cvmx_sata_uctl_bist_status_s cn70xxp1;\n+\tstruct cvmx_sata_uctl_bist_status_s cn73xx;\n+};\n+\n+typedef union cvmx_sata_uctl_bist_status cvmx_sata_uctl_bist_status_t;\n+\n+/**\n+ * cvmx_sata_uctl_shim_cfg\n+ *\n+ * This register allows configuration of various shim (UCTL) features.\n+ *\n+ * Fields XS_NCB_OOB_* are captured when there are no outstanding OOB errors indicated in INTSTAT\n+ * and a new OOB error arrives.\n+ *\n+ * Fields XS_BAD_DMA_* are captured when there are no outstanding DMA errors indicated in INTSTAT\n+ * and a new DMA error arrives.\n+ *\n+ * Accessible only when SATA_UCTL_CTL[A_CLK_EN].\n+ *\n+ * Reset by IOI reset or SATA_UCTL_CTL[SATA_UCTL_RST].\n+ */\n+union cvmx_sata_uctl_shim_cfg {\n+\tu64 u64;\n+\tstruct cvmx_sata_uctl_shim_cfg_s {\n+\t\tu64 xs_ncb_oob_wrn : 1;\n+\t\tu64 reserved_60_62 : 3;\n+\t\tu64 xs_ncb_oob_osrc : 12;\n+\t\tu64 xm_bad_dma_wrn : 1;\n+\t\tu64 reserved_44_46 : 3;\n+\t\tu64 xm_bad_dma_type : 4;\n+\t\tu64 reserved_14_39 : 26;\n+\t\tu64 dma_read_cmd : 2;\n+\t\tu64 reserved_11_11 : 1;\n+\t\tu64 dma_write_cmd : 1;\n+\t\tu64 dma_endian_mode : 2;\n+\t\tu64 reserved_2_7 : 6;\n+\t\tu64 csr_endian_mode : 2;\n+\t} s;\n+\tstruct cvmx_sata_uctl_shim_cfg_cn70xx {\n+\t\tu64 xs_ncb_oob_wrn : 1;\n+\t\tu64 reserved_57_62 : 6;\n+\t\tu64 xs_ncb_oob_osrc : 9;\n+\t\tu64 xm_bad_dma_wrn : 1;\n+\t\tu64 reserved_44_46 : 3;\n+\t\tu64 xm_bad_dma_type : 4;\n+\t\tu64 reserved_13_39 : 27;\n+\t\tu64 dma_read_cmd : 1;\n+\t\tu64 reserved_10_11 : 2;\n+\t\tu64 dma_endian_mode : 2;\n+\t\tu64 reserved_2_7 : 6;\n+\t\tu64 csr_endian_mode : 2;\n+\t} cn70xx;\n+\tstruct cvmx_sata_uctl_shim_cfg_cn70xx cn70xxp1;\n+\tstruct cvmx_sata_uctl_shim_cfg_s cn73xx;\n+};\n+\n+typedef union cvmx_sata_uctl_shim_cfg cvmx_sata_uctl_shim_cfg_t;\n+\n+/**\n+ * cvmx_sata_uahc_gbl_cap\n+ *\n+ * See AHCI specification v1.3 section 3.1\n+ *\n+ */\n+union cvmx_sata_uahc_gbl_cap {\n+\tu32 u32;\n+\tstruct cvmx_sata_uahc_gbl_cap_s {\n+\t\tu32 s64a : 1;\n+\t\tu32 sncq : 1;\n+\t\tu32 ssntf : 1;\n+\t\tu32 smps : 1;\n+\t\tu32 sss : 1;\n+\t\tu32 salp : 1;\n+\t\tu32 sal : 1;\n+\t\tu32 sclo : 1;\n+\t\tu32 iss : 4;\n+\t\tu32 snzo : 1;\n+\t\tu32 sam : 1;\n+\t\tu32 spm : 1;\n+\t\tu32 fbss : 1;\n+\t\tu32 pmd : 1;\n+\t\tu32 ssc : 1;\n+\t\tu32 psc : 1;\n+\t\tu32 ncs : 5;\n+\t\tu32 cccs : 1;\n+\t\tu32 ems : 1;\n+\t\tu32 sxs : 1;\n+\t\tu32 np : 5;\n+\t} s;\n+\tstruct cvmx_sata_uahc_gbl_cap_s cn70xx;\n+\tstruct cvmx_sata_uahc_gbl_cap_s cn70xxp1;\n+\tstruct cvmx_sata_uahc_gbl_cap_s cn73xx;\n+};\n+\n+typedef union cvmx_sata_uahc_gbl_cap cvmx_sata_uahc_gbl_cap_t;\n+\n+/**\n+ * cvmx_sata_uahc_p#_sctl\n+ */\n+union cvmx_sata_uahc_px_sctl {\n+\tu32 u32;\n+\tstruct cvmx_sata_uahc_px_sctl_s {\n+\t\tu32 reserved_10_31 : 22;\n+\t\tu32 ipm : 2;\n+\t\tu32 reserved_6_7 : 2;\n+\t\tu32 spd : 2;\n+\t\tu32 reserved_3_3 : 1;\n+\t\tu32 det : 3;\n+\t} s;\n+\tstruct cvmx_sata_uahc_px_sctl_s cn70xx;\n+\tstruct cvmx_sata_uahc_px_sctl_s cn70xxp1;\n+\tstruct cvmx_sata_uahc_px_sctl_s cn73xx;\n+};\n+\n+typedef union cvmx_sata_uahc_px_sctl cvmx_sata_uahc_px_sctl_t;\n+\n+/**\n+ * cvmx_sata_uahc_p#_cmd\n+ */\n+union cvmx_sata_uahc_px_cmd {\n+\tu32 u32;\n+\tstruct cvmx_sata_uahc_px_cmd_s {\n+\t\tu32 icc : 4;\n+\t\tu32 asp : 1;\n+\t\tu32 alpe : 1;\n+\t\tu32 dlae : 1;\n+\t\tu32 atapi : 1;\n+\t\tu32 apste : 1;\n+\t\tu32 fbscp : 1;\n+\t\tu32 esp : 1;\n+\t\tu32 cpd : 1;\n+\t\tu32 mpsp : 1;\n+\t\tu32 hpcp : 1;\n+\t\tu32 pma : 1;\n+\t\tu32 cps : 1;\n+\t\tu32 cr : 1;\n+\t\tu32 fr : 1;\n+\t\tu32 mpss : 1;\n+\t\tu32 ccs : 5;\n+\t\tu32 reserved_5_7 : 3;\n+\t\tu32 fre : 1;\n+\t\tu32 clo : 1;\n+\t\tu32 pod : 1;\n+\t\tu32 sud : 1;\n+\t\tu32 st : 1;\n+\t} s;\n+\tstruct cvmx_sata_uahc_px_cmd_s cn70xx;\n+\tstruct cvmx_sata_uahc_px_cmd_s cn70xxp1;\n+\tstruct cvmx_sata_uahc_px_cmd_s cn73xx;\n+};\n+\n+typedef union cvmx_sata_uahc_px_cmd cvmx_sata_uahc_px_cmd_t;\n+\n+/**\n+ * cvmx_sata_uahc_gbl_pi\n+ *\n+ * See AHCI specification v1.3 section 3.1.\n+ *\n+ */\n+union cvmx_sata_uahc_gbl_pi {\n+\tu32 u32;\n+\tstruct cvmx_sata_uahc_gbl_pi_s {\n+\t\tu32 reserved_2_31 : 30;\n+\t\tu32 pi : 2;\n+\t} s;\n+\tstruct cvmx_sata_uahc_gbl_pi_s cn70xx;\n+\tstruct cvmx_sata_uahc_gbl_pi_s cn70xxp1;\n+\tstruct cvmx_sata_uahc_gbl_pi_s cn73xx;\n+};\n+\n+typedef union cvmx_sata_uahc_gbl_pi cvmx_sata_uahc_gbl_pi_t;\n+\n+/**\n+ * cvmx_sata_uahc_p#_ssts\n+ */\n+union cvmx_sata_uahc_px_ssts {\n+\tu32 u32;\n+\tstruct cvmx_sata_uahc_px_ssts_s {\n+\t\tu32 reserved_12_31 : 20;\n+\t\tu32 ipm : 4;\n+\t\tu32 spd : 4;\n+\t\tu32 det : 4;\n+\t} s;\n+\tstruct cvmx_sata_uahc_px_ssts_s cn70xx;\n+\tstruct cvmx_sata_uahc_px_ssts_s cn70xxp1;\n+\tstruct cvmx_sata_uahc_px_ssts_s cn73xx;\n+};\n+\n+typedef union cvmx_sata_uahc_px_ssts cvmx_sata_uahc_px_ssts_t;\n+\n+/**\n+ * cvmx_sata_uahc_p#_tfd\n+ */\n+union cvmx_sata_uahc_px_tfd {\n+\tu32 u32;\n+\tstruct cvmx_sata_uahc_px_tfd_s {\n+\t\tu32 reserved_16_31 : 16;\n+\t\tu32 tferr : 8;\n+\t\tu32 sts : 8;\n+\t} s;\n+\tstruct cvmx_sata_uahc_px_tfd_s cn70xx;\n+\tstruct cvmx_sata_uahc_px_tfd_s cn70xxp1;\n+\tstruct cvmx_sata_uahc_px_tfd_s cn73xx;\n+};\n+\n+typedef union cvmx_sata_uahc_px_tfd cvmx_sata_uahc_px_tfd_t;\n+\n+/**\n+ * cvmx_sata_uahc_gbl_timer1ms\n+ */\n+union cvmx_sata_uahc_gbl_timer1ms {\n+\tu32 u32;\n+\tstruct cvmx_sata_uahc_gbl_timer1ms_s {\n+\t\tu32 reserved_20_31 : 12;\n+\t\tu32 timv : 20;\n+\t} s;\n+\tstruct cvmx_sata_uahc_gbl_timer1ms_s cn70xx;\n+\tstruct cvmx_sata_uahc_gbl_timer1ms_s cn70xxp1;\n+\tstruct cvmx_sata_uahc_gbl_timer1ms_s cn73xx;\n+};\n+\n+typedef union cvmx_sata_uahc_gbl_timer1ms cvmx_sata_uahc_gbl_timer1ms_t;\n+\n+#endif\n", "prefixes": [ "v1", "27/50" ] }