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GET /api/patches/1414992/?format=api
{ "id": 1414992, "url": "http://patchwork.ozlabs.org/api/patches/1414992/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-21-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-21-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:42", "name": "[v1,20/50] mips: octeon: Add cvmx-pemx-defs.h header file", "commit_ref": "8f8383880f9bb58664a6afa459dfdc0c8750d5d6", "pull_url": null, "state": "accepted", "archived": false, "hash": "d91df5ef13d0144df129e469db4c79a1ff0ac40b", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-21-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1414992/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1414992/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=ic74yZJT;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4Cswh92Xs7z9sSs\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:08:57 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id D21BF826A6;\n\tFri, 11 Dec 2020 17:07:13 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 58AC082785; Fri, 11 Dec 2020 17:07:01 +0100 (CET)", "from mx2.mailbox.org (mx2a.mailbox.org\n [IPv6:2001:67c:2050:104:0:2:25:2])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id A7ED0826D2\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:24 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id 42289A0BDC;\n Fri, 11 Dec 2020 17:06:24 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter04.heinlein-hosting.de (spamfilter04.heinlein-hosting.de\n [80.241.56.122]) (amavisd-new, port 10030)\n with ESMTP id YOCXY4BKuyDt; Fri, 11 Dec 2020 17:06:19 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702834;\n\tbh=3D2zygLzCoIFA6AHwTUT+OZut0xVIMxDq5MBqQ8VYaQ=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=ic74yZJTVjPRPdvyWPyddOXmLnIDt1eeHupqFi9ZS8oDmnvZ31IIh04/9JSuPCW4b\n\t WWKv7eBGvCesncWM1JFdZSUdY7trqUQDDIvxyJxB3aYIFovJeSDn2rEGUr0gIQAvWR\n\t F3tS4iprAkduESZ1WE5eIrIK7rAYN7fKZ4ycmG9UK/xIl/Z5ZgtWRlhP1NAPz3eHAy\n\t Gm6QxVqvP1eDdGiiRyTDmuYlz8rYoPu2ACbg7Kl8A1i7ZDqFLeEeVVL3vT71m1mpcT\n\t UAvXwp3OCO9HlHty5ZpvkoLBZEVNH+3qY5NJd3rAmvkJfyHVANG3MKG98jwkgl6/EO\n\t 9hRbt1nLohkeQ==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 20/50] mips: octeon: Add cvmx-pemx-defs.h header file", "Date": "Fri, 11 Dec 2020 17:05:42 +0100", "Message-Id": "<20201211160612.1498780-21-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-0.76 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "349AD1887", "X-Rspamd-UID": "cfd499", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-pemx-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-pemx-defs.h | 2028 +++++++++++++++++\n 1 file changed, 2028 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pemx-defs.h", "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pemx-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-pemx-defs.h\nnew file mode 100644\nindex 0000000000..9ec7a4b67c\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-pemx-defs.h\n@@ -0,0 +1,2028 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon pemx.\n+ */\n+\n+#ifndef __CVMX_PEMX_DEFS_H__\n+#define __CVMX_PEMX_DEFS_H__\n+\n+static inline u64 CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long block_id)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C00000A8ull + ((offset) + (block_id) * 0x200000ull) * 8;\n+\t}\n+\treturn 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8;\n+}\n+\n+static inline u64 CVMX_PEMX_BAR2_MASK(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C00000B0ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C00000B0ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800C00000B0ull + (offset) * 0x1000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800C00000B0ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C10000B0ull + (offset) * 0x1000000ull - 16777216 * 1;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000130ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800C00000B0ull + (offset) * 0x1000000ull;\n+}\n+\n+static inline u64 CVMX_PEMX_BAR_CTL(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C00000A8ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C00000A8ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800C00000A8ull + (offset) * 0x1000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800C00000A8ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C10000A8ull + (offset) * 0x1000000ull - 16777216 * 1;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000128ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800C00000A8ull + (offset) * 0x1000000ull;\n+}\n+\n+static inline u64 CVMX_PEMX_BIST_STATUS(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000018ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000018ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000440ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800C0000440ull + (offset) * 0x1000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800C0000440ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C1000440ull + (offset) * 0x1000000ull - 16777216 * 1;\n+\t}\n+\treturn 0x00011800C0000440ull + (offset) * 0x1000000ull;\n+}\n+\n+static inline u64 CVMX_PEMX_BIST_STATUS2(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000420ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000440ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800C0000420ull + (offset) * 0x1000000ull;\n+}\n+\n+#define CVMX_PEMX_CFG(offset)\t\t(0x00011800C0000410ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_CFG_RD(offset)\t(0x00011800C0000030ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_CFG_WR(offset)\t(0x00011800C0000028ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_CLK_EN(offset)\t(0x00011800C0000400ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_CPL_LUT_VALID(offset) (0x00011800C0000098ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_CTL_STATUS(offset)\t(0x00011800C0000000ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_CTL_STATUS2(offset)\t(0x00011800C0000008ull + ((offset) & 3) * 0x1000000ull)\n+static inline u64 CVMX_PEMX_DBG_INFO(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C00000D0ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C00000D0ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800C00000D0ull + (offset) * 0x1000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800C00000D0ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C10000D0ull + (offset) * 0x1000000ull - 16777216 * 1;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000008ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800C00000D0ull + (offset) * 0x1000000ull;\n+}\n+\n+#define CVMX_PEMX_DBG_INFO_EN(offset) (0x00011800C00000A0ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_DIAG_STATUS(offset) (0x00011800C0000020ull + ((offset) & 3) * 0x1000000ull)\n+static inline u64 CVMX_PEMX_ECC_ENA(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000448ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800C0000448ull + (offset) * 0x1000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800C0000448ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C1000448ull + (offset) * 0x1000000ull - 16777216 * 1;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C00000C0ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800C0000448ull + (offset) * 0x1000000ull;\n+}\n+\n+static inline u64 CVMX_PEMX_ECC_SYND_CTRL(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000450ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800C0000450ull + (offset) * 0x1000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800C0000450ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C1000450ull + (offset) * 0x1000000ull - 16777216 * 1;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C00000C8ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800C0000450ull + (offset) * 0x1000000ull;\n+}\n+\n+#define CVMX_PEMX_ECO(offset)\t\t (0x00011800C0000010ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_FLR_GLBLCNT_CTL(offset) (0x00011800C0000210ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_FLR_PF0_VF_STOPREQ(offset) (0x00011800C0000220ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_FLR_PF_STOPREQ(offset) (0x00011800C0000218ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_FLR_STOPREQ_CTL(offset) (0x00011800C0000238ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_FLR_ZOMBIE_CTL(offset) (0x00011800C0000230ull + ((offset) & 3) * 0x1000000ull)\n+static inline u64 CVMX_PEMX_INB_READ_CREDITS(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C00000B8ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C00000B8ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800C00000B8ull + (offset) * 0x1000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800C00000B8ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C10000B8ull + (offset) * 0x1000000ull - 16777216 * 1;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000138ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800C00000B8ull + (offset) * 0x1000000ull;\n+}\n+\n+static inline u64 CVMX_PEMX_INT_ENB(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000410ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000430ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800C0000410ull + (offset) * 0x1000000ull;\n+}\n+\n+static inline u64 CVMX_PEMX_INT_ENB_INT(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000418ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000438ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800C0000418ull + (offset) * 0x1000000ull;\n+}\n+\n+static inline u64 CVMX_PEMX_INT_SUM(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000428ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000428ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00011800C0000428ull + (offset) * 0x1000000ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00011800C0000428ull + (offset) * 0x1000000ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C1000428ull + (offset) * 0x1000000ull - 16777216 * 1;\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800C0000408ull + (offset) * 0x1000000ull;\n+\t}\n+\treturn 0x00011800C0000428ull + (offset) * 0x1000000ull;\n+}\n+\n+#define CVMX_PEMX_ON(offset)\t\t (0x00011800C0000420ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_P2N_BAR0_START(offset) (0x00011800C0000080ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_P2N_BAR1_START(offset) (0x00011800C0000088ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_P2N_BAR2_START(offset) (0x00011800C0000090ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_P2P_BARX_END(offset, block_id) \\\n+\t(0x00011800C0000048ull + (((offset) & 3) + ((block_id) & 3) * 0x100000ull) * 16)\n+#define CVMX_PEMX_P2P_BARX_START(offset, block_id) \\\n+\t(0x00011800C0000040ull + (((offset) & 3) + ((block_id) & 3) * 0x100000ull) * 16)\n+#define CVMX_PEMX_QLM(offset)\t (0x00011800C0000418ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_SPI_CTL(offset) (0x00011800C0000180ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_SPI_DATA(offset) (0x00011800C0000188ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_STRAP(offset)\t (0x00011800C0000408ull + ((offset) & 3) * 0x1000000ull)\n+#define CVMX_PEMX_TLP_CREDITS(offset) (0x00011800C0000038ull + ((offset) & 3) * 0x1000000ull)\n+\n+/**\n+ * cvmx_pem#_bar1_index#\n+ *\n+ * This register contains the address index and control bits for access to memory ranges of BAR1.\n+ * The index is built from supplied address [25:22].\n+ */\n+union cvmx_pemx_bar1_indexx {\n+\tu64 u64;\n+\tstruct cvmx_pemx_bar1_indexx_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 addr_idx : 20;\n+\t\tu64 ca : 1;\n+\t\tu64 end_swp : 2;\n+\t\tu64 addr_v : 1;\n+\t} s;\n+\tstruct cvmx_pemx_bar1_indexx_cn61xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 addr_idx : 16;\n+\t\tu64 ca : 1;\n+\t\tu64 end_swp : 2;\n+\t\tu64 addr_v : 1;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_bar1_indexx_cn61xx cn63xx;\n+\tstruct cvmx_pemx_bar1_indexx_cn61xx cn63xxp1;\n+\tstruct cvmx_pemx_bar1_indexx_cn61xx cn66xx;\n+\tstruct cvmx_pemx_bar1_indexx_cn61xx cn68xx;\n+\tstruct cvmx_pemx_bar1_indexx_cn61xx cn68xxp1;\n+\tstruct cvmx_pemx_bar1_indexx_s cn70xx;\n+\tstruct cvmx_pemx_bar1_indexx_s cn70xxp1;\n+\tstruct cvmx_pemx_bar1_indexx_s cn73xx;\n+\tstruct cvmx_pemx_bar1_indexx_s cn78xx;\n+\tstruct cvmx_pemx_bar1_indexx_s cn78xxp1;\n+\tstruct cvmx_pemx_bar1_indexx_cn61xx cnf71xx;\n+\tstruct cvmx_pemx_bar1_indexx_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_bar1_indexx cvmx_pemx_bar1_indexx_t;\n+\n+/**\n+ * cvmx_pem#_bar2_mask\n+ *\n+ * This register contains the mask pattern that is ANDed with the address from the PCIe core for\n+ * BAR2 hits. This allows the effective size of RC BAR2 to be shrunk. Must not be changed\n+ * from its reset value in EP mode.\n+ */\n+union cvmx_pemx_bar2_mask {\n+\tu64 u64;\n+\tstruct cvmx_pemx_bar2_mask_s {\n+\t\tu64 reserved_45_63 : 19;\n+\t\tu64 mask : 42;\n+\t\tu64 reserved_0_2 : 3;\n+\t} s;\n+\tstruct cvmx_pemx_bar2_mask_cn61xx {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 mask : 35;\n+\t\tu64 reserved_0_2 : 3;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_bar2_mask_cn61xx cn66xx;\n+\tstruct cvmx_pemx_bar2_mask_cn61xx cn68xx;\n+\tstruct cvmx_pemx_bar2_mask_cn61xx cn68xxp1;\n+\tstruct cvmx_pemx_bar2_mask_cn61xx cn70xx;\n+\tstruct cvmx_pemx_bar2_mask_cn61xx cn70xxp1;\n+\tstruct cvmx_pemx_bar2_mask_cn73xx {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 mask : 39;\n+\t\tu64 reserved_0_2 : 3;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_bar2_mask_s cn78xx;\n+\tstruct cvmx_pemx_bar2_mask_cn73xx cn78xxp1;\n+\tstruct cvmx_pemx_bar2_mask_cn61xx cnf71xx;\n+\tstruct cvmx_pemx_bar2_mask_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_bar2_mask cvmx_pemx_bar2_mask_t;\n+\n+/**\n+ * cvmx_pem#_bar_ctl\n+ *\n+ * This register contains control for BAR accesses.\n+ *\n+ */\n+union cvmx_pemx_bar_ctl {\n+\tu64 u64;\n+\tstruct cvmx_pemx_bar_ctl_s {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 bar1_siz : 3;\n+\t\tu64 bar2_enb : 1;\n+\t\tu64 bar2_esx : 2;\n+\t\tu64 bar2_cax : 1;\n+\t} s;\n+\tstruct cvmx_pemx_bar_ctl_s cn61xx;\n+\tstruct cvmx_pemx_bar_ctl_s cn63xx;\n+\tstruct cvmx_pemx_bar_ctl_s cn63xxp1;\n+\tstruct cvmx_pemx_bar_ctl_s cn66xx;\n+\tstruct cvmx_pemx_bar_ctl_s cn68xx;\n+\tstruct cvmx_pemx_bar_ctl_s cn68xxp1;\n+\tstruct cvmx_pemx_bar_ctl_s cn70xx;\n+\tstruct cvmx_pemx_bar_ctl_s cn70xxp1;\n+\tstruct cvmx_pemx_bar_ctl_s cn73xx;\n+\tstruct cvmx_pemx_bar_ctl_s cn78xx;\n+\tstruct cvmx_pemx_bar_ctl_s cn78xxp1;\n+\tstruct cvmx_pemx_bar_ctl_s cnf71xx;\n+\tstruct cvmx_pemx_bar_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_bar_ctl cvmx_pemx_bar_ctl_t;\n+\n+/**\n+ * cvmx_pem#_bist_status\n+ *\n+ * This register contains results from BIST runs of PEM's memories.\n+ *\n+ */\n+union cvmx_pemx_bist_status {\n+\tu64 u64;\n+\tstruct cvmx_pemx_bist_status_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 retryc : 1;\n+\t\tu64 reserved_14_14 : 1;\n+\t\tu64 rqhdrb0 : 1;\n+\t\tu64 rqhdrb1 : 1;\n+\t\tu64 rqdatab0 : 1;\n+\t\tu64 rqdatab1 : 1;\n+\t\tu64 tlpn_d0 : 1;\n+\t\tu64 tlpn_d1 : 1;\n+\t\tu64 reserved_0_7 : 8;\n+\t} s;\n+\tstruct cvmx_pemx_bist_status_cn61xx {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 retry : 1;\n+\t\tu64 rqdata0 : 1;\n+\t\tu64 rqdata1 : 1;\n+\t\tu64 rqdata2 : 1;\n+\t\tu64 rqdata3 : 1;\n+\t\tu64 rqhdr1 : 1;\n+\t\tu64 rqhdr0 : 1;\n+\t\tu64 sot : 1;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_bist_status_cn61xx cn63xx;\n+\tstruct cvmx_pemx_bist_status_cn61xx cn63xxp1;\n+\tstruct cvmx_pemx_bist_status_cn61xx cn66xx;\n+\tstruct cvmx_pemx_bist_status_cn61xx cn68xx;\n+\tstruct cvmx_pemx_bist_status_cn61xx cn68xxp1;\n+\tstruct cvmx_pemx_bist_status_cn70xx {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 retry : 1;\n+\t\tu64 sot : 1;\n+\t\tu64 rqhdr0 : 1;\n+\t\tu64 rqhdr1 : 1;\n+\t\tu64 rqdata0 : 1;\n+\t\tu64 rqdata1 : 1;\n+\t} cn70xx;\n+\tstruct cvmx_pemx_bist_status_cn70xx cn70xxp1;\n+\tstruct cvmx_pemx_bist_status_cn73xx {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 retryc : 1;\n+\t\tu64 sot : 1;\n+\t\tu64 rqhdrb0 : 1;\n+\t\tu64 rqhdrb1 : 1;\n+\t\tu64 rqdatab0 : 1;\n+\t\tu64 rqdatab1 : 1;\n+\t\tu64 tlpn_d0 : 1;\n+\t\tu64 tlpn_d1 : 1;\n+\t\tu64 tlpn_ctl : 1;\n+\t\tu64 tlpp_d0 : 1;\n+\t\tu64 tlpp_d1 : 1;\n+\t\tu64 tlpp_ctl : 1;\n+\t\tu64 tlpc_d0 : 1;\n+\t\tu64 tlpc_d1 : 1;\n+\t\tu64 tlpc_ctl : 1;\n+\t\tu64 m2s : 1;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_bist_status_cn73xx cn78xx;\n+\tstruct cvmx_pemx_bist_status_cn73xx cn78xxp1;\n+\tstruct cvmx_pemx_bist_status_cn61xx cnf71xx;\n+\tstruct cvmx_pemx_bist_status_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_bist_status cvmx_pemx_bist_status_t;\n+\n+/**\n+ * cvmx_pem#_bist_status2\n+ *\n+ * \"PEM#_BIST_STATUS2 = PEM BIST Status Register\n+ * Results from BIST runs of PEM's memories.\"\n+ */\n+union cvmx_pemx_bist_status2 {\n+\tu64 u64;\n+\tstruct cvmx_pemx_bist_status2_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 tlpn_d : 1;\n+\t\tu64 tlpn_ctl : 1;\n+\t\tu64 tlpp_d : 1;\n+\t\tu64 reserved_0_9 : 10;\n+\t} s;\n+\tstruct cvmx_pemx_bist_status2_cn61xx {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 e2p_cpl : 1;\n+\t\tu64 e2p_n : 1;\n+\t\tu64 e2p_p : 1;\n+\t\tu64 peai_p2e : 1;\n+\t\tu64 pef_tpf1 : 1;\n+\t\tu64 pef_tpf0 : 1;\n+\t\tu64 pef_tnf : 1;\n+\t\tu64 pef_tcf1 : 1;\n+\t\tu64 pef_tc0 : 1;\n+\t\tu64 ppf : 1;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_bist_status2_cn61xx cn63xx;\n+\tstruct cvmx_pemx_bist_status2_cn61xx cn63xxp1;\n+\tstruct cvmx_pemx_bist_status2_cn61xx cn66xx;\n+\tstruct cvmx_pemx_bist_status2_cn61xx cn68xx;\n+\tstruct cvmx_pemx_bist_status2_cn61xx cn68xxp1;\n+\tstruct cvmx_pemx_bist_status2_cn70xx {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 peai_p2e : 1;\n+\t\tu64 tlpn_d : 1;\n+\t\tu64 tlpn_ctl : 1;\n+\t\tu64 tlpp_d : 1;\n+\t\tu64 tlpp_ctl : 1;\n+\t\tu64 tlpc_d : 1;\n+\t\tu64 tlpc_ctl : 1;\n+\t\tu64 tlpan_d : 1;\n+\t\tu64 tlpan_ctl : 1;\n+\t\tu64 tlpap_d : 1;\n+\t\tu64 tlpap_ctl : 1;\n+\t\tu64 tlpac_d : 1;\n+\t\tu64 tlpac_ctl : 1;\n+\t\tu64 m2s : 1;\n+\t} cn70xx;\n+\tstruct cvmx_pemx_bist_status2_cn70xx cn70xxp1;\n+\tstruct cvmx_pemx_bist_status2_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_pemx_bist_status2 cvmx_pemx_bist_status2_t;\n+\n+/**\n+ * cvmx_pem#_cfg\n+ *\n+ * Configuration of the PCIe Application.\n+ *\n+ */\n+union cvmx_pemx_cfg {\n+\tu64 u64;\n+\tstruct cvmx_pemx_cfg_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 laneswap : 1;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 md : 2;\n+\t} s;\n+\tstruct cvmx_pemx_cfg_cn70xx {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 laneswap : 1;\n+\t\tu64 hostmd : 1;\n+\t\tu64 md : 3;\n+\t} cn70xx;\n+\tstruct cvmx_pemx_cfg_cn70xx cn70xxp1;\n+\tstruct cvmx_pemx_cfg_cn73xx {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 laneswap : 1;\n+\t\tu64 lanes8 : 1;\n+\t\tu64 hostmd : 1;\n+\t\tu64 md : 2;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_cfg_cn73xx cn78xx;\n+\tstruct cvmx_pemx_cfg_cn73xx cn78xxp1;\n+\tstruct cvmx_pemx_cfg_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_cfg cvmx_pemx_cfg_t;\n+\n+/**\n+ * cvmx_pem#_cfg_rd\n+ *\n+ * This register allows read access to the configuration in the PCIe core.\n+ *\n+ */\n+union cvmx_pemx_cfg_rd {\n+\tu64 u64;\n+\tstruct cvmx_pemx_cfg_rd_s {\n+\t\tu64 data : 32;\n+\t\tu64 addr : 32;\n+\t} s;\n+\tstruct cvmx_pemx_cfg_rd_s cn61xx;\n+\tstruct cvmx_pemx_cfg_rd_s cn63xx;\n+\tstruct cvmx_pemx_cfg_rd_s cn63xxp1;\n+\tstruct cvmx_pemx_cfg_rd_s cn66xx;\n+\tstruct cvmx_pemx_cfg_rd_s cn68xx;\n+\tstruct cvmx_pemx_cfg_rd_s cn68xxp1;\n+\tstruct cvmx_pemx_cfg_rd_s cn70xx;\n+\tstruct cvmx_pemx_cfg_rd_s cn70xxp1;\n+\tstruct cvmx_pemx_cfg_rd_s cn73xx;\n+\tstruct cvmx_pemx_cfg_rd_s cn78xx;\n+\tstruct cvmx_pemx_cfg_rd_s cn78xxp1;\n+\tstruct cvmx_pemx_cfg_rd_s cnf71xx;\n+\tstruct cvmx_pemx_cfg_rd_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_cfg_rd cvmx_pemx_cfg_rd_t;\n+\n+/**\n+ * cvmx_pem#_cfg_wr\n+ *\n+ * This register allows write access to the configuration in the PCIe core.\n+ *\n+ */\n+union cvmx_pemx_cfg_wr {\n+\tu64 u64;\n+\tstruct cvmx_pemx_cfg_wr_s {\n+\t\tu64 data : 32;\n+\t\tu64 addr : 32;\n+\t} s;\n+\tstruct cvmx_pemx_cfg_wr_s cn61xx;\n+\tstruct cvmx_pemx_cfg_wr_s cn63xx;\n+\tstruct cvmx_pemx_cfg_wr_s cn63xxp1;\n+\tstruct cvmx_pemx_cfg_wr_s cn66xx;\n+\tstruct cvmx_pemx_cfg_wr_s cn68xx;\n+\tstruct cvmx_pemx_cfg_wr_s cn68xxp1;\n+\tstruct cvmx_pemx_cfg_wr_s cn70xx;\n+\tstruct cvmx_pemx_cfg_wr_s cn70xxp1;\n+\tstruct cvmx_pemx_cfg_wr_s cn73xx;\n+\tstruct cvmx_pemx_cfg_wr_s cn78xx;\n+\tstruct cvmx_pemx_cfg_wr_s cn78xxp1;\n+\tstruct cvmx_pemx_cfg_wr_s cnf71xx;\n+\tstruct cvmx_pemx_cfg_wr_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_cfg_wr cvmx_pemx_cfg_wr_t;\n+\n+/**\n+ * cvmx_pem#_clk_en\n+ *\n+ * This register contains the clock enable for ECLK and PCE_CLK.\n+ *\n+ */\n+union cvmx_pemx_clk_en {\n+\tu64 u64;\n+\tstruct cvmx_pemx_clk_en_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 pceclk_gate : 1;\n+\t\tu64 csclk_gate : 1;\n+\t} s;\n+\tstruct cvmx_pemx_clk_en_s cn70xx;\n+\tstruct cvmx_pemx_clk_en_s cn70xxp1;\n+\tstruct cvmx_pemx_clk_en_s cn73xx;\n+\tstruct cvmx_pemx_clk_en_s cn78xx;\n+\tstruct cvmx_pemx_clk_en_s cn78xxp1;\n+\tstruct cvmx_pemx_clk_en_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_clk_en cvmx_pemx_clk_en_t;\n+\n+/**\n+ * cvmx_pem#_cpl_lut_valid\n+ *\n+ * This register specifies the bit set for an outstanding tag read.\n+ *\n+ */\n+union cvmx_pemx_cpl_lut_valid {\n+\tu64 u64;\n+\tstruct cvmx_pemx_cpl_lut_valid_s {\n+\t\tu64 tag : 64;\n+\t} s;\n+\tstruct cvmx_pemx_cpl_lut_valid_cn61xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 tag : 32;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_cpl_lut_valid_cn61xx cn63xx;\n+\tstruct cvmx_pemx_cpl_lut_valid_cn61xx cn63xxp1;\n+\tstruct cvmx_pemx_cpl_lut_valid_cn61xx cn66xx;\n+\tstruct cvmx_pemx_cpl_lut_valid_cn61xx cn68xx;\n+\tstruct cvmx_pemx_cpl_lut_valid_cn61xx cn68xxp1;\n+\tstruct cvmx_pemx_cpl_lut_valid_cn61xx cn70xx;\n+\tstruct cvmx_pemx_cpl_lut_valid_cn61xx cn70xxp1;\n+\tstruct cvmx_pemx_cpl_lut_valid_s cn73xx;\n+\tstruct cvmx_pemx_cpl_lut_valid_s cn78xx;\n+\tstruct cvmx_pemx_cpl_lut_valid_s cn78xxp1;\n+\tstruct cvmx_pemx_cpl_lut_valid_cn61xx cnf71xx;\n+\tstruct cvmx_pemx_cpl_lut_valid_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_cpl_lut_valid cvmx_pemx_cpl_lut_valid_t;\n+\n+/**\n+ * cvmx_pem#_ctl_status\n+ *\n+ * This is a general control and status register of the PEM.\n+ *\n+ */\n+union cvmx_pemx_ctl_status {\n+\tu64 u64;\n+\tstruct cvmx_pemx_ctl_status_s {\n+\t\tu64 reserved_51_63 : 13;\n+\t\tu64 inv_dpar : 1;\n+\t\tu64 inv_hpar : 1;\n+\t\tu64 inv_rpar : 1;\n+\t\tu64 auto_sd : 1;\n+\t\tu64 dnum : 5;\n+\t\tu64 pbus : 8;\n+\t\tu64 reserved_32_33 : 2;\n+\t\tu64 cfg_rtry : 16;\n+\t\tu64 reserved_12_15 : 4;\n+\t\tu64 pm_xtoff : 1;\n+\t\tu64 pm_xpme : 1;\n+\t\tu64 ob_p_cmd : 1;\n+\t\tu64 reserved_7_8 : 2;\n+\t\tu64 nf_ecrc : 1;\n+\t\tu64 dly_one : 1;\n+\t\tu64 lnk_enb : 1;\n+\t\tu64 ro_ctlp : 1;\n+\t\tu64 fast_lm : 1;\n+\t\tu64 inv_ecrc : 1;\n+\t\tu64 inv_lcrc : 1;\n+\t} s;\n+\tstruct cvmx_pemx_ctl_status_cn61xx {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 auto_sd : 1;\n+\t\tu64 dnum : 5;\n+\t\tu64 pbus : 8;\n+\t\tu64 reserved_32_33 : 2;\n+\t\tu64 cfg_rtry : 16;\n+\t\tu64 reserved_12_15 : 4;\n+\t\tu64 pm_xtoff : 1;\n+\t\tu64 pm_xpme : 1;\n+\t\tu64 ob_p_cmd : 1;\n+\t\tu64 reserved_7_8 : 2;\n+\t\tu64 nf_ecrc : 1;\n+\t\tu64 dly_one : 1;\n+\t\tu64 lnk_enb : 1;\n+\t\tu64 ro_ctlp : 1;\n+\t\tu64 fast_lm : 1;\n+\t\tu64 inv_ecrc : 1;\n+\t\tu64 inv_lcrc : 1;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_ctl_status_cn61xx cn63xx;\n+\tstruct cvmx_pemx_ctl_status_cn61xx cn63xxp1;\n+\tstruct cvmx_pemx_ctl_status_cn61xx cn66xx;\n+\tstruct cvmx_pemx_ctl_status_cn61xx cn68xx;\n+\tstruct cvmx_pemx_ctl_status_cn61xx cn68xxp1;\n+\tstruct cvmx_pemx_ctl_status_s cn70xx;\n+\tstruct cvmx_pemx_ctl_status_s cn70xxp1;\n+\tstruct cvmx_pemx_ctl_status_cn73xx {\n+\t\tu64 reserved_51_63 : 13;\n+\t\tu64 inv_dpar : 1;\n+\t\tu64 reserved_48_49 : 2;\n+\t\tu64 auto_sd : 1;\n+\t\tu64 dnum : 5;\n+\t\tu64 pbus : 8;\n+\t\tu64 reserved_32_33 : 2;\n+\t\tu64 cfg_rtry : 16;\n+\t\tu64 reserved_12_15 : 4;\n+\t\tu64 pm_xtoff : 1;\n+\t\tu64 pm_xpme : 1;\n+\t\tu64 ob_p_cmd : 1;\n+\t\tu64 reserved_7_8 : 2;\n+\t\tu64 nf_ecrc : 1;\n+\t\tu64 dly_one : 1;\n+\t\tu64 lnk_enb : 1;\n+\t\tu64 ro_ctlp : 1;\n+\t\tu64 fast_lm : 1;\n+\t\tu64 inv_ecrc : 1;\n+\t\tu64 inv_lcrc : 1;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_ctl_status_cn73xx cn78xx;\n+\tstruct cvmx_pemx_ctl_status_cn73xx cn78xxp1;\n+\tstruct cvmx_pemx_ctl_status_cn61xx cnf71xx;\n+\tstruct cvmx_pemx_ctl_status_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_ctl_status cvmx_pemx_ctl_status_t;\n+\n+/**\n+ * cvmx_pem#_ctl_status2\n+ *\n+ * This register contains additional general control and status of the PEM.\n+ *\n+ */\n+union cvmx_pemx_ctl_status2 {\n+\tu64 u64;\n+\tstruct cvmx_pemx_ctl_status2_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 no_fwd_prg : 16;\n+\t} s;\n+\tstruct cvmx_pemx_ctl_status2_s cn73xx;\n+\tstruct cvmx_pemx_ctl_status2_s cn78xx;\n+\tstruct cvmx_pemx_ctl_status2_s cn78xxp1;\n+\tstruct cvmx_pemx_ctl_status2_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_ctl_status2 cvmx_pemx_ctl_status2_t;\n+\n+/**\n+ * cvmx_pem#_dbg_info\n+ *\n+ * This is a debug information register of the PEM.\n+ *\n+ */\n+union cvmx_pemx_dbg_info {\n+\tu64 u64;\n+\tstruct cvmx_pemx_dbg_info_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 m2s_c_dbe : 1;\n+\t\tu64 m2s_c_sbe : 1;\n+\t\tu64 m2s_d_dbe : 1;\n+\t\tu64 m2s_d_sbe : 1;\n+\t\tu64 qhdr_b1_dbe : 1;\n+\t\tu64 qhdr_b1_sbe : 1;\n+\t\tu64 qhdr_b0_dbe : 1;\n+\t\tu64 qhdr_b0_sbe : 1;\n+\t\tu64 rtry_dbe : 1;\n+\t\tu64 rtry_sbe : 1;\n+\t\tu64 reserved_50_51 : 2;\n+\t\tu64 c_d1_dbe : 1;\n+\t\tu64 c_d1_sbe : 1;\n+\t\tu64 c_d0_dbe : 1;\n+\t\tu64 c_d0_sbe : 1;\n+\t\tu64 reserved_34_45 : 12;\n+\t\tu64 datq_pe : 1;\n+\t\tu64 reserved_31_32 : 2;\n+\t\tu64 ecrc_e : 1;\n+\t\tu64 rawwpp : 1;\n+\t\tu64 racpp : 1;\n+\t\tu64 ramtlp : 1;\n+\t\tu64 rarwdns : 1;\n+\t\tu64 caar : 1;\n+\t\tu64 racca : 1;\n+\t\tu64 racur : 1;\n+\t\tu64 rauc : 1;\n+\t\tu64 rqo : 1;\n+\t\tu64 fcuv : 1;\n+\t\tu64 rpe : 1;\n+\t\tu64 fcpvwt : 1;\n+\t\tu64 dpeoosd : 1;\n+\t\tu64 rtwdle : 1;\n+\t\tu64 rdwdle : 1;\n+\t\tu64 mre : 1;\n+\t\tu64 rte : 1;\n+\t\tu64 acto : 1;\n+\t\tu64 rvdm : 1;\n+\t\tu64 rumep : 1;\n+\t\tu64 rptamrc : 1;\n+\t\tu64 rpmerc : 1;\n+\t\tu64 rfemrc : 1;\n+\t\tu64 rnfemrc : 1;\n+\t\tu64 rcemrc : 1;\n+\t\tu64 rpoison : 1;\n+\t\tu64 recrce : 1;\n+\t\tu64 rtlplle : 1;\n+\t\tu64 rtlpmal : 1;\n+\t\tu64 spoison : 1;\n+\t} s;\n+\tstruct cvmx_pemx_dbg_info_cn61xx {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 ecrc_e : 1;\n+\t\tu64 rawwpp : 1;\n+\t\tu64 racpp : 1;\n+\t\tu64 ramtlp : 1;\n+\t\tu64 rarwdns : 1;\n+\t\tu64 caar : 1;\n+\t\tu64 racca : 1;\n+\t\tu64 racur : 1;\n+\t\tu64 rauc : 1;\n+\t\tu64 rqo : 1;\n+\t\tu64 fcuv : 1;\n+\t\tu64 rpe : 1;\n+\t\tu64 fcpvwt : 1;\n+\t\tu64 dpeoosd : 1;\n+\t\tu64 rtwdle : 1;\n+\t\tu64 rdwdle : 1;\n+\t\tu64 mre : 1;\n+\t\tu64 rte : 1;\n+\t\tu64 acto : 1;\n+\t\tu64 rvdm : 1;\n+\t\tu64 rumep : 1;\n+\t\tu64 rptamrc : 1;\n+\t\tu64 rpmerc : 1;\n+\t\tu64 rfemrc : 1;\n+\t\tu64 rnfemrc : 1;\n+\t\tu64 rcemrc : 1;\n+\t\tu64 rpoison : 1;\n+\t\tu64 recrce : 1;\n+\t\tu64 rtlplle : 1;\n+\t\tu64 rtlpmal : 1;\n+\t\tu64 spoison : 1;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_dbg_info_cn61xx cn63xx;\n+\tstruct cvmx_pemx_dbg_info_cn61xx cn63xxp1;\n+\tstruct cvmx_pemx_dbg_info_cn61xx cn66xx;\n+\tstruct cvmx_pemx_dbg_info_cn61xx cn68xx;\n+\tstruct cvmx_pemx_dbg_info_cn61xx cn68xxp1;\n+\tstruct cvmx_pemx_dbg_info_cn70xx {\n+\t\tu64 reserved_46_63 : 18;\n+\t\tu64 c_c_dbe : 1;\n+\t\tu64 c_c_sbe : 1;\n+\t\tu64 c_d_dbe : 1;\n+\t\tu64 c_d_sbe : 1;\n+\t\tu64 n_c_dbe : 1;\n+\t\tu64 n_c_sbe : 1;\n+\t\tu64 n_d_dbe : 1;\n+\t\tu64 n_d_sbe : 1;\n+\t\tu64 p_c_dbe : 1;\n+\t\tu64 p_c_sbe : 1;\n+\t\tu64 p_d_dbe : 1;\n+\t\tu64 p_d_sbe : 1;\n+\t\tu64 datq_pe : 1;\n+\t\tu64 hdrq_pe : 1;\n+\t\tu64 rtry_pe : 1;\n+\t\tu64 ecrc_e : 1;\n+\t\tu64 rawwpp : 1;\n+\t\tu64 racpp : 1;\n+\t\tu64 ramtlp : 1;\n+\t\tu64 rarwdns : 1;\n+\t\tu64 caar : 1;\n+\t\tu64 racca : 1;\n+\t\tu64 racur : 1;\n+\t\tu64 rauc : 1;\n+\t\tu64 rqo : 1;\n+\t\tu64 fcuv : 1;\n+\t\tu64 rpe : 1;\n+\t\tu64 fcpvwt : 1;\n+\t\tu64 dpeoosd : 1;\n+\t\tu64 rtwdle : 1;\n+\t\tu64 rdwdle : 1;\n+\t\tu64 mre : 1;\n+\t\tu64 rte : 1;\n+\t\tu64 acto : 1;\n+\t\tu64 rvdm : 1;\n+\t\tu64 rumep : 1;\n+\t\tu64 rptamrc : 1;\n+\t\tu64 rpmerc : 1;\n+\t\tu64 rfemrc : 1;\n+\t\tu64 rnfemrc : 1;\n+\t\tu64 rcemrc : 1;\n+\t\tu64 rpoison : 1;\n+\t\tu64 recrce : 1;\n+\t\tu64 rtlplle : 1;\n+\t\tu64 rtlpmal : 1;\n+\t\tu64 spoison : 1;\n+\t} cn70xx;\n+\tstruct cvmx_pemx_dbg_info_cn70xx cn70xxp1;\n+\tstruct cvmx_pemx_dbg_info_cn73xx {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 m2s_c_dbe : 1;\n+\t\tu64 m2s_c_sbe : 1;\n+\t\tu64 m2s_d_dbe : 1;\n+\t\tu64 m2s_d_sbe : 1;\n+\t\tu64 qhdr_b1_dbe : 1;\n+\t\tu64 qhdr_b1_sbe : 1;\n+\t\tu64 qhdr_b0_dbe : 1;\n+\t\tu64 qhdr_b0_sbe : 1;\n+\t\tu64 rtry_dbe : 1;\n+\t\tu64 rtry_sbe : 1;\n+\t\tu64 c_c_dbe : 1;\n+\t\tu64 c_c_sbe : 1;\n+\t\tu64 c_d1_dbe : 1;\n+\t\tu64 c_d1_sbe : 1;\n+\t\tu64 c_d0_dbe : 1;\n+\t\tu64 c_d0_sbe : 1;\n+\t\tu64 n_c_dbe : 1;\n+\t\tu64 n_c_sbe : 1;\n+\t\tu64 n_d1_dbe : 1;\n+\t\tu64 n_d1_sbe : 1;\n+\t\tu64 n_d0_dbe : 1;\n+\t\tu64 n_d0_sbe : 1;\n+\t\tu64 p_c_dbe : 1;\n+\t\tu64 p_c_sbe : 1;\n+\t\tu64 p_d1_dbe : 1;\n+\t\tu64 p_d1_sbe : 1;\n+\t\tu64 p_d0_dbe : 1;\n+\t\tu64 p_d0_sbe : 1;\n+\t\tu64 datq_pe : 1;\n+\t\tu64 bmd_e : 1;\n+\t\tu64 lofp : 1;\n+\t\tu64 ecrc_e : 1;\n+\t\tu64 rawwpp : 1;\n+\t\tu64 racpp : 1;\n+\t\tu64 ramtlp : 1;\n+\t\tu64 rarwdns : 1;\n+\t\tu64 caar : 1;\n+\t\tu64 racca : 1;\n+\t\tu64 racur : 1;\n+\t\tu64 rauc : 1;\n+\t\tu64 rqo : 1;\n+\t\tu64 fcuv : 1;\n+\t\tu64 rpe : 1;\n+\t\tu64 fcpvwt : 1;\n+\t\tu64 dpeoosd : 1;\n+\t\tu64 rtwdle : 1;\n+\t\tu64 rdwdle : 1;\n+\t\tu64 mre : 1;\n+\t\tu64 rte : 1;\n+\t\tu64 acto : 1;\n+\t\tu64 rvdm : 1;\n+\t\tu64 rumep : 1;\n+\t\tu64 rptamrc : 1;\n+\t\tu64 rpmerc : 1;\n+\t\tu64 rfemrc : 1;\n+\t\tu64 rnfemrc : 1;\n+\t\tu64 rcemrc : 1;\n+\t\tu64 rpoison : 1;\n+\t\tu64 recrce : 1;\n+\t\tu64 rtlplle : 1;\n+\t\tu64 rtlpmal : 1;\n+\t\tu64 spoison : 1;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_dbg_info_cn73xx cn78xx;\n+\tstruct cvmx_pemx_dbg_info_cn78xxp1 {\n+\t\tu64 reserved_58_63 : 6;\n+\t\tu64 qhdr_b1_dbe : 1;\n+\t\tu64 qhdr_b1_sbe : 1;\n+\t\tu64 qhdr_b0_dbe : 1;\n+\t\tu64 qhdr_b0_sbe : 1;\n+\t\tu64 rtry_dbe : 1;\n+\t\tu64 rtry_sbe : 1;\n+\t\tu64 c_c_dbe : 1;\n+\t\tu64 c_c_sbe : 1;\n+\t\tu64 c_d1_dbe : 1;\n+\t\tu64 c_d1_sbe : 1;\n+\t\tu64 c_d0_dbe : 1;\n+\t\tu64 c_d0_sbe : 1;\n+\t\tu64 n_c_dbe : 1;\n+\t\tu64 n_c_sbe : 1;\n+\t\tu64 n_d1_dbe : 1;\n+\t\tu64 n_d1_sbe : 1;\n+\t\tu64 n_d0_dbe : 1;\n+\t\tu64 n_d0_sbe : 1;\n+\t\tu64 p_c_dbe : 1;\n+\t\tu64 p_c_sbe : 1;\n+\t\tu64 p_d1_dbe : 1;\n+\t\tu64 p_d1_sbe : 1;\n+\t\tu64 p_d0_dbe : 1;\n+\t\tu64 p_d0_sbe : 1;\n+\t\tu64 datq_pe : 1;\n+\t\tu64 reserved_32_32 : 1;\n+\t\tu64 lofp : 1;\n+\t\tu64 ecrc_e : 1;\n+\t\tu64 rawwpp : 1;\n+\t\tu64 racpp : 1;\n+\t\tu64 ramtlp : 1;\n+\t\tu64 rarwdns : 1;\n+\t\tu64 caar : 1;\n+\t\tu64 racca : 1;\n+\t\tu64 racur : 1;\n+\t\tu64 rauc : 1;\n+\t\tu64 rqo : 1;\n+\t\tu64 fcuv : 1;\n+\t\tu64 rpe : 1;\n+\t\tu64 fcpvwt : 1;\n+\t\tu64 dpeoosd : 1;\n+\t\tu64 rtwdle : 1;\n+\t\tu64 rdwdle : 1;\n+\t\tu64 mre : 1;\n+\t\tu64 rte : 1;\n+\t\tu64 acto : 1;\n+\t\tu64 rvdm : 1;\n+\t\tu64 rumep : 1;\n+\t\tu64 rptamrc : 1;\n+\t\tu64 rpmerc : 1;\n+\t\tu64 rfemrc : 1;\n+\t\tu64 rnfemrc : 1;\n+\t\tu64 rcemrc : 1;\n+\t\tu64 rpoison : 1;\n+\t\tu64 recrce : 1;\n+\t\tu64 rtlplle : 1;\n+\t\tu64 rtlpmal : 1;\n+\t\tu64 spoison : 1;\n+\t} cn78xxp1;\n+\tstruct cvmx_pemx_dbg_info_cn61xx cnf71xx;\n+\tstruct cvmx_pemx_dbg_info_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_dbg_info cvmx_pemx_dbg_info_t;\n+\n+/**\n+ * cvmx_pem#_dbg_info_en\n+ *\n+ * \"PEM#_DBG_INFO_EN = PEM Debug Information Enable\n+ * Allows PEM_DBG_INFO to generate interrupts when cooresponding enable bit is set.\"\n+ */\n+union cvmx_pemx_dbg_info_en {\n+\tu64 u64;\n+\tstruct cvmx_pemx_dbg_info_en_s {\n+\t\tu64 reserved_46_63 : 18;\n+\t\tu64 tpcdbe1 : 1;\n+\t\tu64 tpcsbe1 : 1;\n+\t\tu64 tpcdbe0 : 1;\n+\t\tu64 tpcsbe0 : 1;\n+\t\tu64 tnfdbe1 : 1;\n+\t\tu64 tnfsbe1 : 1;\n+\t\tu64 tnfdbe0 : 1;\n+\t\tu64 tnfsbe0 : 1;\n+\t\tu64 tpfdbe1 : 1;\n+\t\tu64 tpfsbe1 : 1;\n+\t\tu64 tpfdbe0 : 1;\n+\t\tu64 tpfsbe0 : 1;\n+\t\tu64 datq_pe : 1;\n+\t\tu64 hdrq_pe : 1;\n+\t\tu64 rtry_pe : 1;\n+\t\tu64 ecrc_e : 1;\n+\t\tu64 rawwpp : 1;\n+\t\tu64 racpp : 1;\n+\t\tu64 ramtlp : 1;\n+\t\tu64 rarwdns : 1;\n+\t\tu64 caar : 1;\n+\t\tu64 racca : 1;\n+\t\tu64 racur : 1;\n+\t\tu64 rauc : 1;\n+\t\tu64 rqo : 1;\n+\t\tu64 fcuv : 1;\n+\t\tu64 rpe : 1;\n+\t\tu64 fcpvwt : 1;\n+\t\tu64 dpeoosd : 1;\n+\t\tu64 rtwdle : 1;\n+\t\tu64 rdwdle : 1;\n+\t\tu64 mre : 1;\n+\t\tu64 rte : 1;\n+\t\tu64 acto : 1;\n+\t\tu64 rvdm : 1;\n+\t\tu64 rumep : 1;\n+\t\tu64 rptamrc : 1;\n+\t\tu64 rpmerc : 1;\n+\t\tu64 rfemrc : 1;\n+\t\tu64 rnfemrc : 1;\n+\t\tu64 rcemrc : 1;\n+\t\tu64 rpoison : 1;\n+\t\tu64 recrce : 1;\n+\t\tu64 rtlplle : 1;\n+\t\tu64 rtlpmal : 1;\n+\t\tu64 spoison : 1;\n+\t} s;\n+\tstruct cvmx_pemx_dbg_info_en_cn61xx {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 ecrc_e : 1;\n+\t\tu64 rawwpp : 1;\n+\t\tu64 racpp : 1;\n+\t\tu64 ramtlp : 1;\n+\t\tu64 rarwdns : 1;\n+\t\tu64 caar : 1;\n+\t\tu64 racca : 1;\n+\t\tu64 racur : 1;\n+\t\tu64 rauc : 1;\n+\t\tu64 rqo : 1;\n+\t\tu64 fcuv : 1;\n+\t\tu64 rpe : 1;\n+\t\tu64 fcpvwt : 1;\n+\t\tu64 dpeoosd : 1;\n+\t\tu64 rtwdle : 1;\n+\t\tu64 rdwdle : 1;\n+\t\tu64 mre : 1;\n+\t\tu64 rte : 1;\n+\t\tu64 acto : 1;\n+\t\tu64 rvdm : 1;\n+\t\tu64 rumep : 1;\n+\t\tu64 rptamrc : 1;\n+\t\tu64 rpmerc : 1;\n+\t\tu64 rfemrc : 1;\n+\t\tu64 rnfemrc : 1;\n+\t\tu64 rcemrc : 1;\n+\t\tu64 rpoison : 1;\n+\t\tu64 recrce : 1;\n+\t\tu64 rtlplle : 1;\n+\t\tu64 rtlpmal : 1;\n+\t\tu64 spoison : 1;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_dbg_info_en_cn61xx cn63xx;\n+\tstruct cvmx_pemx_dbg_info_en_cn61xx cn63xxp1;\n+\tstruct cvmx_pemx_dbg_info_en_cn61xx cn66xx;\n+\tstruct cvmx_pemx_dbg_info_en_cn61xx cn68xx;\n+\tstruct cvmx_pemx_dbg_info_en_cn61xx cn68xxp1;\n+\tstruct cvmx_pemx_dbg_info_en_s cn70xx;\n+\tstruct cvmx_pemx_dbg_info_en_s cn70xxp1;\n+\tstruct cvmx_pemx_dbg_info_en_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_pemx_dbg_info_en cvmx_pemx_dbg_info_en_t;\n+\n+/**\n+ * cvmx_pem#_diag_status\n+ *\n+ * This register contains selection control for the core diagnostic bus.\n+ *\n+ */\n+union cvmx_pemx_diag_status {\n+\tu64 u64;\n+\tstruct cvmx_pemx_diag_status_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 pwrdwn : 3;\n+\t\tu64 pm_dst : 3;\n+\t\tu64 pm_stat : 1;\n+\t\tu64 pm_en : 1;\n+\t\tu64 aux_en : 1;\n+\t} s;\n+\tstruct cvmx_pemx_diag_status_cn61xx {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 pm_dst : 1;\n+\t\tu64 pm_stat : 1;\n+\t\tu64 pm_en : 1;\n+\t\tu64 aux_en : 1;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_diag_status_cn61xx cn63xx;\n+\tstruct cvmx_pemx_diag_status_cn61xx cn63xxp1;\n+\tstruct cvmx_pemx_diag_status_cn61xx cn66xx;\n+\tstruct cvmx_pemx_diag_status_cn61xx cn68xx;\n+\tstruct cvmx_pemx_diag_status_cn61xx cn68xxp1;\n+\tstruct cvmx_pemx_diag_status_cn70xx {\n+\t\tu64 reserved_63_6 : 58;\n+\t\tu64 pm_dst : 3;\n+\t\tu64 pm_stat : 1;\n+\t\tu64 pm_en : 1;\n+\t\tu64 aux_en : 1;\n+\t} cn70xx;\n+\tstruct cvmx_pemx_diag_status_cn70xx cn70xxp1;\n+\tstruct cvmx_pemx_diag_status_cn73xx {\n+\t\tu64 reserved_63_9 : 55;\n+\t\tu64 pwrdwn : 3;\n+\t\tu64 pm_dst : 3;\n+\t\tu64 pm_stat : 1;\n+\t\tu64 pm_en : 1;\n+\t\tu64 aux_en : 1;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_diag_status_cn73xx cn78xx;\n+\tstruct cvmx_pemx_diag_status_cn73xx cn78xxp1;\n+\tstruct cvmx_pemx_diag_status_cn61xx cnf71xx;\n+\tstruct cvmx_pemx_diag_status_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_diag_status cvmx_pemx_diag_status_t;\n+\n+/**\n+ * cvmx_pem#_ecc_ena\n+ *\n+ * Contains enables for TLP FIFO ECC RAMs.\n+ *\n+ */\n+union cvmx_pemx_ecc_ena {\n+\tu64 u64;\n+\tstruct cvmx_pemx_ecc_ena_s {\n+\t\tu64 reserved_35_63 : 29;\n+\t\tu64 qhdr_b1_ena : 1;\n+\t\tu64 qhdr_b0_ena : 1;\n+\t\tu64 rtry_ena : 1;\n+\t\tu64 reserved_11_31 : 21;\n+\t\tu64 m2s_c_ena : 1;\n+\t\tu64 m2s_d_ena : 1;\n+\t\tu64 c_c_ena : 1;\n+\t\tu64 c_d1_ena : 1;\n+\t\tu64 c_d0_ena : 1;\n+\t\tu64 reserved_0_5 : 6;\n+\t} s;\n+\tstruct cvmx_pemx_ecc_ena_cn70xx {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 tlp_nc_ena : 1;\n+\t\tu64 tlp_nd_ena : 1;\n+\t\tu64 tlp_pc_ena : 1;\n+\t\tu64 tlp_pd_ena : 1;\n+\t\tu64 tlp_cc_ena : 1;\n+\t\tu64 tlp_cd_ena : 1;\n+\t} cn70xx;\n+\tstruct cvmx_pemx_ecc_ena_cn70xx cn70xxp1;\n+\tstruct cvmx_pemx_ecc_ena_cn73xx {\n+\t\tu64 reserved_35_63 : 29;\n+\t\tu64 qhdr_b1_ena : 1;\n+\t\tu64 qhdr_b0_ena : 1;\n+\t\tu64 rtry_ena : 1;\n+\t\tu64 reserved_11_31 : 21;\n+\t\tu64 m2s_c_ena : 1;\n+\t\tu64 m2s_d_ena : 1;\n+\t\tu64 c_c_ena : 1;\n+\t\tu64 c_d1_ena : 1;\n+\t\tu64 c_d0_ena : 1;\n+\t\tu64 n_c_ena : 1;\n+\t\tu64 n_d1_ena : 1;\n+\t\tu64 n_d0_ena : 1;\n+\t\tu64 p_c_ena : 1;\n+\t\tu64 p_d1_ena : 1;\n+\t\tu64 p_d0_ena : 1;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_ecc_ena_cn73xx cn78xx;\n+\tstruct cvmx_pemx_ecc_ena_cn78xxp1 {\n+\t\tu64 reserved_35_63 : 29;\n+\t\tu64 qhdr_b1_ena : 1;\n+\t\tu64 qhdr_b0_ena : 1;\n+\t\tu64 rtry_ena : 1;\n+\t\tu64 reserved_9_31 : 23;\n+\t\tu64 c_c_ena : 1;\n+\t\tu64 c_d1_ena : 1;\n+\t\tu64 c_d0_ena : 1;\n+\t\tu64 n_c_ena : 1;\n+\t\tu64 n_d1_ena : 1;\n+\t\tu64 n_d0_ena : 1;\n+\t\tu64 p_c_ena : 1;\n+\t\tu64 p_d1_ena : 1;\n+\t\tu64 p_d0_ena : 1;\n+\t} cn78xxp1;\n+\tstruct cvmx_pemx_ecc_ena_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_ecc_ena cvmx_pemx_ecc_ena_t;\n+\n+/**\n+ * cvmx_pem#_ecc_synd_ctrl\n+ *\n+ * This register contains syndrome control for TLP FIFO ECC RAMs.\n+ *\n+ */\n+union cvmx_pemx_ecc_synd_ctrl {\n+\tu64 u64;\n+\tstruct cvmx_pemx_ecc_synd_ctrl_s {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 qhdr_b1_syn : 2;\n+\t\tu64 qhdr_b0_syn : 2;\n+\t\tu64 rtry_syn : 2;\n+\t\tu64 reserved_22_31 : 10;\n+\t\tu64 m2s_c_syn : 2;\n+\t\tu64 m2s_d_syn : 2;\n+\t\tu64 c_c_syn : 2;\n+\t\tu64 c_d1_syn : 2;\n+\t\tu64 c_d0_syn : 2;\n+\t\tu64 reserved_0_11 : 12;\n+\t} s;\n+\tstruct cvmx_pemx_ecc_synd_ctrl_cn70xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 tlp_nc_syn : 2;\n+\t\tu64 tlp_nd_syn : 2;\n+\t\tu64 tlp_pc_syn : 2;\n+\t\tu64 tlp_pd_syn : 2;\n+\t\tu64 tlp_cc_syn : 2;\n+\t\tu64 tlp_cd_syn : 2;\n+\t} cn70xx;\n+\tstruct cvmx_pemx_ecc_synd_ctrl_cn70xx cn70xxp1;\n+\tstruct cvmx_pemx_ecc_synd_ctrl_cn73xx {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 qhdr_b1_syn : 2;\n+\t\tu64 qhdr_b0_syn : 2;\n+\t\tu64 rtry_syn : 2;\n+\t\tu64 reserved_22_31 : 10;\n+\t\tu64 m2s_c_syn : 2;\n+\t\tu64 m2s_d_syn : 2;\n+\t\tu64 c_c_syn : 2;\n+\t\tu64 c_d1_syn : 2;\n+\t\tu64 c_d0_syn : 2;\n+\t\tu64 n_c_syn : 2;\n+\t\tu64 n_d1_syn : 2;\n+\t\tu64 n_d0_syn : 2;\n+\t\tu64 p_c_syn : 2;\n+\t\tu64 p_d1_syn : 2;\n+\t\tu64 p_d0_syn : 2;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_ecc_synd_ctrl_cn73xx cn78xx;\n+\tstruct cvmx_pemx_ecc_synd_ctrl_cn78xxp1 {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 qhdr_b1_syn : 2;\n+\t\tu64 qhdr_b0_syn : 2;\n+\t\tu64 rtry_syn : 2;\n+\t\tu64 reserved_18_31 : 14;\n+\t\tu64 c_c_syn : 2;\n+\t\tu64 c_d1_syn : 2;\n+\t\tu64 c_d0_syn : 2;\n+\t\tu64 n_c_syn : 2;\n+\t\tu64 n_d1_syn : 2;\n+\t\tu64 n_d0_syn : 2;\n+\t\tu64 p_c_syn : 2;\n+\t\tu64 p_d1_syn : 2;\n+\t\tu64 p_d0_syn : 2;\n+\t} cn78xxp1;\n+\tstruct cvmx_pemx_ecc_synd_ctrl_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_ecc_synd_ctrl cvmx_pemx_ecc_synd_ctrl_t;\n+\n+/**\n+ * cvmx_pem#_eco\n+ */\n+union cvmx_pemx_eco {\n+\tu64 u64;\n+\tstruct cvmx_pemx_eco_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 eco_rw : 8;\n+\t} s;\n+\tstruct cvmx_pemx_eco_s cn73xx;\n+\tstruct cvmx_pemx_eco_s cn78xx;\n+\tstruct cvmx_pemx_eco_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_eco cvmx_pemx_eco_t;\n+\n+/**\n+ * cvmx_pem#_flr_glblcnt_ctl\n+ */\n+union cvmx_pemx_flr_glblcnt_ctl {\n+\tu64 u64;\n+\tstruct cvmx_pemx_flr_glblcnt_ctl_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 chge : 1;\n+\t\tu64 inc : 1;\n+\t\tu64 delta : 2;\n+\t} s;\n+\tstruct cvmx_pemx_flr_glblcnt_ctl_s cn73xx;\n+\tstruct cvmx_pemx_flr_glblcnt_ctl_s cn78xx;\n+\tstruct cvmx_pemx_flr_glblcnt_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_flr_glblcnt_ctl cvmx_pemx_flr_glblcnt_ctl_t;\n+\n+/**\n+ * cvmx_pem#_flr_pf0_vf_stopreq\n+ *\n+ * Hardware automatically sets the STOPREQ bit for the VF when it enters a\n+ * Function Level Reset (FLR). Software is responsible for clearing the STOPREQ\n+ * bit but must not do so prior to hardware taking down the FLR, which could be\n+ * as long as 100ms. It may be appropriate for software to wait longer before clearing\n+ * STOPREQ, software may need to drain deep DPI queues for example.\n+ * Whenever PEM receives a request mastered by CNXXXX over S2M (i.e. P or NP),\n+ * when STOPREQ is set for the function, PEM will discard the outgoing request\n+ * before sending it to the PCIe core. If a NP, PEM will schedule an immediate\n+ * SWI_RSP_ERROR completion for the request - no timeout is required.\n+ *\n+ * STOPREQ mimics the behavior of PCIEEPVF()_CFG001[ME] for outbound requests that will\n+ * master the PCIe bus (P and NP).\n+ *\n+ * Note that STOPREQ will have no effect on completions returned by CNXXXX over the S2M,\n+ * nor on M2S traffic.\n+ */\n+union cvmx_pemx_flr_pf0_vf_stopreq {\n+\tu64 u64;\n+\tstruct cvmx_pemx_flr_pf0_vf_stopreq_s {\n+\t\tu64 vf_stopreq : 64;\n+\t} s;\n+\tstruct cvmx_pemx_flr_pf0_vf_stopreq_s cn73xx;\n+\tstruct cvmx_pemx_flr_pf0_vf_stopreq_s cn78xx;\n+\tstruct cvmx_pemx_flr_pf0_vf_stopreq_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_flr_pf0_vf_stopreq cvmx_pemx_flr_pf0_vf_stopreq_t;\n+\n+/**\n+ * cvmx_pem#_flr_pf_stopreq\n+ *\n+ * Hardware automatically sets the STOPREQ bit for the PF when it enters a\n+ * Function Level Reset (FLR). Software is responsible for clearing the STOPREQ\n+ * bit but must not do so prior to hardware taking down the FLR, which could be\n+ * as long as 100ms. It may be appropriate for software to wait longer before clearing\n+ * STOPREQ, software may need to drain deep DPI queues for example.\n+ * Whenever PEM receives a PF or child VF request mastered by CNXXXX over S2M (i.e. P or NP),\n+ * when STOPREQ is set for the function, PEM will discard the outgoing request\n+ * before sending it to the PCIe core. If a NP, PEM will schedule an immediate\n+ * SWI_RSP_ERROR completion for the request - no timeout is required.\n+ *\n+ * STOPREQ mimics the behavior of PCIEEP()_CFG001[ME] for outbound requests that will\n+ * master the PCIe bus (P and NP).\n+ *\n+ * STOPREQ will have no effect on completions returned by CNXXXX over the S2M,\n+ * nor on M2S traffic.\n+ *\n+ * When a PF()_STOPREQ is set, none of the associated\n+ * PEM()_FLR_PF()_VF_STOPREQ[VF_STOPREQ] will be set.\n+ *\n+ * STOPREQ is reset when the MAC is reset, and is not reset after a chip soft reset.\n+ */\n+union cvmx_pemx_flr_pf_stopreq {\n+\tu64 u64;\n+\tstruct cvmx_pemx_flr_pf_stopreq_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 pf0_stopreq : 1;\n+\t} s;\n+\tstruct cvmx_pemx_flr_pf_stopreq_s cn73xx;\n+\tstruct cvmx_pemx_flr_pf_stopreq_s cn78xx;\n+\tstruct cvmx_pemx_flr_pf_stopreq_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_flr_pf_stopreq cvmx_pemx_flr_pf_stopreq_t;\n+\n+/**\n+ * cvmx_pem#_flr_stopreq_ctl\n+ */\n+union cvmx_pemx_flr_stopreq_ctl {\n+\tu64 u64;\n+\tstruct cvmx_pemx_flr_stopreq_ctl_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 stopreqclr : 1;\n+\t} s;\n+\tstruct cvmx_pemx_flr_stopreq_ctl_s cn78xx;\n+\tstruct cvmx_pemx_flr_stopreq_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_flr_stopreq_ctl cvmx_pemx_flr_stopreq_ctl_t;\n+\n+/**\n+ * cvmx_pem#_flr_zombie_ctl\n+ */\n+union cvmx_pemx_flr_zombie_ctl {\n+\tu64 u64;\n+\tstruct cvmx_pemx_flr_zombie_ctl_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 exp : 10;\n+\t} s;\n+\tstruct cvmx_pemx_flr_zombie_ctl_s cn73xx;\n+\tstruct cvmx_pemx_flr_zombie_ctl_s cn78xx;\n+\tstruct cvmx_pemx_flr_zombie_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_flr_zombie_ctl cvmx_pemx_flr_zombie_ctl_t;\n+\n+/**\n+ * cvmx_pem#_inb_read_credits\n+ *\n+ * This register contains the number of in-flight read operations from PCIe core to SLI.\n+ *\n+ */\n+union cvmx_pemx_inb_read_credits {\n+\tu64 u64;\n+\tstruct cvmx_pemx_inb_read_credits_s {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 num : 7;\n+\t} s;\n+\tstruct cvmx_pemx_inb_read_credits_cn61xx {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 num : 6;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_inb_read_credits_cn61xx cn66xx;\n+\tstruct cvmx_pemx_inb_read_credits_cn61xx cn68xx;\n+\tstruct cvmx_pemx_inb_read_credits_cn61xx cn70xx;\n+\tstruct cvmx_pemx_inb_read_credits_cn61xx cn70xxp1;\n+\tstruct cvmx_pemx_inb_read_credits_s cn73xx;\n+\tstruct cvmx_pemx_inb_read_credits_s cn78xx;\n+\tstruct cvmx_pemx_inb_read_credits_s cn78xxp1;\n+\tstruct cvmx_pemx_inb_read_credits_cn61xx cnf71xx;\n+\tstruct cvmx_pemx_inb_read_credits_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_inb_read_credits cvmx_pemx_inb_read_credits_t;\n+\n+/**\n+ * cvmx_pem#_int_enb\n+ *\n+ * \"PEM#_INT_ENB = PEM Interrupt Enable\n+ * Enables interrupt conditions for the PEM to generate an RSL interrupt.\"\n+ */\n+union cvmx_pemx_int_enb {\n+\tu64 u64;\n+\tstruct cvmx_pemx_int_enb_s {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 crs_dr : 1;\n+\t\tu64 crs_er : 1;\n+\t\tu64 rdlk : 1;\n+\t\tu64 exc : 1;\n+\t\tu64 un_bx : 1;\n+\t\tu64 un_b2 : 1;\n+\t\tu64 un_b1 : 1;\n+\t\tu64 up_bx : 1;\n+\t\tu64 up_b2 : 1;\n+\t\tu64 up_b1 : 1;\n+\t\tu64 pmem : 1;\n+\t\tu64 pmei : 1;\n+\t\tu64 se : 1;\n+\t\tu64 aeri : 1;\n+\t} s;\n+\tstruct cvmx_pemx_int_enb_s cn61xx;\n+\tstruct cvmx_pemx_int_enb_s cn63xx;\n+\tstruct cvmx_pemx_int_enb_s cn63xxp1;\n+\tstruct cvmx_pemx_int_enb_s cn66xx;\n+\tstruct cvmx_pemx_int_enb_s cn68xx;\n+\tstruct cvmx_pemx_int_enb_s cn68xxp1;\n+\tstruct cvmx_pemx_int_enb_s cn70xx;\n+\tstruct cvmx_pemx_int_enb_s cn70xxp1;\n+\tstruct cvmx_pemx_int_enb_s cnf71xx;\n+};\n+\n+typedef union cvmx_pemx_int_enb cvmx_pemx_int_enb_t;\n+\n+/**\n+ * cvmx_pem#_int_enb_int\n+ *\n+ * \"PEM#_INT_ENB_INT = PEM Interrupt Enable\n+ * Enables interrupt conditions for the PEM to generate an RSL interrupt.\"\n+ */\n+union cvmx_pemx_int_enb_int {\n+\tu64 u64;\n+\tstruct cvmx_pemx_int_enb_int_s {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 crs_dr : 1;\n+\t\tu64 crs_er : 1;\n+\t\tu64 rdlk : 1;\n+\t\tu64 exc : 1;\n+\t\tu64 un_bx : 1;\n+\t\tu64 un_b2 : 1;\n+\t\tu64 un_b1 : 1;\n+\t\tu64 up_bx : 1;\n+\t\tu64 up_b2 : 1;\n+\t\tu64 up_b1 : 1;\n+\t\tu64 pmem : 1;\n+\t\tu64 pmei : 1;\n+\t\tu64 se : 1;\n+\t\tu64 aeri : 1;\n+\t} s;\n+\tstruct cvmx_pemx_int_enb_int_s cn61xx;\n+\tstruct cvmx_pemx_int_enb_int_s cn63xx;\n+\tstruct cvmx_pemx_int_enb_int_s cn63xxp1;\n+\tstruct cvmx_pemx_int_enb_int_s cn66xx;\n+\tstruct cvmx_pemx_int_enb_int_s cn68xx;\n+\tstruct cvmx_pemx_int_enb_int_s cn68xxp1;\n+\tstruct cvmx_pemx_int_enb_int_s cn70xx;\n+\tstruct cvmx_pemx_int_enb_int_s cn70xxp1;\n+\tstruct cvmx_pemx_int_enb_int_s cnf71xx;\n+};\n+\n+typedef union cvmx_pemx_int_enb_int cvmx_pemx_int_enb_int_t;\n+\n+/**\n+ * cvmx_pem#_int_sum\n+ *\n+ * This register contains the different interrupt summary bits of the PEM.\n+ *\n+ */\n+union cvmx_pemx_int_sum {\n+\tu64 u64;\n+\tstruct cvmx_pemx_int_sum_s {\n+\t\tu64 intd : 1;\n+\t\tu64 intc : 1;\n+\t\tu64 intb : 1;\n+\t\tu64 inta : 1;\n+\t\tu64 reserved_14_59 : 46;\n+\t\tu64 crs_dr : 1;\n+\t\tu64 crs_er : 1;\n+\t\tu64 rdlk : 1;\n+\t\tu64 exc : 1;\n+\t\tu64 un_bx : 1;\n+\t\tu64 un_b2 : 1;\n+\t\tu64 un_b1 : 1;\n+\t\tu64 up_bx : 1;\n+\t\tu64 up_b2 : 1;\n+\t\tu64 up_b1 : 1;\n+\t\tu64 pmem : 1;\n+\t\tu64 pmei : 1;\n+\t\tu64 se : 1;\n+\t\tu64 aeri : 1;\n+\t} s;\n+\tstruct cvmx_pemx_int_sum_cn61xx {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 crs_dr : 1;\n+\t\tu64 crs_er : 1;\n+\t\tu64 rdlk : 1;\n+\t\tu64 exc : 1;\n+\t\tu64 un_bx : 1;\n+\t\tu64 un_b2 : 1;\n+\t\tu64 un_b1 : 1;\n+\t\tu64 up_bx : 1;\n+\t\tu64 up_b2 : 1;\n+\t\tu64 up_b1 : 1;\n+\t\tu64 pmem : 1;\n+\t\tu64 pmei : 1;\n+\t\tu64 se : 1;\n+\t\tu64 aeri : 1;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_int_sum_cn61xx cn63xx;\n+\tstruct cvmx_pemx_int_sum_cn61xx cn63xxp1;\n+\tstruct cvmx_pemx_int_sum_cn61xx cn66xx;\n+\tstruct cvmx_pemx_int_sum_cn61xx cn68xx;\n+\tstruct cvmx_pemx_int_sum_cn61xx cn68xxp1;\n+\tstruct cvmx_pemx_int_sum_cn61xx cn70xx;\n+\tstruct cvmx_pemx_int_sum_cn61xx cn70xxp1;\n+\tstruct cvmx_pemx_int_sum_cn73xx {\n+\t\tu64 intd : 1;\n+\t\tu64 intc : 1;\n+\t\tu64 intb : 1;\n+\t\tu64 inta : 1;\n+\t\tu64 reserved_14_59 : 46;\n+\t\tu64 crs_dr : 1;\n+\t\tu64 crs_er : 1;\n+\t\tu64 rdlk : 1;\n+\t\tu64 reserved_10_10 : 1;\n+\t\tu64 un_bx : 1;\n+\t\tu64 un_b2 : 1;\n+\t\tu64 un_b1 : 1;\n+\t\tu64 up_bx : 1;\n+\t\tu64 up_b2 : 1;\n+\t\tu64 up_b1 : 1;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 pmei : 1;\n+\t\tu64 se : 1;\n+\t\tu64 aeri : 1;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_int_sum_cn73xx cn78xx;\n+\tstruct cvmx_pemx_int_sum_cn73xx cn78xxp1;\n+\tstruct cvmx_pemx_int_sum_cn61xx cnf71xx;\n+\tstruct cvmx_pemx_int_sum_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_int_sum cvmx_pemx_int_sum_t;\n+\n+/**\n+ * cvmx_pem#_on\n+ *\n+ * This register indicates that PEM is configured and ready.\n+ *\n+ */\n+union cvmx_pemx_on {\n+\tu64 u64;\n+\tstruct cvmx_pemx_on_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 pemoor : 1;\n+\t\tu64 pemon : 1;\n+\t} s;\n+\tstruct cvmx_pemx_on_s cn70xx;\n+\tstruct cvmx_pemx_on_s cn70xxp1;\n+\tstruct cvmx_pemx_on_s cn73xx;\n+\tstruct cvmx_pemx_on_s cn78xx;\n+\tstruct cvmx_pemx_on_s cn78xxp1;\n+\tstruct cvmx_pemx_on_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_on cvmx_pemx_on_t;\n+\n+/**\n+ * cvmx_pem#_p2n_bar0_start\n+ *\n+ * This register specifies the starting address for memory requests that are to be forwarded to\n+ * the SLI in RC mode.\n+ */\n+union cvmx_pemx_p2n_bar0_start {\n+\tu64 u64;\n+\tstruct cvmx_pemx_p2n_bar0_start_s {\n+\t\tu64 reserved_0_63 : 64;\n+\t} s;\n+\tstruct cvmx_pemx_p2n_bar0_start_cn61xx {\n+\t\tu64 addr : 50;\n+\t\tu64 reserved_0_13 : 14;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_p2n_bar0_start_cn61xx cn63xx;\n+\tstruct cvmx_pemx_p2n_bar0_start_cn61xx cn63xxp1;\n+\tstruct cvmx_pemx_p2n_bar0_start_cn61xx cn66xx;\n+\tstruct cvmx_pemx_p2n_bar0_start_cn61xx cn68xx;\n+\tstruct cvmx_pemx_p2n_bar0_start_cn61xx cn68xxp1;\n+\tstruct cvmx_pemx_p2n_bar0_start_cn61xx cn70xx;\n+\tstruct cvmx_pemx_p2n_bar0_start_cn61xx cn70xxp1;\n+\tstruct cvmx_pemx_p2n_bar0_start_cn73xx {\n+\t\tu64 addr : 41;\n+\t\tu64 reserved_0_22 : 23;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_p2n_bar0_start_cn73xx cn78xx;\n+\tstruct cvmx_pemx_p2n_bar0_start_cn78xxp1 {\n+\t\tu64 addr : 49;\n+\t\tu64 reserved_0_14 : 15;\n+\t} cn78xxp1;\n+\tstruct cvmx_pemx_p2n_bar0_start_cn61xx cnf71xx;\n+\tstruct cvmx_pemx_p2n_bar0_start_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_p2n_bar0_start cvmx_pemx_p2n_bar0_start_t;\n+\n+/**\n+ * cvmx_pem#_p2n_bar1_start\n+ *\n+ * This register specifies the starting address for memory requests that are to be forwarded to\n+ * the SLI in RC mode.\n+ */\n+union cvmx_pemx_p2n_bar1_start {\n+\tu64 u64;\n+\tstruct cvmx_pemx_p2n_bar1_start_s {\n+\t\tu64 addr : 38;\n+\t\tu64 reserved_0_25 : 26;\n+\t} s;\n+\tstruct cvmx_pemx_p2n_bar1_start_s cn61xx;\n+\tstruct cvmx_pemx_p2n_bar1_start_s cn63xx;\n+\tstruct cvmx_pemx_p2n_bar1_start_s cn63xxp1;\n+\tstruct cvmx_pemx_p2n_bar1_start_s cn66xx;\n+\tstruct cvmx_pemx_p2n_bar1_start_s cn68xx;\n+\tstruct cvmx_pemx_p2n_bar1_start_s cn68xxp1;\n+\tstruct cvmx_pemx_p2n_bar1_start_s cn70xx;\n+\tstruct cvmx_pemx_p2n_bar1_start_s cn70xxp1;\n+\tstruct cvmx_pemx_p2n_bar1_start_s cn73xx;\n+\tstruct cvmx_pemx_p2n_bar1_start_s cn78xx;\n+\tstruct cvmx_pemx_p2n_bar1_start_s cn78xxp1;\n+\tstruct cvmx_pemx_p2n_bar1_start_s cnf71xx;\n+\tstruct cvmx_pemx_p2n_bar1_start_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_p2n_bar1_start cvmx_pemx_p2n_bar1_start_t;\n+\n+/**\n+ * cvmx_pem#_p2n_bar2_start\n+ *\n+ * This register specifies the starting address for memory requests that are to be forwarded to\n+ * the SLI in RC mode.\n+ */\n+union cvmx_pemx_p2n_bar2_start {\n+\tu64 u64;\n+\tstruct cvmx_pemx_p2n_bar2_start_s {\n+\t\tu64 reserved_0_63 : 64;\n+\t} s;\n+\tstruct cvmx_pemx_p2n_bar2_start_cn61xx {\n+\t\tu64 addr : 23;\n+\t\tu64 reserved_0_40 : 41;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_p2n_bar2_start_cn61xx cn63xx;\n+\tstruct cvmx_pemx_p2n_bar2_start_cn61xx cn63xxp1;\n+\tstruct cvmx_pemx_p2n_bar2_start_cn61xx cn66xx;\n+\tstruct cvmx_pemx_p2n_bar2_start_cn61xx cn68xx;\n+\tstruct cvmx_pemx_p2n_bar2_start_cn61xx cn68xxp1;\n+\tstruct cvmx_pemx_p2n_bar2_start_cn61xx cn70xx;\n+\tstruct cvmx_pemx_p2n_bar2_start_cn61xx cn70xxp1;\n+\tstruct cvmx_pemx_p2n_bar2_start_cn73xx {\n+\t\tu64 addr : 19;\n+\t\tu64 reserved_0_44 : 45;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_p2n_bar2_start_cn73xx cn78xx;\n+\tstruct cvmx_pemx_p2n_bar2_start_cn73xx cn78xxp1;\n+\tstruct cvmx_pemx_p2n_bar2_start_cn61xx cnf71xx;\n+\tstruct cvmx_pemx_p2n_bar2_start_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_p2n_bar2_start cvmx_pemx_p2n_bar2_start_t;\n+\n+/**\n+ * cvmx_pem#_p2p_bar#_end\n+ *\n+ * This register specifies the ending address for memory requests that are to be forwarded to the\n+ * PCIe peer port.\n+ */\n+union cvmx_pemx_p2p_barx_end {\n+\tu64 u64;\n+\tstruct cvmx_pemx_p2p_barx_end_s {\n+\t\tu64 addr : 52;\n+\t\tu64 reserved_0_11 : 12;\n+\t} s;\n+\tstruct cvmx_pemx_p2p_barx_end_s cn63xx;\n+\tstruct cvmx_pemx_p2p_barx_end_s cn63xxp1;\n+\tstruct cvmx_pemx_p2p_barx_end_s cn66xx;\n+\tstruct cvmx_pemx_p2p_barx_end_s cn68xx;\n+\tstruct cvmx_pemx_p2p_barx_end_s cn68xxp1;\n+\tstruct cvmx_pemx_p2p_barx_end_s cn73xx;\n+\tstruct cvmx_pemx_p2p_barx_end_s cn78xx;\n+\tstruct cvmx_pemx_p2p_barx_end_s cn78xxp1;\n+\tstruct cvmx_pemx_p2p_barx_end_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_p2p_barx_end cvmx_pemx_p2p_barx_end_t;\n+\n+/**\n+ * cvmx_pem#_p2p_bar#_start\n+ *\n+ * This register specifies the starting address for memory requests that are to be forwarded to\n+ * the PCIe peer port.\n+ */\n+union cvmx_pemx_p2p_barx_start {\n+\tu64 u64;\n+\tstruct cvmx_pemx_p2p_barx_start_s {\n+\t\tu64 addr : 52;\n+\t\tu64 reserved_2_11 : 10;\n+\t\tu64 dst : 2;\n+\t} s;\n+\tstruct cvmx_pemx_p2p_barx_start_cn63xx {\n+\t\tu64 addr : 52;\n+\t\tu64 reserved_0_11 : 12;\n+\t} cn63xx;\n+\tstruct cvmx_pemx_p2p_barx_start_cn63xx cn63xxp1;\n+\tstruct cvmx_pemx_p2p_barx_start_cn63xx cn66xx;\n+\tstruct cvmx_pemx_p2p_barx_start_cn63xx cn68xx;\n+\tstruct cvmx_pemx_p2p_barx_start_cn63xx cn68xxp1;\n+\tstruct cvmx_pemx_p2p_barx_start_s cn73xx;\n+\tstruct cvmx_pemx_p2p_barx_start_s cn78xx;\n+\tstruct cvmx_pemx_p2p_barx_start_s cn78xxp1;\n+\tstruct cvmx_pemx_p2p_barx_start_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_p2p_barx_start cvmx_pemx_p2p_barx_start_t;\n+\n+/**\n+ * cvmx_pem#_qlm\n+ *\n+ * This register configures the PEM3 QLM.\n+ *\n+ */\n+union cvmx_pemx_qlm {\n+\tu64 u64;\n+\tstruct cvmx_pemx_qlm_s {\n+\t\tu64 reserved_0_63 : 64;\n+\t} s;\n+\tstruct cvmx_pemx_qlm_cn73xx {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 pemdlmsel : 1;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_qlm_cn78xx {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 pem3qlm : 1;\n+\t} cn78xx;\n+\tstruct cvmx_pemx_qlm_cn78xx cn78xxp1;\n+\tstruct cvmx_pemx_qlm_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_qlm cvmx_pemx_qlm_t;\n+\n+/**\n+ * cvmx_pem#_spi_ctl\n+ *\n+ * PEM#_SPI_CTL register.\n+ *\n+ */\n+union cvmx_pemx_spi_ctl {\n+\tu64 u64;\n+\tstruct cvmx_pemx_spi_ctl_s {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 start_busy : 1;\n+\t\tu64 tvalid : 1;\n+\t\tu64 cmd : 3;\n+\t\tu64 adr : 9;\n+\t} s;\n+\tstruct cvmx_pemx_spi_ctl_s cn70xx;\n+\tstruct cvmx_pemx_spi_ctl_s cn70xxp1;\n+\tstruct cvmx_pemx_spi_ctl_s cn73xx;\n+\tstruct cvmx_pemx_spi_ctl_s cn78xx;\n+\tstruct cvmx_pemx_spi_ctl_s cn78xxp1;\n+\tstruct cvmx_pemx_spi_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_spi_ctl cvmx_pemx_spi_ctl_t;\n+\n+/**\n+ * cvmx_pem#_spi_data\n+ *\n+ * This register contains the most recently read or written SPI data and is unpredictable upon\n+ * power-up. Is valid after a PEM()_SPI_CTL[CMD]=READ/RDSR when hardware clears\n+ * PEM()_SPI_CTL[START_BUSY]. Is written after a PEM()_SPI_CTL[CMD]=WRITE/WRSR\n+ * when hardware clears PEM()_SPI_CTL[START_BUSY].\n+ */\n+union cvmx_pemx_spi_data {\n+\tu64 u64;\n+\tstruct cvmx_pemx_spi_data_s {\n+\t\tu64 preamble : 16;\n+\t\tu64 reserved_45_47 : 3;\n+\t\tu64 cs2 : 1;\n+\t\tu64 adr : 12;\n+\t\tu64 data : 32;\n+\t} s;\n+\tstruct cvmx_pemx_spi_data_s cn70xx;\n+\tstruct cvmx_pemx_spi_data_s cn70xxp1;\n+\tstruct cvmx_pemx_spi_data_s cn73xx;\n+\tstruct cvmx_pemx_spi_data_s cn78xx;\n+\tstruct cvmx_pemx_spi_data_s cn78xxp1;\n+\tstruct cvmx_pemx_spi_data_s cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_spi_data cvmx_pemx_spi_data_t;\n+\n+/**\n+ * cvmx_pem#_strap\n+ *\n+ * \"Below are in pesc_csr\n+ * The input strapping pins\"\n+ */\n+union cvmx_pemx_strap {\n+\tu64 u64;\n+\tstruct cvmx_pemx_strap_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 miopem2dlm5sel : 1;\n+\t\tu64 pilaneswap : 1;\n+\t\tu64 reserved_0_2 : 3;\n+\t} s;\n+\tstruct cvmx_pemx_strap_cn70xx {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 pilaneswap : 1;\n+\t\tu64 pimode : 3;\n+\t} cn70xx;\n+\tstruct cvmx_pemx_strap_cn70xx cn70xxp1;\n+\tstruct cvmx_pemx_strap_cn73xx {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 miopem2dlm5sel : 1;\n+\t\tu64 pilaneswap : 1;\n+\t\tu64 pilanes8 : 1;\n+\t\tu64 pimode : 2;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_strap_cn78xx {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 pilaneswap : 1;\n+\t\tu64 pilanes8 : 1;\n+\t\tu64 pimode : 2;\n+\t} cn78xx;\n+\tstruct cvmx_pemx_strap_cn78xx cn78xxp1;\n+\tstruct cvmx_pemx_strap_cnf75xx {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 miopem2dlm5sel : 1;\n+\t\tu64 pilaneswap : 1;\n+\t\tu64 pilanes4 : 1;\n+\t\tu64 pimode : 2;\n+\t} cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_strap cvmx_pemx_strap_t;\n+\n+/**\n+ * cvmx_pem#_tlp_credits\n+ *\n+ * This register specifies the number of credits for use in moving TLPs. When this register is\n+ * written, the credit values are reset to the register value. A write to this register should\n+ * take place before traffic flow starts.\n+ */\n+union cvmx_pemx_tlp_credits {\n+\tu64 u64;\n+\tstruct cvmx_pemx_tlp_credits_s {\n+\t\tu64 reserved_56_63 : 8;\n+\t\tu64 peai_ppf : 8;\n+\t\tu64 pem_cpl : 8;\n+\t\tu64 pem_np : 8;\n+\t\tu64 pem_p : 8;\n+\t\tu64 sli_cpl : 8;\n+\t\tu64 sli_np : 8;\n+\t\tu64 sli_p : 8;\n+\t} s;\n+\tstruct cvmx_pemx_tlp_credits_cn61xx {\n+\t\tu64 reserved_56_63 : 8;\n+\t\tu64 peai_ppf : 8;\n+\t\tu64 reserved_24_47 : 24;\n+\t\tu64 sli_cpl : 8;\n+\t\tu64 sli_np : 8;\n+\t\tu64 sli_p : 8;\n+\t} cn61xx;\n+\tstruct cvmx_pemx_tlp_credits_s cn63xx;\n+\tstruct cvmx_pemx_tlp_credits_s cn63xxp1;\n+\tstruct cvmx_pemx_tlp_credits_s cn66xx;\n+\tstruct cvmx_pemx_tlp_credits_s cn68xx;\n+\tstruct cvmx_pemx_tlp_credits_s cn68xxp1;\n+\tstruct cvmx_pemx_tlp_credits_cn61xx cn70xx;\n+\tstruct cvmx_pemx_tlp_credits_cn61xx cn70xxp1;\n+\tstruct cvmx_pemx_tlp_credits_cn73xx {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 pem_cpl : 8;\n+\t\tu64 pem_np : 8;\n+\t\tu64 pem_p : 8;\n+\t\tu64 sli_cpl : 8;\n+\t\tu64 sli_np : 8;\n+\t\tu64 sli_p : 8;\n+\t} cn73xx;\n+\tstruct cvmx_pemx_tlp_credits_cn73xx cn78xx;\n+\tstruct cvmx_pemx_tlp_credits_cn73xx cn78xxp1;\n+\tstruct cvmx_pemx_tlp_credits_cn61xx cnf71xx;\n+\tstruct cvmx_pemx_tlp_credits_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_pemx_tlp_credits cvmx_pemx_tlp_credits_t;\n+\n+#endif\n", "prefixes": [ "v1", "20/50" ] }