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GET /api/patches/1414991/?format=api
{ "id": 1414991, "url": "http://patchwork.ozlabs.org/api/patches/1414991/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-17-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-17-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:38", "name": "[v1,16/50] mips: octeon: Add cvmx-npi-defs.h header file", "commit_ref": "0b9dce59e6a6662d86810008ab1d5bc7c6320683", "pull_url": null, "state": "accepted", "archived": false, "hash": "50bd5b5828b9efa7a5c50ca8b9f5faa32cc0b256", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-17-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1414991/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1414991/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=zgIe2bED;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4Cswgs2mWGz9sSs\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:08:41 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id A96298261E;\n\tFri, 11 Dec 2020 17:07:10 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 43D4882778; Fri, 11 Dec 2020 17:06:54 +0100 (CET)", "from mx2.mailbox.org (mx2a.mailbox.org\n [IPv6:2001:67c:2050:104:0:2:25:2])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 29AB482563\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:23 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org\n [IPv6:2001:67c:2050:105:465:1:1:0])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id B7C57A0E3B;\n Fri, 11 Dec 2020 17:06:22 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter01.heinlein-hosting.de (spamfilter01.heinlein-hosting.de\n [80.241.56.115]) (amavisd-new, port 10030)\n with ESMTP id VvIz7S-J4Rfn; Fri, 11 Dec 2020 17:06:18 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702830;\n\tbh=ocsmQq6vsh6aZWrhKoE57k8FQIqTipx4r1Ep+iV79+A=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=zgIe2bED3yO/iX/740pFM4WMvFYGtoYbuVRyzkmfurzzLW9dv81YoXynHLFXICXRF\n\t ytk0xRUoMyPUMzp7PmnU+XNHchbG6iTM85ZoUabhDKVD5Fn9HtPATYyMyUw3H4cfRT\n\t sskQFTrdEyvUlL/bJFRv+pgzj/JqeWj8AvWKNuSmcT8v/uKT1VEvBa4yqPAJtGrQy9\n\t jKR2DcCrXn40YVP0lpLFBRYpCrLp0nMfEjxA08b4TN//raagW1AD3WUPVE+/pSNHiL\n\t VoQBtoAVL30i5l8TPT2Tx2It0T9Nfo1S+Z35PfejZaJx++i4tVq0730Vl6J1+6FJfE\n\t eo/uSUEQYq9WQ==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 16/50] mips: octeon: Add cvmx-npi-defs.h header file", "Date": "Fri, 11 Dec 2020 17:05:38 +0100", "Message-Id": "<20201211160612.1498780-17-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-0.76 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "9CEBC1843", "X-Rspamd-UID": "bf156f", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-npi-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-npi-defs.h | 1953 +++++++++++++++++\n 1 file changed, 1953 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-npi-defs.h", "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-npi-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-npi-defs.h\nnew file mode 100644\nindex 0000000000..f23ed78ee4\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-npi-defs.h\n@@ -0,0 +1,1953 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon npi.\n+ */\n+\n+#ifndef __CVMX_NPI_DEFS_H__\n+#define __CVMX_NPI_DEFS_H__\n+\n+#define CVMX_NPI_BASE_ADDR_INPUT0\t CVMX_NPI_BASE_ADDR_INPUTX(0)\n+#define CVMX_NPI_BASE_ADDR_INPUT1\t CVMX_NPI_BASE_ADDR_INPUTX(1)\n+#define CVMX_NPI_BASE_ADDR_INPUT2\t CVMX_NPI_BASE_ADDR_INPUTX(2)\n+#define CVMX_NPI_BASE_ADDR_INPUT3\t CVMX_NPI_BASE_ADDR_INPUTX(3)\n+#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (0x00011F0000000070ull + ((offset) & 3) * 16)\n+#define CVMX_NPI_BASE_ADDR_OUTPUT0\t CVMX_NPI_BASE_ADDR_OUTPUTX(0)\n+#define CVMX_NPI_BASE_ADDR_OUTPUT1\t CVMX_NPI_BASE_ADDR_OUTPUTX(1)\n+#define CVMX_NPI_BASE_ADDR_OUTPUT2\t CVMX_NPI_BASE_ADDR_OUTPUTX(2)\n+#define CVMX_NPI_BASE_ADDR_OUTPUT3\t CVMX_NPI_BASE_ADDR_OUTPUTX(3)\n+#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (0x00011F00000000B8ull + ((offset) & 3) * 8)\n+#define CVMX_NPI_BIST_STATUS\t\t (0x00011F00000003F8ull)\n+#define CVMX_NPI_BUFF_SIZE_OUTPUT0\t CVMX_NPI_BUFF_SIZE_OUTPUTX(0)\n+#define CVMX_NPI_BUFF_SIZE_OUTPUT1\t CVMX_NPI_BUFF_SIZE_OUTPUTX(1)\n+#define CVMX_NPI_BUFF_SIZE_OUTPUT2\t CVMX_NPI_BUFF_SIZE_OUTPUTX(2)\n+#define CVMX_NPI_BUFF_SIZE_OUTPUT3\t CVMX_NPI_BUFF_SIZE_OUTPUTX(3)\n+#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (0x00011F00000000E0ull + ((offset) & 3) * 8)\n+#define CVMX_NPI_COMP_CTL\t\t (0x00011F0000000218ull)\n+#define CVMX_NPI_CTL_STATUS\t\t (0x00011F0000000010ull)\n+#define CVMX_NPI_DBG_SELECT\t\t (0x00011F0000000008ull)\n+#define CVMX_NPI_DMA_CONTROL\t\t (0x00011F0000000128ull)\n+#define CVMX_NPI_DMA_HIGHP_COUNTS\t (0x00011F0000000148ull)\n+#define CVMX_NPI_DMA_HIGHP_NADDR\t (0x00011F0000000158ull)\n+#define CVMX_NPI_DMA_LOWP_COUNTS\t (0x00011F0000000140ull)\n+#define CVMX_NPI_DMA_LOWP_NADDR\t\t (0x00011F0000000150ull)\n+#define CVMX_NPI_HIGHP_DBELL\t\t (0x00011F0000000120ull)\n+#define CVMX_NPI_HIGHP_IBUFF_SADDR\t (0x00011F0000000110ull)\n+#define CVMX_NPI_INPUT_CONTROL\t\t (0x00011F0000000138ull)\n+#define CVMX_NPI_INT_ENB\t\t (0x00011F0000000020ull)\n+#define CVMX_NPI_INT_SUM\t\t (0x00011F0000000018ull)\n+#define CVMX_NPI_LOWP_DBELL\t\t (0x00011F0000000118ull)\n+#define CVMX_NPI_LOWP_IBUFF_SADDR\t (0x00011F0000000108ull)\n+#define CVMX_NPI_MEM_ACCESS_SUBID3\t CVMX_NPI_MEM_ACCESS_SUBIDX(3)\n+#define CVMX_NPI_MEM_ACCESS_SUBID4\t CVMX_NPI_MEM_ACCESS_SUBIDX(4)\n+#define CVMX_NPI_MEM_ACCESS_SUBID5\t CVMX_NPI_MEM_ACCESS_SUBIDX(5)\n+#define CVMX_NPI_MEM_ACCESS_SUBID6\t CVMX_NPI_MEM_ACCESS_SUBIDX(6)\n+#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (0x00011F0000000028ull + ((offset) & 7) * 8 - 8 * 3)\n+#define CVMX_NPI_MSI_RCV\t\t (0x0000000000000190ull)\n+#define CVMX_NPI_NPI_MSI_RCV\t\t (0x00011F0000001190ull)\n+#define CVMX_NPI_NUM_DESC_OUTPUT0\t CVMX_NPI_NUM_DESC_OUTPUTX(0)\n+#define CVMX_NPI_NUM_DESC_OUTPUT1\t CVMX_NPI_NUM_DESC_OUTPUTX(1)\n+#define CVMX_NPI_NUM_DESC_OUTPUT2\t CVMX_NPI_NUM_DESC_OUTPUTX(2)\n+#define CVMX_NPI_NUM_DESC_OUTPUT3\t CVMX_NPI_NUM_DESC_OUTPUTX(3)\n+#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (0x00011F0000000050ull + ((offset) & 3) * 8)\n+#define CVMX_NPI_OUTPUT_CONTROL\t\t (0x00011F0000000100ull)\n+#define CVMX_NPI_P0_DBPAIR_ADDR\t\t CVMX_NPI_PX_DBPAIR_ADDR(0)\n+#define CVMX_NPI_P0_INSTR_ADDR\t\t CVMX_NPI_PX_INSTR_ADDR(0)\n+#define CVMX_NPI_P0_INSTR_CNTS\t\t CVMX_NPI_PX_INSTR_CNTS(0)\n+#define CVMX_NPI_P0_PAIR_CNTS\t\t CVMX_NPI_PX_PAIR_CNTS(0)\n+#define CVMX_NPI_P1_DBPAIR_ADDR\t\t CVMX_NPI_PX_DBPAIR_ADDR(1)\n+#define CVMX_NPI_P1_INSTR_ADDR\t\t CVMX_NPI_PX_INSTR_ADDR(1)\n+#define CVMX_NPI_P1_INSTR_CNTS\t\t CVMX_NPI_PX_INSTR_CNTS(1)\n+#define CVMX_NPI_P1_PAIR_CNTS\t\t CVMX_NPI_PX_PAIR_CNTS(1)\n+#define CVMX_NPI_P2_DBPAIR_ADDR\t\t CVMX_NPI_PX_DBPAIR_ADDR(2)\n+#define CVMX_NPI_P2_INSTR_ADDR\t\t CVMX_NPI_PX_INSTR_ADDR(2)\n+#define CVMX_NPI_P2_INSTR_CNTS\t\t CVMX_NPI_PX_INSTR_CNTS(2)\n+#define CVMX_NPI_P2_PAIR_CNTS\t\t CVMX_NPI_PX_PAIR_CNTS(2)\n+#define CVMX_NPI_P3_DBPAIR_ADDR\t\t CVMX_NPI_PX_DBPAIR_ADDR(3)\n+#define CVMX_NPI_P3_INSTR_ADDR\t\t CVMX_NPI_PX_INSTR_ADDR(3)\n+#define CVMX_NPI_P3_INSTR_CNTS\t\t CVMX_NPI_PX_INSTR_CNTS(3)\n+#define CVMX_NPI_P3_PAIR_CNTS\t\t CVMX_NPI_PX_PAIR_CNTS(3)\n+#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (0x00011F0000001100ull + ((offset) & 31) * 4)\n+#define CVMX_NPI_PCI_BIST_REG\t\t (0x00011F00000011C0ull)\n+#define CVMX_NPI_PCI_BURST_SIZE\t\t (0x00011F00000000D8ull)\n+#define CVMX_NPI_PCI_CFG00\t\t (0x00011F0000001800ull)\n+#define CVMX_NPI_PCI_CFG01\t\t (0x00011F0000001804ull)\n+#define CVMX_NPI_PCI_CFG02\t\t (0x00011F0000001808ull)\n+#define CVMX_NPI_PCI_CFG03\t\t (0x00011F000000180Cull)\n+#define CVMX_NPI_PCI_CFG04\t\t (0x00011F0000001810ull)\n+#define CVMX_NPI_PCI_CFG05\t\t (0x00011F0000001814ull)\n+#define CVMX_NPI_PCI_CFG06\t\t (0x00011F0000001818ull)\n+#define CVMX_NPI_PCI_CFG07\t\t (0x00011F000000181Cull)\n+#define CVMX_NPI_PCI_CFG08\t\t (0x00011F0000001820ull)\n+#define CVMX_NPI_PCI_CFG09\t\t (0x00011F0000001824ull)\n+#define CVMX_NPI_PCI_CFG10\t\t (0x00011F0000001828ull)\n+#define CVMX_NPI_PCI_CFG11\t\t (0x00011F000000182Cull)\n+#define CVMX_NPI_PCI_CFG12\t\t (0x00011F0000001830ull)\n+#define CVMX_NPI_PCI_CFG13\t\t (0x00011F0000001834ull)\n+#define CVMX_NPI_PCI_CFG15\t\t (0x00011F000000183Cull)\n+#define CVMX_NPI_PCI_CFG16\t\t (0x00011F0000001840ull)\n+#define CVMX_NPI_PCI_CFG17\t\t (0x00011F0000001844ull)\n+#define CVMX_NPI_PCI_CFG18\t\t (0x00011F0000001848ull)\n+#define CVMX_NPI_PCI_CFG19\t\t (0x00011F000000184Cull)\n+#define CVMX_NPI_PCI_CFG20\t\t (0x00011F0000001850ull)\n+#define CVMX_NPI_PCI_CFG21\t\t (0x00011F0000001854ull)\n+#define CVMX_NPI_PCI_CFG22\t\t (0x00011F0000001858ull)\n+#define CVMX_NPI_PCI_CFG56\t\t (0x00011F00000018E0ull)\n+#define CVMX_NPI_PCI_CFG57\t\t (0x00011F00000018E4ull)\n+#define CVMX_NPI_PCI_CFG58\t\t (0x00011F00000018E8ull)\n+#define CVMX_NPI_PCI_CFG59\t\t (0x00011F00000018ECull)\n+#define CVMX_NPI_PCI_CFG60\t\t (0x00011F00000018F0ull)\n+#define CVMX_NPI_PCI_CFG61\t\t (0x00011F00000018F4ull)\n+#define CVMX_NPI_PCI_CFG62\t\t (0x00011F00000018F8ull)\n+#define CVMX_NPI_PCI_CFG63\t\t (0x00011F00000018FCull)\n+#define CVMX_NPI_PCI_CNT_REG\t\t (0x00011F00000011B8ull)\n+#define CVMX_NPI_PCI_CTL_STATUS_2\t (0x00011F000000118Cull)\n+#define CVMX_NPI_PCI_INT_ARB_CFG\t (0x00011F0000000130ull)\n+#define CVMX_NPI_PCI_INT_ENB2\t\t (0x00011F00000011A0ull)\n+#define CVMX_NPI_PCI_INT_SUM2\t\t (0x00011F0000001198ull)\n+#define CVMX_NPI_PCI_READ_CMD\t\t (0x00011F0000000048ull)\n+#define CVMX_NPI_PCI_READ_CMD_6\t\t (0x00011F0000001180ull)\n+#define CVMX_NPI_PCI_READ_CMD_C\t\t (0x00011F0000001184ull)\n+#define CVMX_NPI_PCI_READ_CMD_E\t\t (0x00011F0000001188ull)\n+#define CVMX_NPI_PCI_SCM_REG\t\t (0x00011F00000011A8ull)\n+#define CVMX_NPI_PCI_TSR_REG\t\t (0x00011F00000011B0ull)\n+#define CVMX_NPI_PORT32_INSTR_HDR\t (0x00011F00000001F8ull)\n+#define CVMX_NPI_PORT33_INSTR_HDR\t (0x00011F0000000200ull)\n+#define CVMX_NPI_PORT34_INSTR_HDR\t (0x00011F0000000208ull)\n+#define CVMX_NPI_PORT35_INSTR_HDR\t (0x00011F0000000210ull)\n+#define CVMX_NPI_PORT_BP_CONTROL\t (0x00011F00000001F0ull)\n+#define CVMX_NPI_PX_DBPAIR_ADDR(offset)\t (0x00011F0000000180ull + ((offset) & 3) * 8)\n+#define CVMX_NPI_PX_INSTR_ADDR(offset)\t (0x00011F00000001C0ull + ((offset) & 3) * 8)\n+#define CVMX_NPI_PX_INSTR_CNTS(offset)\t (0x00011F00000001A0ull + ((offset) & 3) * 8)\n+#define CVMX_NPI_PX_PAIR_CNTS(offset)\t (0x00011F0000000160ull + ((offset) & 3) * 8)\n+#define CVMX_NPI_RSL_INT_BLOCKS\t\t (0x00011F0000000000ull)\n+#define CVMX_NPI_SIZE_INPUT0\t\t CVMX_NPI_SIZE_INPUTX(0)\n+#define CVMX_NPI_SIZE_INPUT1\t\t CVMX_NPI_SIZE_INPUTX(1)\n+#define CVMX_NPI_SIZE_INPUT2\t\t CVMX_NPI_SIZE_INPUTX(2)\n+#define CVMX_NPI_SIZE_INPUT3\t\t CVMX_NPI_SIZE_INPUTX(3)\n+#define CVMX_NPI_SIZE_INPUTX(offset)\t (0x00011F0000000078ull + ((offset) & 3) * 16)\n+#define CVMX_NPI_WIN_READ_TO\t\t (0x00011F00000001E0ull)\n+\n+/**\n+ * cvmx_npi_base_addr_input#\n+ *\n+ * NPI_BASE_ADDR_INPUT0 = NPI's Base Address Input 0 Register\n+ *\n+ * The address to start reading Instructions from for Input-0.\n+ */\n+union cvmx_npi_base_addr_inputx {\n+\tu64 u64;\n+\tstruct cvmx_npi_base_addr_inputx_s {\n+\t\tu64 baddr : 61;\n+\t\tu64 reserved_0_2 : 3;\n+\t} s;\n+\tstruct cvmx_npi_base_addr_inputx_s cn30xx;\n+\tstruct cvmx_npi_base_addr_inputx_s cn31xx;\n+\tstruct cvmx_npi_base_addr_inputx_s cn38xx;\n+\tstruct cvmx_npi_base_addr_inputx_s cn38xxp2;\n+\tstruct cvmx_npi_base_addr_inputx_s cn50xx;\n+\tstruct cvmx_npi_base_addr_inputx_s cn58xx;\n+\tstruct cvmx_npi_base_addr_inputx_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_base_addr_inputx cvmx_npi_base_addr_inputx_t;\n+\n+/**\n+ * cvmx_npi_base_addr_output#\n+ *\n+ * NPI_BASE_ADDR_OUTPUT0 = NPI's Base Address Output 0 Register\n+ *\n+ * The address to start reading Instructions from for Output-0.\n+ */\n+union cvmx_npi_base_addr_outputx {\n+\tu64 u64;\n+\tstruct cvmx_npi_base_addr_outputx_s {\n+\t\tu64 baddr : 61;\n+\t\tu64 reserved_0_2 : 3;\n+\t} s;\n+\tstruct cvmx_npi_base_addr_outputx_s cn30xx;\n+\tstruct cvmx_npi_base_addr_outputx_s cn31xx;\n+\tstruct cvmx_npi_base_addr_outputx_s cn38xx;\n+\tstruct cvmx_npi_base_addr_outputx_s cn38xxp2;\n+\tstruct cvmx_npi_base_addr_outputx_s cn50xx;\n+\tstruct cvmx_npi_base_addr_outputx_s cn58xx;\n+\tstruct cvmx_npi_base_addr_outputx_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_base_addr_outputx cvmx_npi_base_addr_outputx_t;\n+\n+/**\n+ * cvmx_npi_bist_status\n+ *\n+ * NPI_BIST_STATUS = NPI's BIST Status Register\n+ *\n+ * Results from BIST runs of NPI's memories.\n+ */\n+union cvmx_npi_bist_status {\n+\tu64 u64;\n+\tstruct cvmx_npi_bist_status_s {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 csr_bs : 1;\n+\t\tu64 dif_bs : 1;\n+\t\tu64 rdp_bs : 1;\n+\t\tu64 pcnc_bs : 1;\n+\t\tu64 pcn_bs : 1;\n+\t\tu64 rdn_bs : 1;\n+\t\tu64 pcac_bs : 1;\n+\t\tu64 pcad_bs : 1;\n+\t\tu64 rdnl_bs : 1;\n+\t\tu64 pgf_bs : 1;\n+\t\tu64 pig_bs : 1;\n+\t\tu64 pof0_bs : 1;\n+\t\tu64 pof1_bs : 1;\n+\t\tu64 pof2_bs : 1;\n+\t\tu64 pof3_bs : 1;\n+\t\tu64 pos_bs : 1;\n+\t\tu64 nus_bs : 1;\n+\t\tu64 dob_bs : 1;\n+\t\tu64 pdf_bs : 1;\n+\t\tu64 dpi_bs : 1;\n+\t} s;\n+\tstruct cvmx_npi_bist_status_cn30xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 csr_bs : 1;\n+\t\tu64 dif_bs : 1;\n+\t\tu64 rdp_bs : 1;\n+\t\tu64 pcnc_bs : 1;\n+\t\tu64 pcn_bs : 1;\n+\t\tu64 rdn_bs : 1;\n+\t\tu64 pcac_bs : 1;\n+\t\tu64 pcad_bs : 1;\n+\t\tu64 rdnl_bs : 1;\n+\t\tu64 pgf_bs : 1;\n+\t\tu64 pig_bs : 1;\n+\t\tu64 pof0_bs : 1;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 pos_bs : 1;\n+\t\tu64 nus_bs : 1;\n+\t\tu64 dob_bs : 1;\n+\t\tu64 pdf_bs : 1;\n+\t\tu64 dpi_bs : 1;\n+\t} cn30xx;\n+\tstruct cvmx_npi_bist_status_s cn31xx;\n+\tstruct cvmx_npi_bist_status_s cn38xx;\n+\tstruct cvmx_npi_bist_status_s cn38xxp2;\n+\tstruct cvmx_npi_bist_status_cn50xx {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 csr_bs : 1;\n+\t\tu64 dif_bs : 1;\n+\t\tu64 rdp_bs : 1;\n+\t\tu64 pcnc_bs : 1;\n+\t\tu64 pcn_bs : 1;\n+\t\tu64 rdn_bs : 1;\n+\t\tu64 pcac_bs : 1;\n+\t\tu64 pcad_bs : 1;\n+\t\tu64 rdnl_bs : 1;\n+\t\tu64 pgf_bs : 1;\n+\t\tu64 pig_bs : 1;\n+\t\tu64 pof0_bs : 1;\n+\t\tu64 pof1_bs : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 pos_bs : 1;\n+\t\tu64 nus_bs : 1;\n+\t\tu64 dob_bs : 1;\n+\t\tu64 pdf_bs : 1;\n+\t\tu64 dpi_bs : 1;\n+\t} cn50xx;\n+\tstruct cvmx_npi_bist_status_s cn58xx;\n+\tstruct cvmx_npi_bist_status_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_bist_status cvmx_npi_bist_status_t;\n+\n+/**\n+ * cvmx_npi_buff_size_output#\n+ *\n+ * NPI_BUFF_SIZE_OUTPUT0 = NPI's D/I Buffer Sizes For Output 0\n+ *\n+ * The size in bytes of the Data Bufffer and Information Buffer for output 0.\n+ */\n+union cvmx_npi_buff_size_outputx {\n+\tu64 u64;\n+\tstruct cvmx_npi_buff_size_outputx_s {\n+\t\tu64 reserved_23_63 : 41;\n+\t\tu64 isize : 7;\n+\t\tu64 bsize : 16;\n+\t} s;\n+\tstruct cvmx_npi_buff_size_outputx_s cn30xx;\n+\tstruct cvmx_npi_buff_size_outputx_s cn31xx;\n+\tstruct cvmx_npi_buff_size_outputx_s cn38xx;\n+\tstruct cvmx_npi_buff_size_outputx_s cn38xxp2;\n+\tstruct cvmx_npi_buff_size_outputx_s cn50xx;\n+\tstruct cvmx_npi_buff_size_outputx_s cn58xx;\n+\tstruct cvmx_npi_buff_size_outputx_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_buff_size_outputx cvmx_npi_buff_size_outputx_t;\n+\n+/**\n+ * cvmx_npi_comp_ctl\n+ *\n+ * NPI_COMP_CTL = PCI Compensation Control\n+ *\n+ * PCI Compensation Control\n+ */\n+union cvmx_npi_comp_ctl {\n+\tu64 u64;\n+\tstruct cvmx_npi_comp_ctl_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 pctl : 5;\n+\t\tu64 nctl : 5;\n+\t} s;\n+\tstruct cvmx_npi_comp_ctl_s cn50xx;\n+\tstruct cvmx_npi_comp_ctl_s cn58xx;\n+\tstruct cvmx_npi_comp_ctl_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_comp_ctl cvmx_npi_comp_ctl_t;\n+\n+/**\n+ * cvmx_npi_ctl_status\n+ *\n+ * NPI_CTL_STATUS = NPI's Control Status Register\n+ *\n+ * Contains control ans status for NPI.\n+ * Writes to this register are not ordered with writes/reads to the PCI Memory space.\n+ * To ensure that a write has completed the user must read the register before\n+ * making an access(i.e. PCI memory space) that requires the value of this register to be updated.\n+ */\n+union cvmx_npi_ctl_status {\n+\tu64 u64;\n+\tstruct cvmx_npi_ctl_status_s {\n+\t\tu64 reserved_63_63 : 1;\n+\t\tu64 chip_rev : 8;\n+\t\tu64 dis_pniw : 1;\n+\t\tu64 out3_enb : 1;\n+\t\tu64 out2_enb : 1;\n+\t\tu64 out1_enb : 1;\n+\t\tu64 out0_enb : 1;\n+\t\tu64 ins3_enb : 1;\n+\t\tu64 ins2_enb : 1;\n+\t\tu64 ins1_enb : 1;\n+\t\tu64 ins0_enb : 1;\n+\t\tu64 ins3_64b : 1;\n+\t\tu64 ins2_64b : 1;\n+\t\tu64 ins1_64b : 1;\n+\t\tu64 ins0_64b : 1;\n+\t\tu64 pci_wdis : 1;\n+\t\tu64 wait_com : 1;\n+\t\tu64 reserved_37_39 : 3;\n+\t\tu64 max_word : 5;\n+\t\tu64 reserved_10_31 : 22;\n+\t\tu64 timer : 10;\n+\t} s;\n+\tstruct cvmx_npi_ctl_status_cn30xx {\n+\t\tu64 reserved_63_63 : 1;\n+\t\tu64 chip_rev : 8;\n+\t\tu64 dis_pniw : 1;\n+\t\tu64 reserved_51_53 : 3;\n+\t\tu64 out0_enb : 1;\n+\t\tu64 reserved_47_49 : 3;\n+\t\tu64 ins0_enb : 1;\n+\t\tu64 reserved_43_45 : 3;\n+\t\tu64 ins0_64b : 1;\n+\t\tu64 pci_wdis : 1;\n+\t\tu64 wait_com : 1;\n+\t\tu64 reserved_37_39 : 3;\n+\t\tu64 max_word : 5;\n+\t\tu64 reserved_10_31 : 22;\n+\t\tu64 timer : 10;\n+\t} cn30xx;\n+\tstruct cvmx_npi_ctl_status_cn31xx {\n+\t\tu64 reserved_63_63 : 1;\n+\t\tu64 chip_rev : 8;\n+\t\tu64 dis_pniw : 1;\n+\t\tu64 reserved_52_53 : 2;\n+\t\tu64 out1_enb : 1;\n+\t\tu64 out0_enb : 1;\n+\t\tu64 reserved_48_49 : 2;\n+\t\tu64 ins1_enb : 1;\n+\t\tu64 ins0_enb : 1;\n+\t\tu64 reserved_44_45 : 2;\n+\t\tu64 ins1_64b : 1;\n+\t\tu64 ins0_64b : 1;\n+\t\tu64 pci_wdis : 1;\n+\t\tu64 wait_com : 1;\n+\t\tu64 reserved_37_39 : 3;\n+\t\tu64 max_word : 5;\n+\t\tu64 reserved_10_31 : 22;\n+\t\tu64 timer : 10;\n+\t} cn31xx;\n+\tstruct cvmx_npi_ctl_status_s cn38xx;\n+\tstruct cvmx_npi_ctl_status_s cn38xxp2;\n+\tstruct cvmx_npi_ctl_status_cn31xx cn50xx;\n+\tstruct cvmx_npi_ctl_status_s cn58xx;\n+\tstruct cvmx_npi_ctl_status_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_ctl_status cvmx_npi_ctl_status_t;\n+\n+/**\n+ * cvmx_npi_dbg_select\n+ *\n+ * NPI_DBG_SELECT = Debug Select Register\n+ *\n+ * Contains the debug select value in last written to the RSLs.\n+ */\n+union cvmx_npi_dbg_select {\n+\tu64 u64;\n+\tstruct cvmx_npi_dbg_select_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 dbg_sel : 16;\n+\t} s;\n+\tstruct cvmx_npi_dbg_select_s cn30xx;\n+\tstruct cvmx_npi_dbg_select_s cn31xx;\n+\tstruct cvmx_npi_dbg_select_s cn38xx;\n+\tstruct cvmx_npi_dbg_select_s cn38xxp2;\n+\tstruct cvmx_npi_dbg_select_s cn50xx;\n+\tstruct cvmx_npi_dbg_select_s cn58xx;\n+\tstruct cvmx_npi_dbg_select_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_dbg_select cvmx_npi_dbg_select_t;\n+\n+/**\n+ * cvmx_npi_dma_control\n+ *\n+ * NPI_DMA_CONTROL = DMA Control Register\n+ *\n+ * Controls operation of the DMA IN/OUT of the NPI.\n+ */\n+union cvmx_npi_dma_control {\n+\tu64 u64;\n+\tstruct cvmx_npi_dma_control_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 b0_lend : 1;\n+\t\tu64 dwb_denb : 1;\n+\t\tu64 dwb_ichk : 9;\n+\t\tu64 fpa_que : 3;\n+\t\tu64 o_add1 : 1;\n+\t\tu64 o_ro : 1;\n+\t\tu64 o_ns : 1;\n+\t\tu64 o_es : 2;\n+\t\tu64 o_mode : 1;\n+\t\tu64 hp_enb : 1;\n+\t\tu64 lp_enb : 1;\n+\t\tu64 csize : 14;\n+\t} s;\n+\tstruct cvmx_npi_dma_control_s cn30xx;\n+\tstruct cvmx_npi_dma_control_s cn31xx;\n+\tstruct cvmx_npi_dma_control_s cn38xx;\n+\tstruct cvmx_npi_dma_control_s cn38xxp2;\n+\tstruct cvmx_npi_dma_control_s cn50xx;\n+\tstruct cvmx_npi_dma_control_s cn58xx;\n+\tstruct cvmx_npi_dma_control_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_dma_control cvmx_npi_dma_control_t;\n+\n+/**\n+ * cvmx_npi_dma_highp_counts\n+ *\n+ * NPI_DMA_HIGHP_COUNTS = NPI's High Priority DMA Counts\n+ *\n+ * Values for determing the number of instructions for High Priority DMA in the NPI.\n+ */\n+union cvmx_npi_dma_highp_counts {\n+\tu64 u64;\n+\tstruct cvmx_npi_dma_highp_counts_s {\n+\t\tu64 reserved_39_63 : 25;\n+\t\tu64 fcnt : 7;\n+\t\tu64 dbell : 32;\n+\t} s;\n+\tstruct cvmx_npi_dma_highp_counts_s cn30xx;\n+\tstruct cvmx_npi_dma_highp_counts_s cn31xx;\n+\tstruct cvmx_npi_dma_highp_counts_s cn38xx;\n+\tstruct cvmx_npi_dma_highp_counts_s cn38xxp2;\n+\tstruct cvmx_npi_dma_highp_counts_s cn50xx;\n+\tstruct cvmx_npi_dma_highp_counts_s cn58xx;\n+\tstruct cvmx_npi_dma_highp_counts_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_dma_highp_counts cvmx_npi_dma_highp_counts_t;\n+\n+/**\n+ * cvmx_npi_dma_highp_naddr\n+ *\n+ * NPI_DMA_HIGHP_NADDR = NPI's High Priority DMA Next Ichunk Address\n+ *\n+ * Place NPI will read the next Ichunk data from. This is valid when state is 0\n+ */\n+union cvmx_npi_dma_highp_naddr {\n+\tu64 u64;\n+\tstruct cvmx_npi_dma_highp_naddr_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 state : 4;\n+\t\tu64 addr : 36;\n+\t} s;\n+\tstruct cvmx_npi_dma_highp_naddr_s cn30xx;\n+\tstruct cvmx_npi_dma_highp_naddr_s cn31xx;\n+\tstruct cvmx_npi_dma_highp_naddr_s cn38xx;\n+\tstruct cvmx_npi_dma_highp_naddr_s cn38xxp2;\n+\tstruct cvmx_npi_dma_highp_naddr_s cn50xx;\n+\tstruct cvmx_npi_dma_highp_naddr_s cn58xx;\n+\tstruct cvmx_npi_dma_highp_naddr_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_dma_highp_naddr cvmx_npi_dma_highp_naddr_t;\n+\n+/**\n+ * cvmx_npi_dma_lowp_counts\n+ *\n+ * NPI_DMA_LOWP_COUNTS = NPI's Low Priority DMA Counts\n+ *\n+ * Values for determing the number of instructions for Low Priority DMA in the NPI.\n+ */\n+union cvmx_npi_dma_lowp_counts {\n+\tu64 u64;\n+\tstruct cvmx_npi_dma_lowp_counts_s {\n+\t\tu64 reserved_39_63 : 25;\n+\t\tu64 fcnt : 7;\n+\t\tu64 dbell : 32;\n+\t} s;\n+\tstruct cvmx_npi_dma_lowp_counts_s cn30xx;\n+\tstruct cvmx_npi_dma_lowp_counts_s cn31xx;\n+\tstruct cvmx_npi_dma_lowp_counts_s cn38xx;\n+\tstruct cvmx_npi_dma_lowp_counts_s cn38xxp2;\n+\tstruct cvmx_npi_dma_lowp_counts_s cn50xx;\n+\tstruct cvmx_npi_dma_lowp_counts_s cn58xx;\n+\tstruct cvmx_npi_dma_lowp_counts_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_dma_lowp_counts cvmx_npi_dma_lowp_counts_t;\n+\n+/**\n+ * cvmx_npi_dma_lowp_naddr\n+ *\n+ * NPI_DMA_LOWP_NADDR = NPI's Low Priority DMA Next Ichunk Address\n+ *\n+ * Place NPI will read the next Ichunk data from. This is valid when state is 0\n+ */\n+union cvmx_npi_dma_lowp_naddr {\n+\tu64 u64;\n+\tstruct cvmx_npi_dma_lowp_naddr_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 state : 4;\n+\t\tu64 addr : 36;\n+\t} s;\n+\tstruct cvmx_npi_dma_lowp_naddr_s cn30xx;\n+\tstruct cvmx_npi_dma_lowp_naddr_s cn31xx;\n+\tstruct cvmx_npi_dma_lowp_naddr_s cn38xx;\n+\tstruct cvmx_npi_dma_lowp_naddr_s cn38xxp2;\n+\tstruct cvmx_npi_dma_lowp_naddr_s cn50xx;\n+\tstruct cvmx_npi_dma_lowp_naddr_s cn58xx;\n+\tstruct cvmx_npi_dma_lowp_naddr_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_dma_lowp_naddr cvmx_npi_dma_lowp_naddr_t;\n+\n+/**\n+ * cvmx_npi_highp_dbell\n+ *\n+ * NPI_HIGHP_DBELL = High Priority Door Bell\n+ *\n+ * The door bell register for the high priority DMA queue.\n+ */\n+union cvmx_npi_highp_dbell {\n+\tu64 u64;\n+\tstruct cvmx_npi_highp_dbell_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 dbell : 16;\n+\t} s;\n+\tstruct cvmx_npi_highp_dbell_s cn30xx;\n+\tstruct cvmx_npi_highp_dbell_s cn31xx;\n+\tstruct cvmx_npi_highp_dbell_s cn38xx;\n+\tstruct cvmx_npi_highp_dbell_s cn38xxp2;\n+\tstruct cvmx_npi_highp_dbell_s cn50xx;\n+\tstruct cvmx_npi_highp_dbell_s cn58xx;\n+\tstruct cvmx_npi_highp_dbell_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_highp_dbell cvmx_npi_highp_dbell_t;\n+\n+/**\n+ * cvmx_npi_highp_ibuff_saddr\n+ *\n+ * NPI_HIGHP_IBUFF_SADDR = DMA High Priority Instruction Buffer Starting Address\n+ *\n+ * The address to start reading Instructions from for HIGHP.\n+ */\n+union cvmx_npi_highp_ibuff_saddr {\n+\tu64 u64;\n+\tstruct cvmx_npi_highp_ibuff_saddr_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 saddr : 36;\n+\t} s;\n+\tstruct cvmx_npi_highp_ibuff_saddr_s cn30xx;\n+\tstruct cvmx_npi_highp_ibuff_saddr_s cn31xx;\n+\tstruct cvmx_npi_highp_ibuff_saddr_s cn38xx;\n+\tstruct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;\n+\tstruct cvmx_npi_highp_ibuff_saddr_s cn50xx;\n+\tstruct cvmx_npi_highp_ibuff_saddr_s cn58xx;\n+\tstruct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_highp_ibuff_saddr cvmx_npi_highp_ibuff_saddr_t;\n+\n+/**\n+ * cvmx_npi_input_control\n+ *\n+ * NPI_INPUT_CONTROL = NPI's Input Control Register\n+ *\n+ * Control for reads for gather list and instructions.\n+ */\n+union cvmx_npi_input_control {\n+\tu64 u64;\n+\tstruct cvmx_npi_input_control_s {\n+\t\tu64 reserved_23_63 : 41;\n+\t\tu64 pkt_rr : 1;\n+\t\tu64 pbp_dhi : 13;\n+\t\tu64 d_nsr : 1;\n+\t\tu64 d_esr : 2;\n+\t\tu64 d_ror : 1;\n+\t\tu64 use_csr : 1;\n+\t\tu64 nsr : 1;\n+\t\tu64 esr : 2;\n+\t\tu64 ror : 1;\n+\t} s;\n+\tstruct cvmx_npi_input_control_cn30xx {\n+\t\tu64 reserved_22_63 : 42;\n+\t\tu64 pbp_dhi : 13;\n+\t\tu64 d_nsr : 1;\n+\t\tu64 d_esr : 2;\n+\t\tu64 d_ror : 1;\n+\t\tu64 use_csr : 1;\n+\t\tu64 nsr : 1;\n+\t\tu64 esr : 2;\n+\t\tu64 ror : 1;\n+\t} cn30xx;\n+\tstruct cvmx_npi_input_control_cn30xx cn31xx;\n+\tstruct cvmx_npi_input_control_s cn38xx;\n+\tstruct cvmx_npi_input_control_cn30xx cn38xxp2;\n+\tstruct cvmx_npi_input_control_s cn50xx;\n+\tstruct cvmx_npi_input_control_s cn58xx;\n+\tstruct cvmx_npi_input_control_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_input_control cvmx_npi_input_control_t;\n+\n+/**\n+ * cvmx_npi_int_enb\n+ *\n+ * NPI_INTERRUPT_ENB = NPI's Interrupt Enable Register\n+ *\n+ * Used to enable the various interrupting conditions of NPI\n+ */\n+union cvmx_npi_int_enb {\n+\tu64 u64;\n+\tstruct cvmx_npi_int_enb_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 q1_a_f : 1;\n+\t\tu64 q1_s_e : 1;\n+\t\tu64 pdf_p_f : 1;\n+\t\tu64 pdf_p_e : 1;\n+\t\tu64 pcf_p_f : 1;\n+\t\tu64 pcf_p_e : 1;\n+\t\tu64 rdx_s_e : 1;\n+\t\tu64 rwx_s_e : 1;\n+\t\tu64 pnc_a_f : 1;\n+\t\tu64 pnc_s_e : 1;\n+\t\tu64 com_a_f : 1;\n+\t\tu64 com_s_e : 1;\n+\t\tu64 q3_a_f : 1;\n+\t\tu64 q3_s_e : 1;\n+\t\tu64 q2_a_f : 1;\n+\t\tu64 q2_s_e : 1;\n+\t\tu64 pcr_a_f : 1;\n+\t\tu64 pcr_s_e : 1;\n+\t\tu64 fcr_a_f : 1;\n+\t\tu64 fcr_s_e : 1;\n+\t\tu64 iobdma : 1;\n+\t\tu64 p_dperr : 1;\n+\t\tu64 win_rto : 1;\n+\t\tu64 i3_pperr : 1;\n+\t\tu64 i2_pperr : 1;\n+\t\tu64 i1_pperr : 1;\n+\t\tu64 i0_pperr : 1;\n+\t\tu64 p3_ptout : 1;\n+\t\tu64 p2_ptout : 1;\n+\t\tu64 p1_ptout : 1;\n+\t\tu64 p0_ptout : 1;\n+\t\tu64 p3_pperr : 1;\n+\t\tu64 p2_pperr : 1;\n+\t\tu64 p1_pperr : 1;\n+\t\tu64 p0_pperr : 1;\n+\t\tu64 g3_rtout : 1;\n+\t\tu64 g2_rtout : 1;\n+\t\tu64 g1_rtout : 1;\n+\t\tu64 g0_rtout : 1;\n+\t\tu64 p3_perr : 1;\n+\t\tu64 p2_perr : 1;\n+\t\tu64 p1_perr : 1;\n+\t\tu64 p0_perr : 1;\n+\t\tu64 p3_rtout : 1;\n+\t\tu64 p2_rtout : 1;\n+\t\tu64 p1_rtout : 1;\n+\t\tu64 p0_rtout : 1;\n+\t\tu64 i3_overf : 1;\n+\t\tu64 i2_overf : 1;\n+\t\tu64 i1_overf : 1;\n+\t\tu64 i0_overf : 1;\n+\t\tu64 i3_rtout : 1;\n+\t\tu64 i2_rtout : 1;\n+\t\tu64 i1_rtout : 1;\n+\t\tu64 i0_rtout : 1;\n+\t\tu64 po3_2sml : 1;\n+\t\tu64 po2_2sml : 1;\n+\t\tu64 po1_2sml : 1;\n+\t\tu64 po0_2sml : 1;\n+\t\tu64 pci_rsl : 1;\n+\t\tu64 rml_wto : 1;\n+\t\tu64 rml_rto : 1;\n+\t} s;\n+\tstruct cvmx_npi_int_enb_cn30xx {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 q1_a_f : 1;\n+\t\tu64 q1_s_e : 1;\n+\t\tu64 pdf_p_f : 1;\n+\t\tu64 pdf_p_e : 1;\n+\t\tu64 pcf_p_f : 1;\n+\t\tu64 pcf_p_e : 1;\n+\t\tu64 rdx_s_e : 1;\n+\t\tu64 rwx_s_e : 1;\n+\t\tu64 pnc_a_f : 1;\n+\t\tu64 pnc_s_e : 1;\n+\t\tu64 com_a_f : 1;\n+\t\tu64 com_s_e : 1;\n+\t\tu64 q3_a_f : 1;\n+\t\tu64 q3_s_e : 1;\n+\t\tu64 q2_a_f : 1;\n+\t\tu64 q2_s_e : 1;\n+\t\tu64 pcr_a_f : 1;\n+\t\tu64 pcr_s_e : 1;\n+\t\tu64 fcr_a_f : 1;\n+\t\tu64 fcr_s_e : 1;\n+\t\tu64 iobdma : 1;\n+\t\tu64 p_dperr : 1;\n+\t\tu64 win_rto : 1;\n+\t\tu64 reserved_36_38 : 3;\n+\t\tu64 i0_pperr : 1;\n+\t\tu64 reserved_32_34 : 3;\n+\t\tu64 p0_ptout : 1;\n+\t\tu64 reserved_28_30 : 3;\n+\t\tu64 p0_pperr : 1;\n+\t\tu64 reserved_24_26 : 3;\n+\t\tu64 g0_rtout : 1;\n+\t\tu64 reserved_20_22 : 3;\n+\t\tu64 p0_perr : 1;\n+\t\tu64 reserved_16_18 : 3;\n+\t\tu64 p0_rtout : 1;\n+\t\tu64 reserved_12_14 : 3;\n+\t\tu64 i0_overf : 1;\n+\t\tu64 reserved_8_10 : 3;\n+\t\tu64 i0_rtout : 1;\n+\t\tu64 reserved_4_6 : 3;\n+\t\tu64 po0_2sml : 1;\n+\t\tu64 pci_rsl : 1;\n+\t\tu64 rml_wto : 1;\n+\t\tu64 rml_rto : 1;\n+\t} cn30xx;\n+\tstruct cvmx_npi_int_enb_cn31xx {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 q1_a_f : 1;\n+\t\tu64 q1_s_e : 1;\n+\t\tu64 pdf_p_f : 1;\n+\t\tu64 pdf_p_e : 1;\n+\t\tu64 pcf_p_f : 1;\n+\t\tu64 pcf_p_e : 1;\n+\t\tu64 rdx_s_e : 1;\n+\t\tu64 rwx_s_e : 1;\n+\t\tu64 pnc_a_f : 1;\n+\t\tu64 pnc_s_e : 1;\n+\t\tu64 com_a_f : 1;\n+\t\tu64 com_s_e : 1;\n+\t\tu64 q3_a_f : 1;\n+\t\tu64 q3_s_e : 1;\n+\t\tu64 q2_a_f : 1;\n+\t\tu64 q2_s_e : 1;\n+\t\tu64 pcr_a_f : 1;\n+\t\tu64 pcr_s_e : 1;\n+\t\tu64 fcr_a_f : 1;\n+\t\tu64 fcr_s_e : 1;\n+\t\tu64 iobdma : 1;\n+\t\tu64 p_dperr : 1;\n+\t\tu64 win_rto : 1;\n+\t\tu64 reserved_37_38 : 2;\n+\t\tu64 i1_pperr : 1;\n+\t\tu64 i0_pperr : 1;\n+\t\tu64 reserved_33_34 : 2;\n+\t\tu64 p1_ptout : 1;\n+\t\tu64 p0_ptout : 1;\n+\t\tu64 reserved_29_30 : 2;\n+\t\tu64 p1_pperr : 1;\n+\t\tu64 p0_pperr : 1;\n+\t\tu64 reserved_25_26 : 2;\n+\t\tu64 g1_rtout : 1;\n+\t\tu64 g0_rtout : 1;\n+\t\tu64 reserved_21_22 : 2;\n+\t\tu64 p1_perr : 1;\n+\t\tu64 p0_perr : 1;\n+\t\tu64 reserved_17_18 : 2;\n+\t\tu64 p1_rtout : 1;\n+\t\tu64 p0_rtout : 1;\n+\t\tu64 reserved_13_14 : 2;\n+\t\tu64 i1_overf : 1;\n+\t\tu64 i0_overf : 1;\n+\t\tu64 reserved_9_10 : 2;\n+\t\tu64 i1_rtout : 1;\n+\t\tu64 i0_rtout : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 po1_2sml : 1;\n+\t\tu64 po0_2sml : 1;\n+\t\tu64 pci_rsl : 1;\n+\t\tu64 rml_wto : 1;\n+\t\tu64 rml_rto : 1;\n+\t} cn31xx;\n+\tstruct cvmx_npi_int_enb_s cn38xx;\n+\tstruct cvmx_npi_int_enb_cn38xxp2 {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 iobdma : 1;\n+\t\tu64 p_dperr : 1;\n+\t\tu64 win_rto : 1;\n+\t\tu64 i3_pperr : 1;\n+\t\tu64 i2_pperr : 1;\n+\t\tu64 i1_pperr : 1;\n+\t\tu64 i0_pperr : 1;\n+\t\tu64 p3_ptout : 1;\n+\t\tu64 p2_ptout : 1;\n+\t\tu64 p1_ptout : 1;\n+\t\tu64 p0_ptout : 1;\n+\t\tu64 p3_pperr : 1;\n+\t\tu64 p2_pperr : 1;\n+\t\tu64 p1_pperr : 1;\n+\t\tu64 p0_pperr : 1;\n+\t\tu64 g3_rtout : 1;\n+\t\tu64 g2_rtout : 1;\n+\t\tu64 g1_rtout : 1;\n+\t\tu64 g0_rtout : 1;\n+\t\tu64 p3_perr : 1;\n+\t\tu64 p2_perr : 1;\n+\t\tu64 p1_perr : 1;\n+\t\tu64 p0_perr : 1;\n+\t\tu64 p3_rtout : 1;\n+\t\tu64 p2_rtout : 1;\n+\t\tu64 p1_rtout : 1;\n+\t\tu64 p0_rtout : 1;\n+\t\tu64 i3_overf : 1;\n+\t\tu64 i2_overf : 1;\n+\t\tu64 i1_overf : 1;\n+\t\tu64 i0_overf : 1;\n+\t\tu64 i3_rtout : 1;\n+\t\tu64 i2_rtout : 1;\n+\t\tu64 i1_rtout : 1;\n+\t\tu64 i0_rtout : 1;\n+\t\tu64 po3_2sml : 1;\n+\t\tu64 po2_2sml : 1;\n+\t\tu64 po1_2sml : 1;\n+\t\tu64 po0_2sml : 1;\n+\t\tu64 pci_rsl : 1;\n+\t\tu64 rml_wto : 1;\n+\t\tu64 rml_rto : 1;\n+\t} cn38xxp2;\n+\tstruct cvmx_npi_int_enb_cn31xx cn50xx;\n+\tstruct cvmx_npi_int_enb_s cn58xx;\n+\tstruct cvmx_npi_int_enb_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_int_enb cvmx_npi_int_enb_t;\n+\n+/**\n+ * cvmx_npi_int_sum\n+ *\n+ * NPI_INTERRUPT_SUM = NPI Interrupt Summary Register\n+ *\n+ * Set when an interrupt condition occurs, write '1' to clear.\n+ */\n+union cvmx_npi_int_sum {\n+\tu64 u64;\n+\tstruct cvmx_npi_int_sum_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 q1_a_f : 1;\n+\t\tu64 q1_s_e : 1;\n+\t\tu64 pdf_p_f : 1;\n+\t\tu64 pdf_p_e : 1;\n+\t\tu64 pcf_p_f : 1;\n+\t\tu64 pcf_p_e : 1;\n+\t\tu64 rdx_s_e : 1;\n+\t\tu64 rwx_s_e : 1;\n+\t\tu64 pnc_a_f : 1;\n+\t\tu64 pnc_s_e : 1;\n+\t\tu64 com_a_f : 1;\n+\t\tu64 com_s_e : 1;\n+\t\tu64 q3_a_f : 1;\n+\t\tu64 q3_s_e : 1;\n+\t\tu64 q2_a_f : 1;\n+\t\tu64 q2_s_e : 1;\n+\t\tu64 pcr_a_f : 1;\n+\t\tu64 pcr_s_e : 1;\n+\t\tu64 fcr_a_f : 1;\n+\t\tu64 fcr_s_e : 1;\n+\t\tu64 iobdma : 1;\n+\t\tu64 p_dperr : 1;\n+\t\tu64 win_rto : 1;\n+\t\tu64 i3_pperr : 1;\n+\t\tu64 i2_pperr : 1;\n+\t\tu64 i1_pperr : 1;\n+\t\tu64 i0_pperr : 1;\n+\t\tu64 p3_ptout : 1;\n+\t\tu64 p2_ptout : 1;\n+\t\tu64 p1_ptout : 1;\n+\t\tu64 p0_ptout : 1;\n+\t\tu64 p3_pperr : 1;\n+\t\tu64 p2_pperr : 1;\n+\t\tu64 p1_pperr : 1;\n+\t\tu64 p0_pperr : 1;\n+\t\tu64 g3_rtout : 1;\n+\t\tu64 g2_rtout : 1;\n+\t\tu64 g1_rtout : 1;\n+\t\tu64 g0_rtout : 1;\n+\t\tu64 p3_perr : 1;\n+\t\tu64 p2_perr : 1;\n+\t\tu64 p1_perr : 1;\n+\t\tu64 p0_perr : 1;\n+\t\tu64 p3_rtout : 1;\n+\t\tu64 p2_rtout : 1;\n+\t\tu64 p1_rtout : 1;\n+\t\tu64 p0_rtout : 1;\n+\t\tu64 i3_overf : 1;\n+\t\tu64 i2_overf : 1;\n+\t\tu64 i1_overf : 1;\n+\t\tu64 i0_overf : 1;\n+\t\tu64 i3_rtout : 1;\n+\t\tu64 i2_rtout : 1;\n+\t\tu64 i1_rtout : 1;\n+\t\tu64 i0_rtout : 1;\n+\t\tu64 po3_2sml : 1;\n+\t\tu64 po2_2sml : 1;\n+\t\tu64 po1_2sml : 1;\n+\t\tu64 po0_2sml : 1;\n+\t\tu64 pci_rsl : 1;\n+\t\tu64 rml_wto : 1;\n+\t\tu64 rml_rto : 1;\n+\t} s;\n+\tstruct cvmx_npi_int_sum_cn30xx {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 q1_a_f : 1;\n+\t\tu64 q1_s_e : 1;\n+\t\tu64 pdf_p_f : 1;\n+\t\tu64 pdf_p_e : 1;\n+\t\tu64 pcf_p_f : 1;\n+\t\tu64 pcf_p_e : 1;\n+\t\tu64 rdx_s_e : 1;\n+\t\tu64 rwx_s_e : 1;\n+\t\tu64 pnc_a_f : 1;\n+\t\tu64 pnc_s_e : 1;\n+\t\tu64 com_a_f : 1;\n+\t\tu64 com_s_e : 1;\n+\t\tu64 q3_a_f : 1;\n+\t\tu64 q3_s_e : 1;\n+\t\tu64 q2_a_f : 1;\n+\t\tu64 q2_s_e : 1;\n+\t\tu64 pcr_a_f : 1;\n+\t\tu64 pcr_s_e : 1;\n+\t\tu64 fcr_a_f : 1;\n+\t\tu64 fcr_s_e : 1;\n+\t\tu64 iobdma : 1;\n+\t\tu64 p_dperr : 1;\n+\t\tu64 win_rto : 1;\n+\t\tu64 reserved_36_38 : 3;\n+\t\tu64 i0_pperr : 1;\n+\t\tu64 reserved_32_34 : 3;\n+\t\tu64 p0_ptout : 1;\n+\t\tu64 reserved_28_30 : 3;\n+\t\tu64 p0_pperr : 1;\n+\t\tu64 reserved_24_26 : 3;\n+\t\tu64 g0_rtout : 1;\n+\t\tu64 reserved_20_22 : 3;\n+\t\tu64 p0_perr : 1;\n+\t\tu64 reserved_16_18 : 3;\n+\t\tu64 p0_rtout : 1;\n+\t\tu64 reserved_12_14 : 3;\n+\t\tu64 i0_overf : 1;\n+\t\tu64 reserved_8_10 : 3;\n+\t\tu64 i0_rtout : 1;\n+\t\tu64 reserved_4_6 : 3;\n+\t\tu64 po0_2sml : 1;\n+\t\tu64 pci_rsl : 1;\n+\t\tu64 rml_wto : 1;\n+\t\tu64 rml_rto : 1;\n+\t} cn30xx;\n+\tstruct cvmx_npi_int_sum_cn31xx {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 q1_a_f : 1;\n+\t\tu64 q1_s_e : 1;\n+\t\tu64 pdf_p_f : 1;\n+\t\tu64 pdf_p_e : 1;\n+\t\tu64 pcf_p_f : 1;\n+\t\tu64 pcf_p_e : 1;\n+\t\tu64 rdx_s_e : 1;\n+\t\tu64 rwx_s_e : 1;\n+\t\tu64 pnc_a_f : 1;\n+\t\tu64 pnc_s_e : 1;\n+\t\tu64 com_a_f : 1;\n+\t\tu64 com_s_e : 1;\n+\t\tu64 q3_a_f : 1;\n+\t\tu64 q3_s_e : 1;\n+\t\tu64 q2_a_f : 1;\n+\t\tu64 q2_s_e : 1;\n+\t\tu64 pcr_a_f : 1;\n+\t\tu64 pcr_s_e : 1;\n+\t\tu64 fcr_a_f : 1;\n+\t\tu64 fcr_s_e : 1;\n+\t\tu64 iobdma : 1;\n+\t\tu64 p_dperr : 1;\n+\t\tu64 win_rto : 1;\n+\t\tu64 reserved_37_38 : 2;\n+\t\tu64 i1_pperr : 1;\n+\t\tu64 i0_pperr : 1;\n+\t\tu64 reserved_33_34 : 2;\n+\t\tu64 p1_ptout : 1;\n+\t\tu64 p0_ptout : 1;\n+\t\tu64 reserved_29_30 : 2;\n+\t\tu64 p1_pperr : 1;\n+\t\tu64 p0_pperr : 1;\n+\t\tu64 reserved_25_26 : 2;\n+\t\tu64 g1_rtout : 1;\n+\t\tu64 g0_rtout : 1;\n+\t\tu64 reserved_21_22 : 2;\n+\t\tu64 p1_perr : 1;\n+\t\tu64 p0_perr : 1;\n+\t\tu64 reserved_17_18 : 2;\n+\t\tu64 p1_rtout : 1;\n+\t\tu64 p0_rtout : 1;\n+\t\tu64 reserved_13_14 : 2;\n+\t\tu64 i1_overf : 1;\n+\t\tu64 i0_overf : 1;\n+\t\tu64 reserved_9_10 : 2;\n+\t\tu64 i1_rtout : 1;\n+\t\tu64 i0_rtout : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 po1_2sml : 1;\n+\t\tu64 po0_2sml : 1;\n+\t\tu64 pci_rsl : 1;\n+\t\tu64 rml_wto : 1;\n+\t\tu64 rml_rto : 1;\n+\t} cn31xx;\n+\tstruct cvmx_npi_int_sum_s cn38xx;\n+\tstruct cvmx_npi_int_sum_cn38xxp2 {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 iobdma : 1;\n+\t\tu64 p_dperr : 1;\n+\t\tu64 win_rto : 1;\n+\t\tu64 i3_pperr : 1;\n+\t\tu64 i2_pperr : 1;\n+\t\tu64 i1_pperr : 1;\n+\t\tu64 i0_pperr : 1;\n+\t\tu64 p3_ptout : 1;\n+\t\tu64 p2_ptout : 1;\n+\t\tu64 p1_ptout : 1;\n+\t\tu64 p0_ptout : 1;\n+\t\tu64 p3_pperr : 1;\n+\t\tu64 p2_pperr : 1;\n+\t\tu64 p1_pperr : 1;\n+\t\tu64 p0_pperr : 1;\n+\t\tu64 g3_rtout : 1;\n+\t\tu64 g2_rtout : 1;\n+\t\tu64 g1_rtout : 1;\n+\t\tu64 g0_rtout : 1;\n+\t\tu64 p3_perr : 1;\n+\t\tu64 p2_perr : 1;\n+\t\tu64 p1_perr : 1;\n+\t\tu64 p0_perr : 1;\n+\t\tu64 p3_rtout : 1;\n+\t\tu64 p2_rtout : 1;\n+\t\tu64 p1_rtout : 1;\n+\t\tu64 p0_rtout : 1;\n+\t\tu64 i3_overf : 1;\n+\t\tu64 i2_overf : 1;\n+\t\tu64 i1_overf : 1;\n+\t\tu64 i0_overf : 1;\n+\t\tu64 i3_rtout : 1;\n+\t\tu64 i2_rtout : 1;\n+\t\tu64 i1_rtout : 1;\n+\t\tu64 i0_rtout : 1;\n+\t\tu64 po3_2sml : 1;\n+\t\tu64 po2_2sml : 1;\n+\t\tu64 po1_2sml : 1;\n+\t\tu64 po0_2sml : 1;\n+\t\tu64 pci_rsl : 1;\n+\t\tu64 rml_wto : 1;\n+\t\tu64 rml_rto : 1;\n+\t} cn38xxp2;\n+\tstruct cvmx_npi_int_sum_cn31xx cn50xx;\n+\tstruct cvmx_npi_int_sum_s cn58xx;\n+\tstruct cvmx_npi_int_sum_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_int_sum cvmx_npi_int_sum_t;\n+\n+/**\n+ * cvmx_npi_lowp_dbell\n+ *\n+ * NPI_LOWP_DBELL = Low Priority Door Bell\n+ *\n+ * The door bell register for the low priority DMA queue.\n+ */\n+union cvmx_npi_lowp_dbell {\n+\tu64 u64;\n+\tstruct cvmx_npi_lowp_dbell_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 dbell : 16;\n+\t} s;\n+\tstruct cvmx_npi_lowp_dbell_s cn30xx;\n+\tstruct cvmx_npi_lowp_dbell_s cn31xx;\n+\tstruct cvmx_npi_lowp_dbell_s cn38xx;\n+\tstruct cvmx_npi_lowp_dbell_s cn38xxp2;\n+\tstruct cvmx_npi_lowp_dbell_s cn50xx;\n+\tstruct cvmx_npi_lowp_dbell_s cn58xx;\n+\tstruct cvmx_npi_lowp_dbell_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_lowp_dbell cvmx_npi_lowp_dbell_t;\n+\n+/**\n+ * cvmx_npi_lowp_ibuff_saddr\n+ *\n+ * NPI_LOWP_IBUFF_SADDR = DMA Low Priority's Instruction Buffer Starting Address\n+ *\n+ * The address to start reading Instructions from for LOWP.\n+ */\n+union cvmx_npi_lowp_ibuff_saddr {\n+\tu64 u64;\n+\tstruct cvmx_npi_lowp_ibuff_saddr_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 saddr : 36;\n+\t} s;\n+\tstruct cvmx_npi_lowp_ibuff_saddr_s cn30xx;\n+\tstruct cvmx_npi_lowp_ibuff_saddr_s cn31xx;\n+\tstruct cvmx_npi_lowp_ibuff_saddr_s cn38xx;\n+\tstruct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;\n+\tstruct cvmx_npi_lowp_ibuff_saddr_s cn50xx;\n+\tstruct cvmx_npi_lowp_ibuff_saddr_s cn58xx;\n+\tstruct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_lowp_ibuff_saddr cvmx_npi_lowp_ibuff_saddr_t;\n+\n+/**\n+ * cvmx_npi_mem_access_subid#\n+ *\n+ * NPI_MEM_ACCESS_SUBID3 = Memory Access SubId 3Register\n+ *\n+ * Carries Read/Write parameters for PP access to PCI memory that use NPI SubId3.\n+ * Writes to this register are not ordered with writes/reads to the PCI Memory space.\n+ * To ensure that a write has completed the user must read the register before\n+ * making an access(i.e. PCI memory space) that requires the value of this register to be updated.\n+ */\n+union cvmx_npi_mem_access_subidx {\n+\tu64 u64;\n+\tstruct cvmx_npi_mem_access_subidx_s {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 shortl : 1;\n+\t\tu64 nmerge : 1;\n+\t\tu64 esr : 2;\n+\t\tu64 esw : 2;\n+\t\tu64 nsr : 1;\n+\t\tu64 nsw : 1;\n+\t\tu64 ror : 1;\n+\t\tu64 row : 1;\n+\t\tu64 ba : 28;\n+\t} s;\n+\tstruct cvmx_npi_mem_access_subidx_s cn30xx;\n+\tstruct cvmx_npi_mem_access_subidx_cn31xx {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 esr : 2;\n+\t\tu64 esw : 2;\n+\t\tu64 nsr : 1;\n+\t\tu64 nsw : 1;\n+\t\tu64 ror : 1;\n+\t\tu64 row : 1;\n+\t\tu64 ba : 28;\n+\t} cn31xx;\n+\tstruct cvmx_npi_mem_access_subidx_s cn38xx;\n+\tstruct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;\n+\tstruct cvmx_npi_mem_access_subidx_s cn50xx;\n+\tstruct cvmx_npi_mem_access_subidx_s cn58xx;\n+\tstruct cvmx_npi_mem_access_subidx_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_mem_access_subidx cvmx_npi_mem_access_subidx_t;\n+\n+/**\n+ * cvmx_npi_msi_rcv\n+ *\n+ * NPI_MSI_RCV = NPI MSI Receive Vector Register\n+ *\n+ * A bit is set in this register relative to the vector received during a MSI. And cleared by a W1 to the register.\n+ */\n+union cvmx_npi_msi_rcv {\n+\tu64 u64;\n+\tstruct cvmx_npi_msi_rcv_s {\n+\t\tu64 int_vec : 64;\n+\t} s;\n+\tstruct cvmx_npi_msi_rcv_s cn30xx;\n+\tstruct cvmx_npi_msi_rcv_s cn31xx;\n+\tstruct cvmx_npi_msi_rcv_s cn38xx;\n+\tstruct cvmx_npi_msi_rcv_s cn38xxp2;\n+\tstruct cvmx_npi_msi_rcv_s cn50xx;\n+\tstruct cvmx_npi_msi_rcv_s cn58xx;\n+\tstruct cvmx_npi_msi_rcv_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_msi_rcv cvmx_npi_msi_rcv_t;\n+\n+/**\n+ * cvmx_npi_num_desc_output#\n+ *\n+ * NUM_DESC_OUTPUT0 = Number Of Descriptors Available For Output 0\n+ *\n+ * The size of the Buffer/Info Pointer Pair ring for Output-0.\n+ */\n+union cvmx_npi_num_desc_outputx {\n+\tu64 u64;\n+\tstruct cvmx_npi_num_desc_outputx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 size : 32;\n+\t} s;\n+\tstruct cvmx_npi_num_desc_outputx_s cn30xx;\n+\tstruct cvmx_npi_num_desc_outputx_s cn31xx;\n+\tstruct cvmx_npi_num_desc_outputx_s cn38xx;\n+\tstruct cvmx_npi_num_desc_outputx_s cn38xxp2;\n+\tstruct cvmx_npi_num_desc_outputx_s cn50xx;\n+\tstruct cvmx_npi_num_desc_outputx_s cn58xx;\n+\tstruct cvmx_npi_num_desc_outputx_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_num_desc_outputx cvmx_npi_num_desc_outputx_t;\n+\n+/**\n+ * cvmx_npi_output_control\n+ *\n+ * NPI_OUTPUT_CONTROL = NPI's Output Control Register\n+ *\n+ * The address to start reading Instructions from for Output-3.\n+ */\n+union cvmx_npi_output_control {\n+\tu64 u64;\n+\tstruct cvmx_npi_output_control_s {\n+\t\tu64 reserved_49_63 : 15;\n+\t\tu64 pkt_rr : 1;\n+\t\tu64 p3_bmode : 1;\n+\t\tu64 p2_bmode : 1;\n+\t\tu64 p1_bmode : 1;\n+\t\tu64 p0_bmode : 1;\n+\t\tu64 o3_es : 2;\n+\t\tu64 o3_ns : 1;\n+\t\tu64 o3_ro : 1;\n+\t\tu64 o2_es : 2;\n+\t\tu64 o2_ns : 1;\n+\t\tu64 o2_ro : 1;\n+\t\tu64 o1_es : 2;\n+\t\tu64 o1_ns : 1;\n+\t\tu64 o1_ro : 1;\n+\t\tu64 o0_es : 2;\n+\t\tu64 o0_ns : 1;\n+\t\tu64 o0_ro : 1;\n+\t\tu64 o3_csrm : 1;\n+\t\tu64 o2_csrm : 1;\n+\t\tu64 o1_csrm : 1;\n+\t\tu64 o0_csrm : 1;\n+\t\tu64 reserved_20_23 : 4;\n+\t\tu64 iptr_o3 : 1;\n+\t\tu64 iptr_o2 : 1;\n+\t\tu64 iptr_o1 : 1;\n+\t\tu64 iptr_o0 : 1;\n+\t\tu64 esr_sl3 : 2;\n+\t\tu64 nsr_sl3 : 1;\n+\t\tu64 ror_sl3 : 1;\n+\t\tu64 esr_sl2 : 2;\n+\t\tu64 nsr_sl2 : 1;\n+\t\tu64 ror_sl2 : 1;\n+\t\tu64 esr_sl1 : 2;\n+\t\tu64 nsr_sl1 : 1;\n+\t\tu64 ror_sl1 : 1;\n+\t\tu64 esr_sl0 : 2;\n+\t\tu64 nsr_sl0 : 1;\n+\t\tu64 ror_sl0 : 1;\n+\t} s;\n+\tstruct cvmx_npi_output_control_cn30xx {\n+\t\tu64 reserved_45_63 : 19;\n+\t\tu64 p0_bmode : 1;\n+\t\tu64 reserved_32_43 : 12;\n+\t\tu64 o0_es : 2;\n+\t\tu64 o0_ns : 1;\n+\t\tu64 o0_ro : 1;\n+\t\tu64 reserved_25_27 : 3;\n+\t\tu64 o0_csrm : 1;\n+\t\tu64 reserved_17_23 : 7;\n+\t\tu64 iptr_o0 : 1;\n+\t\tu64 reserved_4_15 : 12;\n+\t\tu64 esr_sl0 : 2;\n+\t\tu64 nsr_sl0 : 1;\n+\t\tu64 ror_sl0 : 1;\n+\t} cn30xx;\n+\tstruct cvmx_npi_output_control_cn31xx {\n+\t\tu64 reserved_46_63 : 18;\n+\t\tu64 p1_bmode : 1;\n+\t\tu64 p0_bmode : 1;\n+\t\tu64 reserved_36_43 : 8;\n+\t\tu64 o1_es : 2;\n+\t\tu64 o1_ns : 1;\n+\t\tu64 o1_ro : 1;\n+\t\tu64 o0_es : 2;\n+\t\tu64 o0_ns : 1;\n+\t\tu64 o0_ro : 1;\n+\t\tu64 reserved_26_27 : 2;\n+\t\tu64 o1_csrm : 1;\n+\t\tu64 o0_csrm : 1;\n+\t\tu64 reserved_18_23 : 6;\n+\t\tu64 iptr_o1 : 1;\n+\t\tu64 iptr_o0 : 1;\n+\t\tu64 reserved_8_15 : 8;\n+\t\tu64 esr_sl1 : 2;\n+\t\tu64 nsr_sl1 : 1;\n+\t\tu64 ror_sl1 : 1;\n+\t\tu64 esr_sl0 : 2;\n+\t\tu64 nsr_sl0 : 1;\n+\t\tu64 ror_sl0 : 1;\n+\t} cn31xx;\n+\tstruct cvmx_npi_output_control_s cn38xx;\n+\tstruct cvmx_npi_output_control_cn38xxp2 {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 p3_bmode : 1;\n+\t\tu64 p2_bmode : 1;\n+\t\tu64 p1_bmode : 1;\n+\t\tu64 p0_bmode : 1;\n+\t\tu64 o3_es : 2;\n+\t\tu64 o3_ns : 1;\n+\t\tu64 o3_ro : 1;\n+\t\tu64 o2_es : 2;\n+\t\tu64 o2_ns : 1;\n+\t\tu64 o2_ro : 1;\n+\t\tu64 o1_es : 2;\n+\t\tu64 o1_ns : 1;\n+\t\tu64 o1_ro : 1;\n+\t\tu64 o0_es : 2;\n+\t\tu64 o0_ns : 1;\n+\t\tu64 o0_ro : 1;\n+\t\tu64 o3_csrm : 1;\n+\t\tu64 o2_csrm : 1;\n+\t\tu64 o1_csrm : 1;\n+\t\tu64 o0_csrm : 1;\n+\t\tu64 reserved_20_23 : 4;\n+\t\tu64 iptr_o3 : 1;\n+\t\tu64 iptr_o2 : 1;\n+\t\tu64 iptr_o1 : 1;\n+\t\tu64 iptr_o0 : 1;\n+\t\tu64 esr_sl3 : 2;\n+\t\tu64 nsr_sl3 : 1;\n+\t\tu64 ror_sl3 : 1;\n+\t\tu64 esr_sl2 : 2;\n+\t\tu64 nsr_sl2 : 1;\n+\t\tu64 ror_sl2 : 1;\n+\t\tu64 esr_sl1 : 2;\n+\t\tu64 nsr_sl1 : 1;\n+\t\tu64 ror_sl1 : 1;\n+\t\tu64 esr_sl0 : 2;\n+\t\tu64 nsr_sl0 : 1;\n+\t\tu64 ror_sl0 : 1;\n+\t} cn38xxp2;\n+\tstruct cvmx_npi_output_control_cn50xx {\n+\t\tu64 reserved_49_63 : 15;\n+\t\tu64 pkt_rr : 1;\n+\t\tu64 reserved_46_47 : 2;\n+\t\tu64 p1_bmode : 1;\n+\t\tu64 p0_bmode : 1;\n+\t\tu64 reserved_36_43 : 8;\n+\t\tu64 o1_es : 2;\n+\t\tu64 o1_ns : 1;\n+\t\tu64 o1_ro : 1;\n+\t\tu64 o0_es : 2;\n+\t\tu64 o0_ns : 1;\n+\t\tu64 o0_ro : 1;\n+\t\tu64 reserved_26_27 : 2;\n+\t\tu64 o1_csrm : 1;\n+\t\tu64 o0_csrm : 1;\n+\t\tu64 reserved_18_23 : 6;\n+\t\tu64 iptr_o1 : 1;\n+\t\tu64 iptr_o0 : 1;\n+\t\tu64 reserved_8_15 : 8;\n+\t\tu64 esr_sl1 : 2;\n+\t\tu64 nsr_sl1 : 1;\n+\t\tu64 ror_sl1 : 1;\n+\t\tu64 esr_sl0 : 2;\n+\t\tu64 nsr_sl0 : 1;\n+\t\tu64 ror_sl0 : 1;\n+\t} cn50xx;\n+\tstruct cvmx_npi_output_control_s cn58xx;\n+\tstruct cvmx_npi_output_control_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_output_control cvmx_npi_output_control_t;\n+\n+/**\n+ * cvmx_npi_p#_dbpair_addr\n+ *\n+ * NPI_P0_DBPAIR_ADDR = NPI's Port-0 DATA-BUFFER Pair Next Read Address.\n+ *\n+ * Contains the next address to read for Port's-0 Data/Buffer Pair.\n+ */\n+union cvmx_npi_px_dbpair_addr {\n+\tu64 u64;\n+\tstruct cvmx_npi_px_dbpair_addr_s {\n+\t\tu64 reserved_63_63 : 1;\n+\t\tu64 state : 2;\n+\t\tu64 naddr : 61;\n+\t} s;\n+\tstruct cvmx_npi_px_dbpair_addr_s cn30xx;\n+\tstruct cvmx_npi_px_dbpair_addr_s cn31xx;\n+\tstruct cvmx_npi_px_dbpair_addr_s cn38xx;\n+\tstruct cvmx_npi_px_dbpair_addr_s cn38xxp2;\n+\tstruct cvmx_npi_px_dbpair_addr_s cn50xx;\n+\tstruct cvmx_npi_px_dbpair_addr_s cn58xx;\n+\tstruct cvmx_npi_px_dbpair_addr_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_px_dbpair_addr cvmx_npi_px_dbpair_addr_t;\n+\n+/**\n+ * cvmx_npi_p#_instr_addr\n+ *\n+ * NPI_P0_INSTR_ADDR = NPI's Port-0 Instruction Next Read Address.\n+ *\n+ * Contains the next address to read for Port's-0 Instructions.\n+ */\n+union cvmx_npi_px_instr_addr {\n+\tu64 u64;\n+\tstruct cvmx_npi_px_instr_addr_s {\n+\t\tu64 state : 3;\n+\t\tu64 naddr : 61;\n+\t} s;\n+\tstruct cvmx_npi_px_instr_addr_s cn30xx;\n+\tstruct cvmx_npi_px_instr_addr_s cn31xx;\n+\tstruct cvmx_npi_px_instr_addr_s cn38xx;\n+\tstruct cvmx_npi_px_instr_addr_s cn38xxp2;\n+\tstruct cvmx_npi_px_instr_addr_s cn50xx;\n+\tstruct cvmx_npi_px_instr_addr_s cn58xx;\n+\tstruct cvmx_npi_px_instr_addr_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_px_instr_addr cvmx_npi_px_instr_addr_t;\n+\n+/**\n+ * cvmx_npi_p#_instr_cnts\n+ *\n+ * NPI_P0_INSTR_CNTS = NPI's Port-0 Instruction Counts For Packets In.\n+ *\n+ * Used to determine the number of instruction in the NPI and to be fetched for Input-Packets.\n+ */\n+union cvmx_npi_px_instr_cnts {\n+\tu64 u64;\n+\tstruct cvmx_npi_px_instr_cnts_s {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 fcnt : 6;\n+\t\tu64 avail : 32;\n+\t} s;\n+\tstruct cvmx_npi_px_instr_cnts_s cn30xx;\n+\tstruct cvmx_npi_px_instr_cnts_s cn31xx;\n+\tstruct cvmx_npi_px_instr_cnts_s cn38xx;\n+\tstruct cvmx_npi_px_instr_cnts_s cn38xxp2;\n+\tstruct cvmx_npi_px_instr_cnts_s cn50xx;\n+\tstruct cvmx_npi_px_instr_cnts_s cn58xx;\n+\tstruct cvmx_npi_px_instr_cnts_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_px_instr_cnts cvmx_npi_px_instr_cnts_t;\n+\n+/**\n+ * cvmx_npi_p#_pair_cnts\n+ *\n+ * NPI_P0_PAIR_CNTS = NPI's Port-0 Instruction Counts For Packets Out.\n+ *\n+ * Used to determine the number of instruction in the NPI and to be fetched for Output-Packets.\n+ */\n+union cvmx_npi_px_pair_cnts {\n+\tu64 u64;\n+\tstruct cvmx_npi_px_pair_cnts_s {\n+\t\tu64 reserved_37_63 : 27;\n+\t\tu64 fcnt : 5;\n+\t\tu64 avail : 32;\n+\t} s;\n+\tstruct cvmx_npi_px_pair_cnts_s cn30xx;\n+\tstruct cvmx_npi_px_pair_cnts_s cn31xx;\n+\tstruct cvmx_npi_px_pair_cnts_s cn38xx;\n+\tstruct cvmx_npi_px_pair_cnts_s cn38xxp2;\n+\tstruct cvmx_npi_px_pair_cnts_s cn50xx;\n+\tstruct cvmx_npi_px_pair_cnts_s cn58xx;\n+\tstruct cvmx_npi_px_pair_cnts_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_px_pair_cnts cvmx_npi_px_pair_cnts_t;\n+\n+/**\n+ * cvmx_npi_pci_burst_size\n+ *\n+ * NPI_PCI_BURST_SIZE = NPI PCI Burst Size Register\n+ *\n+ * Control the number of words the NPI will attempt to read / write to/from the PCI.\n+ */\n+union cvmx_npi_pci_burst_size {\n+\tu64 u64;\n+\tstruct cvmx_npi_pci_burst_size_s {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 wr_brst : 7;\n+\t\tu64 rd_brst : 7;\n+\t} s;\n+\tstruct cvmx_npi_pci_burst_size_s cn30xx;\n+\tstruct cvmx_npi_pci_burst_size_s cn31xx;\n+\tstruct cvmx_npi_pci_burst_size_s cn38xx;\n+\tstruct cvmx_npi_pci_burst_size_s cn38xxp2;\n+\tstruct cvmx_npi_pci_burst_size_s cn50xx;\n+\tstruct cvmx_npi_pci_burst_size_s cn58xx;\n+\tstruct cvmx_npi_pci_burst_size_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_pci_burst_size cvmx_npi_pci_burst_size_t;\n+\n+/**\n+ * cvmx_npi_pci_int_arb_cfg\n+ *\n+ * NPI_PCI_INT_ARB_CFG = Configuration For PCI Arbiter\n+ *\n+ * Controls operation of the Internal PCI Arbiter. This register should\n+ * only be written when PRST# is asserted. NPI_PCI_INT_ARB_CFG[EN] should\n+ * only be set when Octane is a host.\n+ */\n+union cvmx_npi_pci_int_arb_cfg {\n+\tu64 u64;\n+\tstruct cvmx_npi_pci_int_arb_cfg_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 hostmode : 1;\n+\t\tu64 pci_ovr : 4;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 en : 1;\n+\t\tu64 park_mod : 1;\n+\t\tu64 park_dev : 3;\n+\t} s;\n+\tstruct cvmx_npi_pci_int_arb_cfg_cn30xx {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 en : 1;\n+\t\tu64 park_mod : 1;\n+\t\tu64 park_dev : 3;\n+\t} cn30xx;\n+\tstruct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;\n+\tstruct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;\n+\tstruct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;\n+\tstruct cvmx_npi_pci_int_arb_cfg_s cn50xx;\n+\tstruct cvmx_npi_pci_int_arb_cfg_s cn58xx;\n+\tstruct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_pci_int_arb_cfg cvmx_npi_pci_int_arb_cfg_t;\n+\n+/**\n+ * cvmx_npi_pci_read_cmd\n+ *\n+ * NPI_PCI_READ_CMD = NPI PCI Read Command Register\n+ *\n+ * Controls the type of read command sent.\n+ * Writes to this register are not ordered with writes/reads to the PCI Memory space.\n+ * To ensure that a write has completed the user must read the register before\n+ * making an access(i.e. PCI memory space) that requires the value of this register to be updated.\n+ * Also any previously issued reads/writes to PCI memory space, still stored in the outbound\n+ * FIFO will use the value of this register after it has been updated.\n+ */\n+union cvmx_npi_pci_read_cmd {\n+\tu64 u64;\n+\tstruct cvmx_npi_pci_read_cmd_s {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 cmd_size : 11;\n+\t} s;\n+\tstruct cvmx_npi_pci_read_cmd_s cn30xx;\n+\tstruct cvmx_npi_pci_read_cmd_s cn31xx;\n+\tstruct cvmx_npi_pci_read_cmd_s cn38xx;\n+\tstruct cvmx_npi_pci_read_cmd_s cn38xxp2;\n+\tstruct cvmx_npi_pci_read_cmd_s cn50xx;\n+\tstruct cvmx_npi_pci_read_cmd_s cn58xx;\n+\tstruct cvmx_npi_pci_read_cmd_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_pci_read_cmd cvmx_npi_pci_read_cmd_t;\n+\n+/**\n+ * cvmx_npi_port32_instr_hdr\n+ *\n+ * NPI_PORT32_INSTR_HDR = NPI Port 32 Instruction Header\n+ *\n+ * Contains bits [62:42] of the Instruction Header for port 32.\n+ */\n+union cvmx_npi_port32_instr_hdr {\n+\tu64 u64;\n+\tstruct cvmx_npi_port32_instr_hdr_s {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 pbp : 1;\n+\t\tu64 rsv_f : 5;\n+\t\tu64 rparmode : 2;\n+\t\tu64 rsv_e : 1;\n+\t\tu64 rskp_len : 7;\n+\t\tu64 rsv_d : 6;\n+\t\tu64 use_ihdr : 1;\n+\t\tu64 rsv_c : 5;\n+\t\tu64 par_mode : 2;\n+\t\tu64 rsv_b : 1;\n+\t\tu64 skp_len : 7;\n+\t\tu64 rsv_a : 6;\n+\t} s;\n+\tstruct cvmx_npi_port32_instr_hdr_s cn30xx;\n+\tstruct cvmx_npi_port32_instr_hdr_s cn31xx;\n+\tstruct cvmx_npi_port32_instr_hdr_s cn38xx;\n+\tstruct cvmx_npi_port32_instr_hdr_s cn38xxp2;\n+\tstruct cvmx_npi_port32_instr_hdr_s cn50xx;\n+\tstruct cvmx_npi_port32_instr_hdr_s cn58xx;\n+\tstruct cvmx_npi_port32_instr_hdr_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_port32_instr_hdr cvmx_npi_port32_instr_hdr_t;\n+\n+/**\n+ * cvmx_npi_port33_instr_hdr\n+ *\n+ * NPI_PORT33_INSTR_HDR = NPI Port 33 Instruction Header\n+ *\n+ * Contains bits [62:42] of the Instruction Header for port 33.\n+ */\n+union cvmx_npi_port33_instr_hdr {\n+\tu64 u64;\n+\tstruct cvmx_npi_port33_instr_hdr_s {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 pbp : 1;\n+\t\tu64 rsv_f : 5;\n+\t\tu64 rparmode : 2;\n+\t\tu64 rsv_e : 1;\n+\t\tu64 rskp_len : 7;\n+\t\tu64 rsv_d : 6;\n+\t\tu64 use_ihdr : 1;\n+\t\tu64 rsv_c : 5;\n+\t\tu64 par_mode : 2;\n+\t\tu64 rsv_b : 1;\n+\t\tu64 skp_len : 7;\n+\t\tu64 rsv_a : 6;\n+\t} s;\n+\tstruct cvmx_npi_port33_instr_hdr_s cn31xx;\n+\tstruct cvmx_npi_port33_instr_hdr_s cn38xx;\n+\tstruct cvmx_npi_port33_instr_hdr_s cn38xxp2;\n+\tstruct cvmx_npi_port33_instr_hdr_s cn50xx;\n+\tstruct cvmx_npi_port33_instr_hdr_s cn58xx;\n+\tstruct cvmx_npi_port33_instr_hdr_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_port33_instr_hdr cvmx_npi_port33_instr_hdr_t;\n+\n+/**\n+ * cvmx_npi_port34_instr_hdr\n+ *\n+ * NPI_PORT34_INSTR_HDR = NPI Port 34 Instruction Header\n+ *\n+ * Contains bits [62:42] of the Instruction Header for port 34. Added for PASS-2.\n+ */\n+union cvmx_npi_port34_instr_hdr {\n+\tu64 u64;\n+\tstruct cvmx_npi_port34_instr_hdr_s {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 pbp : 1;\n+\t\tu64 rsv_f : 5;\n+\t\tu64 rparmode : 2;\n+\t\tu64 rsv_e : 1;\n+\t\tu64 rskp_len : 7;\n+\t\tu64 rsv_d : 6;\n+\t\tu64 use_ihdr : 1;\n+\t\tu64 rsv_c : 5;\n+\t\tu64 par_mode : 2;\n+\t\tu64 rsv_b : 1;\n+\t\tu64 skp_len : 7;\n+\t\tu64 rsv_a : 6;\n+\t} s;\n+\tstruct cvmx_npi_port34_instr_hdr_s cn38xx;\n+\tstruct cvmx_npi_port34_instr_hdr_s cn38xxp2;\n+\tstruct cvmx_npi_port34_instr_hdr_s cn58xx;\n+\tstruct cvmx_npi_port34_instr_hdr_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_port34_instr_hdr cvmx_npi_port34_instr_hdr_t;\n+\n+/**\n+ * cvmx_npi_port35_instr_hdr\n+ *\n+ * NPI_PORT35_INSTR_HDR = NPI Port 35 Instruction Header\n+ *\n+ * Contains bits [62:42] of the Instruction Header for port 35. Added for PASS-2.\n+ */\n+union cvmx_npi_port35_instr_hdr {\n+\tu64 u64;\n+\tstruct cvmx_npi_port35_instr_hdr_s {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 pbp : 1;\n+\t\tu64 rsv_f : 5;\n+\t\tu64 rparmode : 2;\n+\t\tu64 rsv_e : 1;\n+\t\tu64 rskp_len : 7;\n+\t\tu64 rsv_d : 6;\n+\t\tu64 use_ihdr : 1;\n+\t\tu64 rsv_c : 5;\n+\t\tu64 par_mode : 2;\n+\t\tu64 rsv_b : 1;\n+\t\tu64 skp_len : 7;\n+\t\tu64 rsv_a : 6;\n+\t} s;\n+\tstruct cvmx_npi_port35_instr_hdr_s cn38xx;\n+\tstruct cvmx_npi_port35_instr_hdr_s cn38xxp2;\n+\tstruct cvmx_npi_port35_instr_hdr_s cn58xx;\n+\tstruct cvmx_npi_port35_instr_hdr_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_port35_instr_hdr cvmx_npi_port35_instr_hdr_t;\n+\n+/**\n+ * cvmx_npi_port_bp_control\n+ *\n+ * NPI_PORT_BP_CONTROL = Port Backpressure Control\n+ *\n+ * Enables Port Level Backpressure\n+ */\n+union cvmx_npi_port_bp_control {\n+\tu64 u64;\n+\tstruct cvmx_npi_port_bp_control_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 bp_on : 4;\n+\t\tu64 enb : 4;\n+\t} s;\n+\tstruct cvmx_npi_port_bp_control_s cn30xx;\n+\tstruct cvmx_npi_port_bp_control_s cn31xx;\n+\tstruct cvmx_npi_port_bp_control_s cn38xx;\n+\tstruct cvmx_npi_port_bp_control_s cn38xxp2;\n+\tstruct cvmx_npi_port_bp_control_s cn50xx;\n+\tstruct cvmx_npi_port_bp_control_s cn58xx;\n+\tstruct cvmx_npi_port_bp_control_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_port_bp_control cvmx_npi_port_bp_control_t;\n+\n+/**\n+ * cvmx_npi_rsl_int_blocks\n+ *\n+ * RSL_INT_BLOCKS = RSL Interrupt Blocks Register\n+ *\n+ * Reading this register will return a vector with a bit set '1' for a corresponding RSL block\n+ * that presently has an interrupt pending. The Field Description below supplies the name of the\n+ * register that software should read to find out why that intterupt bit is set.\n+ */\n+union cvmx_npi_rsl_int_blocks {\n+\tu64 u64;\n+\tstruct cvmx_npi_rsl_int_blocks_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 rint_31 : 1;\n+\t\tu64 iob : 1;\n+\t\tu64 reserved_28_29 : 2;\n+\t\tu64 rint_27 : 1;\n+\t\tu64 rint_26 : 1;\n+\t\tu64 rint_25 : 1;\n+\t\tu64 rint_24 : 1;\n+\t\tu64 asx1 : 1;\n+\t\tu64 asx0 : 1;\n+\t\tu64 rint_21 : 1;\n+\t\tu64 pip : 1;\n+\t\tu64 spx1 : 1;\n+\t\tu64 spx0 : 1;\n+\t\tu64 lmc : 1;\n+\t\tu64 l2c : 1;\n+\t\tu64 rint_15 : 1;\n+\t\tu64 reserved_13_14 : 2;\n+\t\tu64 pow : 1;\n+\t\tu64 tim : 1;\n+\t\tu64 pko : 1;\n+\t\tu64 ipd : 1;\n+\t\tu64 rint_8 : 1;\n+\t\tu64 zip : 1;\n+\t\tu64 dfa : 1;\n+\t\tu64 fpa : 1;\n+\t\tu64 key : 1;\n+\t\tu64 npi : 1;\n+\t\tu64 gmx1 : 1;\n+\t\tu64 gmx0 : 1;\n+\t\tu64 mio : 1;\n+\t} s;\n+\tstruct cvmx_npi_rsl_int_blocks_cn30xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 rint_31 : 1;\n+\t\tu64 iob : 1;\n+\t\tu64 rint_29 : 1;\n+\t\tu64 rint_28 : 1;\n+\t\tu64 rint_27 : 1;\n+\t\tu64 rint_26 : 1;\n+\t\tu64 rint_25 : 1;\n+\t\tu64 rint_24 : 1;\n+\t\tu64 asx1 : 1;\n+\t\tu64 asx0 : 1;\n+\t\tu64 rint_21 : 1;\n+\t\tu64 pip : 1;\n+\t\tu64 spx1 : 1;\n+\t\tu64 spx0 : 1;\n+\t\tu64 lmc : 1;\n+\t\tu64 l2c : 1;\n+\t\tu64 rint_15 : 1;\n+\t\tu64 rint_14 : 1;\n+\t\tu64 usb : 1;\n+\t\tu64 pow : 1;\n+\t\tu64 tim : 1;\n+\t\tu64 pko : 1;\n+\t\tu64 ipd : 1;\n+\t\tu64 rint_8 : 1;\n+\t\tu64 zip : 1;\n+\t\tu64 dfa : 1;\n+\t\tu64 fpa : 1;\n+\t\tu64 key : 1;\n+\t\tu64 npi : 1;\n+\t\tu64 gmx1 : 1;\n+\t\tu64 gmx0 : 1;\n+\t\tu64 mio : 1;\n+\t} cn30xx;\n+\tstruct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;\n+\tstruct cvmx_npi_rsl_int_blocks_cn38xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 rint_31 : 1;\n+\t\tu64 iob : 1;\n+\t\tu64 rint_29 : 1;\n+\t\tu64 rint_28 : 1;\n+\t\tu64 rint_27 : 1;\n+\t\tu64 rint_26 : 1;\n+\t\tu64 rint_25 : 1;\n+\t\tu64 rint_24 : 1;\n+\t\tu64 asx1 : 1;\n+\t\tu64 asx0 : 1;\n+\t\tu64 rint_21 : 1;\n+\t\tu64 pip : 1;\n+\t\tu64 spx1 : 1;\n+\t\tu64 spx0 : 1;\n+\t\tu64 lmc : 1;\n+\t\tu64 l2c : 1;\n+\t\tu64 rint_15 : 1;\n+\t\tu64 rint_14 : 1;\n+\t\tu64 rint_13 : 1;\n+\t\tu64 pow : 1;\n+\t\tu64 tim : 1;\n+\t\tu64 pko : 1;\n+\t\tu64 ipd : 1;\n+\t\tu64 rint_8 : 1;\n+\t\tu64 zip : 1;\n+\t\tu64 dfa : 1;\n+\t\tu64 fpa : 1;\n+\t\tu64 key : 1;\n+\t\tu64 npi : 1;\n+\t\tu64 gmx1 : 1;\n+\t\tu64 gmx0 : 1;\n+\t\tu64 mio : 1;\n+\t} cn38xx;\n+\tstruct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;\n+\tstruct cvmx_npi_rsl_int_blocks_cn50xx {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 iob : 1;\n+\t\tu64 lmc1 : 1;\n+\t\tu64 agl : 1;\n+\t\tu64 reserved_24_27 : 4;\n+\t\tu64 asx1 : 1;\n+\t\tu64 asx0 : 1;\n+\t\tu64 reserved_21_21 : 1;\n+\t\tu64 pip : 1;\n+\t\tu64 spx1 : 1;\n+\t\tu64 spx0 : 1;\n+\t\tu64 lmc : 1;\n+\t\tu64 l2c : 1;\n+\t\tu64 reserved_15_15 : 1;\n+\t\tu64 rad : 1;\n+\t\tu64 usb : 1;\n+\t\tu64 pow : 1;\n+\t\tu64 tim : 1;\n+\t\tu64 pko : 1;\n+\t\tu64 ipd : 1;\n+\t\tu64 reserved_8_8 : 1;\n+\t\tu64 zip : 1;\n+\t\tu64 dfa : 1;\n+\t\tu64 fpa : 1;\n+\t\tu64 key : 1;\n+\t\tu64 npi : 1;\n+\t\tu64 gmx1 : 1;\n+\t\tu64 gmx0 : 1;\n+\t\tu64 mio : 1;\n+\t} cn50xx;\n+\tstruct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;\n+\tstruct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_rsl_int_blocks cvmx_npi_rsl_int_blocks_t;\n+\n+/**\n+ * cvmx_npi_size_input#\n+ *\n+ * NPI_SIZE_INPUT0 = NPI's Size for Input 0 Register\n+ *\n+ * The size (in instructions) of Instruction Queue-0.\n+ */\n+union cvmx_npi_size_inputx {\n+\tu64 u64;\n+\tstruct cvmx_npi_size_inputx_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 size : 32;\n+\t} s;\n+\tstruct cvmx_npi_size_inputx_s cn30xx;\n+\tstruct cvmx_npi_size_inputx_s cn31xx;\n+\tstruct cvmx_npi_size_inputx_s cn38xx;\n+\tstruct cvmx_npi_size_inputx_s cn38xxp2;\n+\tstruct cvmx_npi_size_inputx_s cn50xx;\n+\tstruct cvmx_npi_size_inputx_s cn58xx;\n+\tstruct cvmx_npi_size_inputx_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_size_inputx cvmx_npi_size_inputx_t;\n+\n+/**\n+ * cvmx_npi_win_read_to\n+ *\n+ * NPI_WIN_READ_TO = NPI WINDOW READ Timeout Register\n+ *\n+ * Number of core clocks to wait before timing out on a WINDOW-READ to the NCB.\n+ */\n+union cvmx_npi_win_read_to {\n+\tu64 u64;\n+\tstruct cvmx_npi_win_read_to_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 time : 32;\n+\t} s;\n+\tstruct cvmx_npi_win_read_to_s cn30xx;\n+\tstruct cvmx_npi_win_read_to_s cn31xx;\n+\tstruct cvmx_npi_win_read_to_s cn38xx;\n+\tstruct cvmx_npi_win_read_to_s cn38xxp2;\n+\tstruct cvmx_npi_win_read_to_s cn50xx;\n+\tstruct cvmx_npi_win_read_to_s cn58xx;\n+\tstruct cvmx_npi_win_read_to_s cn58xxp1;\n+};\n+\n+typedef union cvmx_npi_win_read_to cvmx_npi_win_read_to_t;\n+\n+#endif\n", "prefixes": [ "v1", "16/50" ] }