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GET /api/patches/1414990/?format=api
{ "id": 1414990, "url": "http://patchwork.ozlabs.org/api/patches/1414990/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-14-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-14-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:35", "name": "[v1,13/50] mips: octeon: Add cvmx-ipd-defs.h header file", "commit_ref": "0a48b0bd636390eaef4917ab70d3011e4869297e", "pull_url": null, "state": "accepted", "archived": false, "hash": "2bc1b133b83d1b826c053bed36016bb84a225d26", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-14-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1414990/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1414990/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=orJ6aCES;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4CswgY3Dchz9sSs\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:08:25 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 211F082786;\n\tFri, 11 Dec 2020 17:07:06 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 0675C82776; Fri, 11 Dec 2020 17:06:52 +0100 (CET)", "from mx2.mailbox.org (mx2a.mailbox.org\n [IPv6:2001:67c:2050:104:0:2:25:2])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 55B0382626\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:22 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org\n [IPv6:2001:67c:2050:105:465:1:1:0])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id F064BA0E39;\n Fri, 11 Dec 2020 17:06:21 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter01.heinlein-hosting.de (spamfilter01.heinlein-hosting.de\n [80.241.56.115]) (amavisd-new, port 10030)\n with ESMTP id cI3rXE7ol_La; Fri, 11 Dec 2020 17:06:17 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702826;\n\tbh=wl9keSqpbab4a3vF6kkW8h6I0oKAtPaAwTCjeF70Ulw=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=orJ6aCESALaCFOQfNvumNPkwABFZXgGy7KJNX1LG+gaeLrilgUIaRYz9xeoiW7Rwl\n\t Oh3Ao/0cXqZZ3JOG7P/KWPeMdkdZV178RrehRwIvEvCb6aK+yrHuEYou89o4Oc1ONv\n\t Yv03yjha7wHCabj2HCHstlcbFavaOJgmL56FT75113ttb0X6tMPO/b4V+X9+s1f7we\n\t kQh2nEI3wkwns0OwLx7gSr7sAJYRduUMgNtA7sCykiz2LXF3ZGTcZArRYhtqeXO0KZ\n\t EoqHwhD/G60ww7CekekNwg7xHtZJ4Nt+V2D8owog0rlKTNa2tiGdymce/RaMBTQRpa\n\t MWacACXUY76pA==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 13/50] mips: octeon: Add cvmx-ipd-defs.h header file", "Date": "Fri, 11 Dec 2020 17:05:35 +0100", "Message-Id": "<20201211160612.1498780-14-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-0.76 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "D55B1187E", "X-Rspamd-UID": "f493b2", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-ipd-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-ipd-defs.h | 1925 +++++++++++++++++\n 1 file changed, 1925 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-ipd-defs.h", "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-ipd-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-ipd-defs.h\nnew file mode 100644\nindex 0000000000..ad860fc7db\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-ipd-defs.h\n@@ -0,0 +1,1925 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon ipd.\n+ */\n+\n+#ifndef __CVMX_IPD_DEFS_H__\n+#define __CVMX_IPD_DEFS_H__\n+\n+#define CVMX_IPD_1ST_MBUFF_SKIP\t\t (0x00014F0000000000ull)\n+#define CVMX_IPD_1st_NEXT_PTR_BACK\t (0x00014F0000000150ull)\n+#define CVMX_IPD_2nd_NEXT_PTR_BACK\t (0x00014F0000000158ull)\n+#define CVMX_IPD_BIST_STATUS\t\t (0x00014F00000007F8ull)\n+#define CVMX_IPD_BPIDX_MBUF_TH(offset)\t (0x00014F0000002000ull + ((offset) & 63) * 8)\n+#define CVMX_IPD_BPID_BP_COUNTERX(offset) (0x00014F0000003000ull + ((offset) & 63) * 8)\n+#define CVMX_IPD_BP_PRT_RED_END\t\t (0x00014F0000000328ull)\n+#define CVMX_IPD_CLK_COUNT\t\t (0x00014F0000000338ull)\n+#define CVMX_IPD_CREDITS\t\t (0x00014F0000004410ull)\n+#define CVMX_IPD_CTL_STATUS\t\t (0x00014F0000000018ull)\n+#define CVMX_IPD_ECC_CTL\t\t (0x00014F0000004408ull)\n+#define CVMX_IPD_FREE_PTR_FIFO_CTL\t (0x00014F0000000780ull)\n+#define CVMX_IPD_FREE_PTR_VALUE\t\t (0x00014F0000000788ull)\n+#define CVMX_IPD_HOLD_PTR_FIFO_CTL\t (0x00014F0000000790ull)\n+#define CVMX_IPD_INT_ENB\t\t (0x00014F0000000160ull)\n+#define CVMX_IPD_INT_SUM\t\t (0x00014F0000000168ull)\n+#define CVMX_IPD_NEXT_PKT_PTR\t\t (0x00014F00000007A0ull)\n+#define CVMX_IPD_NEXT_WQE_PTR\t\t (0x00014F00000007A8ull)\n+#define CVMX_IPD_NOT_1ST_MBUFF_SKIP\t (0x00014F0000000008ull)\n+#define CVMX_IPD_ON_BP_DROP_PKTX(offset) (0x00014F0000004100ull)\n+#define CVMX_IPD_PACKET_MBUFF_SIZE\t (0x00014F0000000010ull)\n+#define CVMX_IPD_PKT_ERR\t\t (0x00014F00000003F0ull)\n+#define CVMX_IPD_PKT_PTR_VALID\t\t (0x00014F0000000358ull)\n+#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (0x00014F0000000028ull + ((offset) & 63) * 8)\n+#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (0x00014F0000000368ull + ((offset) & 63) * 8 - 8 * 36)\n+#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (0x00014F00000003D0ull + ((offset) & 63) * 8 - 8 * 40)\n+#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) \\\n+\t(0x00014F0000000388ull + ((offset) & 63) * 8 - 8 * 36)\n+#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) \\\n+\t(0x00014F00000003B0ull + ((offset) & 63) * 8 - 8 * 40)\n+#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) \\\n+\t(0x00014F0000000410ull + ((offset) & 63) * 8 - 8 * 44)\n+#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (0x00014F00000001B8ull + ((offset) & 63) * 8)\n+#define CVMX_IPD_PORT_PTR_FIFO_CTL\t\t(0x00014F0000000798ull)\n+#define CVMX_IPD_PORT_QOS_INTX(offset)\t\t(0x00014F0000000808ull + ((offset) & 7) * 8)\n+#define CVMX_IPD_PORT_QOS_INT_ENBX(offset)\t(0x00014F0000000848ull + ((offset) & 7) * 8)\n+#define CVMX_IPD_PORT_QOS_X_CNT(offset)\t\t(0x00014F0000000888ull + ((offset) & 511) * 8)\n+#define CVMX_IPD_PORT_SOPX(offset)\t\t(0x00014F0000004400ull)\n+#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL\t\t(0x00014F0000000348ull)\n+#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL\t\t(0x00014F0000000350ull)\n+#define CVMX_IPD_PTR_COUNT\t\t\t(0x00014F0000000320ull)\n+#define CVMX_IPD_PWP_PTR_FIFO_CTL\t\t(0x00014F0000000340ull)\n+#define CVMX_IPD_QOS0_RED_MARKS\t\t\tCVMX_IPD_QOSX_RED_MARKS(0)\n+#define CVMX_IPD_QOS1_RED_MARKS\t\t\tCVMX_IPD_QOSX_RED_MARKS(1)\n+#define CVMX_IPD_QOS2_RED_MARKS\t\t\tCVMX_IPD_QOSX_RED_MARKS(2)\n+#define CVMX_IPD_QOS3_RED_MARKS\t\t\tCVMX_IPD_QOSX_RED_MARKS(3)\n+#define CVMX_IPD_QOS4_RED_MARKS\t\t\tCVMX_IPD_QOSX_RED_MARKS(4)\n+#define CVMX_IPD_QOS5_RED_MARKS\t\t\tCVMX_IPD_QOSX_RED_MARKS(5)\n+#define CVMX_IPD_QOS6_RED_MARKS\t\t\tCVMX_IPD_QOSX_RED_MARKS(6)\n+#define CVMX_IPD_QOS7_RED_MARKS\t\t\tCVMX_IPD_QOSX_RED_MARKS(7)\n+#define CVMX_IPD_QOSX_RED_MARKS(offset)\t\t(0x00014F0000000178ull + ((offset) & 7) * 8)\n+#define CVMX_IPD_QUE0_FREE_PAGE_CNT\t\t(0x00014F0000000330ull)\n+#define CVMX_IPD_RED_BPID_ENABLEX(offset)\t(0x00014F0000004200ull)\n+#define CVMX_IPD_RED_DELAY\t\t\t(0x00014F0000004300ull)\n+#define CVMX_IPD_RED_PORT_ENABLE\t\t(0x00014F00000002D8ull)\n+#define CVMX_IPD_RED_PORT_ENABLE2\t\t(0x00014F00000003A8ull)\n+#define CVMX_IPD_RED_QUE0_PARAM\t\t\tCVMX_IPD_RED_QUEX_PARAM(0)\n+#define CVMX_IPD_RED_QUE1_PARAM\t\t\tCVMX_IPD_RED_QUEX_PARAM(1)\n+#define CVMX_IPD_RED_QUE2_PARAM\t\t\tCVMX_IPD_RED_QUEX_PARAM(2)\n+#define CVMX_IPD_RED_QUE3_PARAM\t\t\tCVMX_IPD_RED_QUEX_PARAM(3)\n+#define CVMX_IPD_RED_QUE4_PARAM\t\t\tCVMX_IPD_RED_QUEX_PARAM(4)\n+#define CVMX_IPD_RED_QUE5_PARAM\t\t\tCVMX_IPD_RED_QUEX_PARAM(5)\n+#define CVMX_IPD_RED_QUE6_PARAM\t\t\tCVMX_IPD_RED_QUEX_PARAM(6)\n+#define CVMX_IPD_RED_QUE7_PARAM\t\t\tCVMX_IPD_RED_QUEX_PARAM(7)\n+#define CVMX_IPD_RED_QUEX_PARAM(offset)\t\t(0x00014F00000002E0ull + ((offset) & 7) * 8)\n+#define CVMX_IPD_REQ_WGT\t\t\t(0x00014F0000004418ull)\n+#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT\t\t(0x00014F0000000148ull)\n+#define CVMX_IPD_SUB_PORT_FCS\t\t\t(0x00014F0000000170ull)\n+#define CVMX_IPD_SUB_PORT_QOS_CNT\t\t(0x00014F0000000800ull)\n+#define CVMX_IPD_WQE_FPA_QUEUE\t\t\t(0x00014F0000000020ull)\n+#define CVMX_IPD_WQE_PTR_VALID\t\t\t(0x00014F0000000360ull)\n+\n+/**\n+ * cvmx_ipd_1st_mbuff_skip\n+ *\n+ * The number of words that the IPD will skip when writing the first MBUFF.\n+ *\n+ */\n+union cvmx_ipd_1st_mbuff_skip {\n+\tu64 u64;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 skip_sz : 6;\n+\t} s;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn30xx;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn31xx;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn38xx;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn38xxp2;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn50xx;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn52xx;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn52xxp1;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn56xx;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn56xxp1;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn58xx;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn58xxp1;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn61xx;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn63xx;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn63xxp1;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn66xx;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn68xx;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn68xxp1;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn70xx;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cn70xxp1;\n+\tstruct cvmx_ipd_1st_mbuff_skip_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_1st_mbuff_skip_t;\n+\n+/**\n+ * cvmx_ipd_1st_next_ptr_back\n+ *\n+ * IPD_1st_NEXT_PTR_BACK = IPD First Next Pointer Back Values\n+ * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF\n+ */\n+union cvmx_ipd_1st_next_ptr_back {\n+\tu64 u64;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 back : 4;\n+\t} s;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn30xx;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn31xx;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn38xx;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn38xxp2;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn50xx;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn52xx;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn52xxp1;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn56xx;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn56xxp1;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn58xx;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn58xxp1;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn61xx;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn63xx;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn63xxp1;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn66xx;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn68xx;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn68xxp1;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn70xx;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cn70xxp1;\n+\tstruct cvmx_ipd_1st_next_ptr_back_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_1st_next_ptr_back_t;\n+\n+/**\n+ * cvmx_ipd_2nd_next_ptr_back\n+ *\n+ * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF\n+ *\n+ */\n+union cvmx_ipd_2nd_next_ptr_back {\n+\tu64 u64;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 back : 4;\n+\t} s;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn30xx;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn31xx;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn38xx;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn38xxp2;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn50xx;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn52xx;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn52xxp1;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn56xx;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn58xx;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn61xx;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn63xx;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn66xx;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn68xx;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn68xxp1;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn70xx;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cn70xxp1;\n+\tstruct cvmx_ipd_2nd_next_ptr_back_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_2nd_next_ptr_back cvmx_ipd_2nd_next_ptr_back_t;\n+\n+/**\n+ * cvmx_ipd_bist_status\n+ *\n+ * BIST Status for IPD's Memories.\n+ *\n+ */\n+union cvmx_ipd_bist_status {\n+\tu64 u64;\n+\tstruct cvmx_ipd_bist_status_s {\n+\t\tu64 reserved_23_63 : 41;\n+\t\tu64 iiwo1 : 1;\n+\t\tu64 iiwo0 : 1;\n+\t\tu64 iio1 : 1;\n+\t\tu64 iio0 : 1;\n+\t\tu64 pbm4 : 1;\n+\t\tu64 csr_mem : 1;\n+\t\tu64 csr_ncmd : 1;\n+\t\tu64 pwq_wqed : 1;\n+\t\tu64 pwq_wp1 : 1;\n+\t\tu64 pwq_pow : 1;\n+\t\tu64 ipq_pbe1 : 1;\n+\t\tu64 ipq_pbe0 : 1;\n+\t\tu64 pbm3 : 1;\n+\t\tu64 pbm2 : 1;\n+\t\tu64 pbm1 : 1;\n+\t\tu64 pbm0 : 1;\n+\t\tu64 pbm_word : 1;\n+\t\tu64 pwq1 : 1;\n+\t\tu64 pwq0 : 1;\n+\t\tu64 prc_off : 1;\n+\t\tu64 ipd_old : 1;\n+\t\tu64 ipd_new : 1;\n+\t\tu64 pwp : 1;\n+\t} s;\n+\tstruct cvmx_ipd_bist_status_cn30xx {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 pwq_wqed : 1;\n+\t\tu64 pwq_wp1 : 1;\n+\t\tu64 pwq_pow : 1;\n+\t\tu64 ipq_pbe1 : 1;\n+\t\tu64 ipq_pbe0 : 1;\n+\t\tu64 pbm3 : 1;\n+\t\tu64 pbm2 : 1;\n+\t\tu64 pbm1 : 1;\n+\t\tu64 pbm0 : 1;\n+\t\tu64 pbm_word : 1;\n+\t\tu64 pwq1 : 1;\n+\t\tu64 pwq0 : 1;\n+\t\tu64 prc_off : 1;\n+\t\tu64 ipd_old : 1;\n+\t\tu64 ipd_new : 1;\n+\t\tu64 pwp : 1;\n+\t} cn30xx;\n+\tstruct cvmx_ipd_bist_status_cn30xx cn31xx;\n+\tstruct cvmx_ipd_bist_status_cn30xx cn38xx;\n+\tstruct cvmx_ipd_bist_status_cn30xx cn38xxp2;\n+\tstruct cvmx_ipd_bist_status_cn30xx cn50xx;\n+\tstruct cvmx_ipd_bist_status_cn52xx {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 csr_mem : 1;\n+\t\tu64 csr_ncmd : 1;\n+\t\tu64 pwq_wqed : 1;\n+\t\tu64 pwq_wp1 : 1;\n+\t\tu64 pwq_pow : 1;\n+\t\tu64 ipq_pbe1 : 1;\n+\t\tu64 ipq_pbe0 : 1;\n+\t\tu64 pbm3 : 1;\n+\t\tu64 pbm2 : 1;\n+\t\tu64 pbm1 : 1;\n+\t\tu64 pbm0 : 1;\n+\t\tu64 pbm_word : 1;\n+\t\tu64 pwq1 : 1;\n+\t\tu64 pwq0 : 1;\n+\t\tu64 prc_off : 1;\n+\t\tu64 ipd_old : 1;\n+\t\tu64 ipd_new : 1;\n+\t\tu64 pwp : 1;\n+\t} cn52xx;\n+\tstruct cvmx_ipd_bist_status_cn52xx cn52xxp1;\n+\tstruct cvmx_ipd_bist_status_cn52xx cn56xx;\n+\tstruct cvmx_ipd_bist_status_cn52xx cn56xxp1;\n+\tstruct cvmx_ipd_bist_status_cn30xx cn58xx;\n+\tstruct cvmx_ipd_bist_status_cn30xx cn58xxp1;\n+\tstruct cvmx_ipd_bist_status_cn52xx cn61xx;\n+\tstruct cvmx_ipd_bist_status_cn52xx cn63xx;\n+\tstruct cvmx_ipd_bist_status_cn52xx cn63xxp1;\n+\tstruct cvmx_ipd_bist_status_cn52xx cn66xx;\n+\tstruct cvmx_ipd_bist_status_s cn68xx;\n+\tstruct cvmx_ipd_bist_status_s cn68xxp1;\n+\tstruct cvmx_ipd_bist_status_cn52xx cn70xx;\n+\tstruct cvmx_ipd_bist_status_cn52xx cn70xxp1;\n+\tstruct cvmx_ipd_bist_status_cn52xx cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_bist_status cvmx_ipd_bist_status_t;\n+\n+/**\n+ * cvmx_ipd_bp_prt_red_end\n+ *\n+ * When IPD applies backpressure to a PORT and the corresponding bit in this register is set,\n+ * the RED Unit will drop packets for that port.\n+ */\n+union cvmx_ipd_bp_prt_red_end {\n+\tu64 u64;\n+\tstruct cvmx_ipd_bp_prt_red_end_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 prt_enb : 48;\n+\t} s;\n+\tstruct cvmx_ipd_bp_prt_red_end_cn30xx {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 prt_enb : 36;\n+\t} cn30xx;\n+\tstruct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx;\n+\tstruct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;\n+\tstruct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;\n+\tstruct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;\n+\tstruct cvmx_ipd_bp_prt_red_end_cn52xx {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 prt_enb : 40;\n+\t} cn52xx;\n+\tstruct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1;\n+\tstruct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx;\n+\tstruct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1;\n+\tstruct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;\n+\tstruct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;\n+\tstruct cvmx_ipd_bp_prt_red_end_s cn61xx;\n+\tstruct cvmx_ipd_bp_prt_red_end_cn63xx {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 prt_enb : 44;\n+\t} cn63xx;\n+\tstruct cvmx_ipd_bp_prt_red_end_cn63xx cn63xxp1;\n+\tstruct cvmx_ipd_bp_prt_red_end_s cn66xx;\n+\tstruct cvmx_ipd_bp_prt_red_end_s cn70xx;\n+\tstruct cvmx_ipd_bp_prt_red_end_s cn70xxp1;\n+\tstruct cvmx_ipd_bp_prt_red_end_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_bp_prt_red_end cvmx_ipd_bp_prt_red_end_t;\n+\n+/**\n+ * cvmx_ipd_bpid#_mbuf_th\n+ *\n+ * 0x2000 2FFF\n+ *\n+ * IPD_BPIDX_MBUF_TH = IPD BPID MBUFF Threshold\n+ *\n+ * The number of MBUFFs in use by the BPID, that when exceeded, backpressure will be applied to the BPID.\n+ */\n+union cvmx_ipd_bpidx_mbuf_th {\n+\tu64 u64;\n+\tstruct cvmx_ipd_bpidx_mbuf_th_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 bp_enb : 1;\n+\t\tu64 page_cnt : 17;\n+\t} s;\n+\tstruct cvmx_ipd_bpidx_mbuf_th_s cn68xx;\n+\tstruct cvmx_ipd_bpidx_mbuf_th_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_bpidx_mbuf_th cvmx_ipd_bpidx_mbuf_th_t;\n+\n+/**\n+ * cvmx_ipd_bpid_bp_counter#\n+ *\n+ * RESERVE SPACE UPTO 0x2FFF\n+ *\n+ * 0x3000 0x3ffff\n+ *\n+ * IPD_BPID_BP_COUNTERX = MBUF BPID Counters used to generate Back Pressure Per BPID.\n+ */\n+union cvmx_ipd_bpid_bp_counterx {\n+\tu64 u64;\n+\tstruct cvmx_ipd_bpid_bp_counterx_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 cnt_val : 25;\n+\t} s;\n+\tstruct cvmx_ipd_bpid_bp_counterx_s cn68xx;\n+\tstruct cvmx_ipd_bpid_bp_counterx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_bpid_bp_counterx cvmx_ipd_bpid_bp_counterx_t;\n+\n+/**\n+ * cvmx_ipd_clk_count\n+ *\n+ * Counts the number of core clocks periods since the de-asserition of reset.\n+ *\n+ */\n+union cvmx_ipd_clk_count {\n+\tu64 u64;\n+\tstruct cvmx_ipd_clk_count_s {\n+\t\tu64 clk_cnt : 64;\n+\t} s;\n+\tstruct cvmx_ipd_clk_count_s cn30xx;\n+\tstruct cvmx_ipd_clk_count_s cn31xx;\n+\tstruct cvmx_ipd_clk_count_s cn38xx;\n+\tstruct cvmx_ipd_clk_count_s cn38xxp2;\n+\tstruct cvmx_ipd_clk_count_s cn50xx;\n+\tstruct cvmx_ipd_clk_count_s cn52xx;\n+\tstruct cvmx_ipd_clk_count_s cn52xxp1;\n+\tstruct cvmx_ipd_clk_count_s cn56xx;\n+\tstruct cvmx_ipd_clk_count_s cn56xxp1;\n+\tstruct cvmx_ipd_clk_count_s cn58xx;\n+\tstruct cvmx_ipd_clk_count_s cn58xxp1;\n+\tstruct cvmx_ipd_clk_count_s cn61xx;\n+\tstruct cvmx_ipd_clk_count_s cn63xx;\n+\tstruct cvmx_ipd_clk_count_s cn63xxp1;\n+\tstruct cvmx_ipd_clk_count_s cn66xx;\n+\tstruct cvmx_ipd_clk_count_s cn68xx;\n+\tstruct cvmx_ipd_clk_count_s cn68xxp1;\n+\tstruct cvmx_ipd_clk_count_s cn70xx;\n+\tstruct cvmx_ipd_clk_count_s cn70xxp1;\n+\tstruct cvmx_ipd_clk_count_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_clk_count cvmx_ipd_clk_count_t;\n+\n+/**\n+ * cvmx_ipd_credits\n+ *\n+ * IPD_CREDITS = IPD Credits\n+ *\n+ * The credits allowed for IPD.\n+ */\n+union cvmx_ipd_credits {\n+\tu64 u64;\n+\tstruct cvmx_ipd_credits_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 iob_wrc : 8;\n+\t\tu64 iob_wr : 8;\n+\t} s;\n+\tstruct cvmx_ipd_credits_s cn68xx;\n+\tstruct cvmx_ipd_credits_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_credits cvmx_ipd_credits_t;\n+\n+/**\n+ * cvmx_ipd_ctl_status\n+ *\n+ * The number of words in a MBUFF used for packet data store.\n+ *\n+ */\n+union cvmx_ipd_ctl_status {\n+\tu64 u64;\n+\tstruct cvmx_ipd_ctl_status_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 use_sop : 1;\n+\t\tu64 rst_done : 1;\n+\t\tu64 clken : 1;\n+\t\tu64 no_wptr : 1;\n+\t\tu64 pq_apkt : 1;\n+\t\tu64 pq_nabuf : 1;\n+\t\tu64 ipd_full : 1;\n+\t\tu64 pkt_off : 1;\n+\t\tu64 len_m8 : 1;\n+\t\tu64 reset : 1;\n+\t\tu64 addpkt : 1;\n+\t\tu64 naddbuf : 1;\n+\t\tu64 pkt_lend : 1;\n+\t\tu64 wqe_lend : 1;\n+\t\tu64 pbp_en : 1;\n+\t\tcvmx_ipd_mode_t opc_mode : 2;\n+\t\tu64 ipd_en : 1;\n+\t} s;\n+\tstruct cvmx_ipd_ctl_status_cn30xx {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 len_m8 : 1;\n+\t\tu64 reset : 1;\n+\t\tu64 addpkt : 1;\n+\t\tu64 naddbuf : 1;\n+\t\tu64 pkt_lend : 1;\n+\t\tu64 wqe_lend : 1;\n+\t\tu64 pbp_en : 1;\n+\t\tcvmx_ipd_mode_t opc_mode : 2;\n+\t\tu64 ipd_en : 1;\n+\t} cn30xx;\n+\tstruct cvmx_ipd_ctl_status_cn30xx cn31xx;\n+\tstruct cvmx_ipd_ctl_status_cn30xx cn38xx;\n+\tstruct cvmx_ipd_ctl_status_cn38xxp2 {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 reset : 1;\n+\t\tu64 addpkt : 1;\n+\t\tu64 naddbuf : 1;\n+\t\tu64 pkt_lend : 1;\n+\t\tu64 wqe_lend : 1;\n+\t\tu64 pbp_en : 1;\n+\t\tcvmx_ipd_mode_t opc_mode : 2;\n+\t\tu64 ipd_en : 1;\n+\t} cn38xxp2;\n+\tstruct cvmx_ipd_ctl_status_cn50xx {\n+\t\tu64 reserved_15_63 : 49;\n+\t\tu64 no_wptr : 1;\n+\t\tu64 pq_apkt : 1;\n+\t\tu64 pq_nabuf : 1;\n+\t\tu64 ipd_full : 1;\n+\t\tu64 pkt_off : 1;\n+\t\tu64 len_m8 : 1;\n+\t\tu64 reset : 1;\n+\t\tu64 addpkt : 1;\n+\t\tu64 naddbuf : 1;\n+\t\tu64 pkt_lend : 1;\n+\t\tu64 wqe_lend : 1;\n+\t\tu64 pbp_en : 1;\n+\t\tcvmx_ipd_mode_t opc_mode : 2;\n+\t\tu64 ipd_en : 1;\n+\t} cn50xx;\n+\tstruct cvmx_ipd_ctl_status_cn50xx cn52xx;\n+\tstruct cvmx_ipd_ctl_status_cn50xx cn52xxp1;\n+\tstruct cvmx_ipd_ctl_status_cn50xx cn56xx;\n+\tstruct cvmx_ipd_ctl_status_cn50xx cn56xxp1;\n+\tstruct cvmx_ipd_ctl_status_cn58xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 ipd_full : 1;\n+\t\tu64 pkt_off : 1;\n+\t\tu64 len_m8 : 1;\n+\t\tu64 reset : 1;\n+\t\tu64 addpkt : 1;\n+\t\tu64 naddbuf : 1;\n+\t\tu64 pkt_lend : 1;\n+\t\tu64 wqe_lend : 1;\n+\t\tu64 pbp_en : 1;\n+\t\tcvmx_ipd_mode_t opc_mode : 2;\n+\t\tu64 ipd_en : 1;\n+\t} cn58xx;\n+\tstruct cvmx_ipd_ctl_status_cn58xx cn58xxp1;\n+\tstruct cvmx_ipd_ctl_status_s cn61xx;\n+\tstruct cvmx_ipd_ctl_status_s cn63xx;\n+\tstruct cvmx_ipd_ctl_status_cn63xxp1 {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 clken : 1;\n+\t\tu64 no_wptr : 1;\n+\t\tu64 pq_apkt : 1;\n+\t\tu64 pq_nabuf : 1;\n+\t\tu64 ipd_full : 1;\n+\t\tu64 pkt_off : 1;\n+\t\tu64 len_m8 : 1;\n+\t\tu64 reset : 1;\n+\t\tu64 addpkt : 1;\n+\t\tu64 naddbuf : 1;\n+\t\tu64 pkt_lend : 1;\n+\t\tu64 wqe_lend : 1;\n+\t\tu64 pbp_en : 1;\n+\t\tcvmx_ipd_mode_t opc_mode : 2;\n+\t\tu64 ipd_en : 1;\n+\t} cn63xxp1;\n+\tstruct cvmx_ipd_ctl_status_s cn66xx;\n+\tstruct cvmx_ipd_ctl_status_s cn68xx;\n+\tstruct cvmx_ipd_ctl_status_s cn68xxp1;\n+\tstruct cvmx_ipd_ctl_status_s cn70xx;\n+\tstruct cvmx_ipd_ctl_status_s cn70xxp1;\n+\tstruct cvmx_ipd_ctl_status_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_ctl_status cvmx_ipd_ctl_status_t;\n+\n+/**\n+ * cvmx_ipd_ecc_ctl\n+ *\n+ * IPD_ECC_CTL = IPD ECC Control\n+ *\n+ * Allows inserting ECC errors for testing.\n+ */\n+union cvmx_ipd_ecc_ctl {\n+\tu64 u64;\n+\tstruct cvmx_ipd_ecc_ctl_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 pm3_syn : 2;\n+\t\tu64 pm2_syn : 2;\n+\t\tu64 pm1_syn : 2;\n+\t\tu64 pm0_syn : 2;\n+\t} s;\n+\tstruct cvmx_ipd_ecc_ctl_s cn68xx;\n+\tstruct cvmx_ipd_ecc_ctl_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_ecc_ctl cvmx_ipd_ecc_ctl_t;\n+\n+/**\n+ * cvmx_ipd_free_ptr_fifo_ctl\n+ *\n+ * IPD_FREE_PTR_FIFO_CTL = IPD's FREE Pointer FIFO Control\n+ *\n+ * Allows reading of the Page-Pointers stored in the IPD's FREE Fifo.\n+ * See also the IPD_FREE_PTR_VALUE\n+ */\n+union cvmx_ipd_free_ptr_fifo_ctl {\n+\tu64 u64;\n+\tstruct cvmx_ipd_free_ptr_fifo_ctl_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 max_cnts : 7;\n+\t\tu64 wraddr : 8;\n+\t\tu64 praddr : 8;\n+\t\tu64 cena : 1;\n+\t\tu64 raddr : 8;\n+\t} s;\n+\tstruct cvmx_ipd_free_ptr_fifo_ctl_s cn68xx;\n+\tstruct cvmx_ipd_free_ptr_fifo_ctl_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_free_ptr_fifo_ctl cvmx_ipd_free_ptr_fifo_ctl_t;\n+\n+/**\n+ * cvmx_ipd_free_ptr_value\n+ *\n+ * IPD_FREE_PTR_VALUE = IPD's FREE Pointer Value\n+ *\n+ * The value of the pointer selected through the IPD_FREE_PTR_FIFO_CTL\n+ */\n+union cvmx_ipd_free_ptr_value {\n+\tu64 u64;\n+\tstruct cvmx_ipd_free_ptr_value_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 ptr : 33;\n+\t} s;\n+\tstruct cvmx_ipd_free_ptr_value_s cn68xx;\n+\tstruct cvmx_ipd_free_ptr_value_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_free_ptr_value cvmx_ipd_free_ptr_value_t;\n+\n+/**\n+ * cvmx_ipd_hold_ptr_fifo_ctl\n+ *\n+ * IPD_HOLD_PTR_FIFO_CTL = IPD's Holding Pointer FIFO Control\n+ *\n+ * Allows reading of the Page-Pointers stored in the IPD's Holding Fifo.\n+ */\n+union cvmx_ipd_hold_ptr_fifo_ctl {\n+\tu64 u64;\n+\tstruct cvmx_ipd_hold_ptr_fifo_ctl_s {\n+\t\tu64 reserved_43_63 : 21;\n+\t\tu64 ptr : 33;\n+\t\tu64 max_pkt : 3;\n+\t\tu64 praddr : 3;\n+\t\tu64 cena : 1;\n+\t\tu64 raddr : 3;\n+\t} s;\n+\tstruct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xx;\n+\tstruct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_hold_ptr_fifo_ctl cvmx_ipd_hold_ptr_fifo_ctl_t;\n+\n+/**\n+ * cvmx_ipd_int_enb\n+ *\n+ * IPD_INTERRUPT_ENB = IPD Interrupt Enable Register\n+ * Used to enable the various interrupting conditions of IPD\n+ */\n+union cvmx_ipd_int_enb {\n+\tu64 u64;\n+\tstruct cvmx_ipd_int_enb_s {\n+\t\tu64 reserved_23_63 : 41;\n+\t\tu64 pw3_dbe : 1;\n+\t\tu64 pw3_sbe : 1;\n+\t\tu64 pw2_dbe : 1;\n+\t\tu64 pw2_sbe : 1;\n+\t\tu64 pw1_dbe : 1;\n+\t\tu64 pw1_sbe : 1;\n+\t\tu64 pw0_dbe : 1;\n+\t\tu64 pw0_sbe : 1;\n+\t\tu64 dat : 1;\n+\t\tu64 eop : 1;\n+\t\tu64 sop : 1;\n+\t\tu64 pq_sub : 1;\n+\t\tu64 pq_add : 1;\n+\t\tu64 bc_ovr : 1;\n+\t\tu64 d_coll : 1;\n+\t\tu64 c_coll : 1;\n+\t\tu64 cc_ovr : 1;\n+\t\tu64 dc_ovr : 1;\n+\t\tu64 bp_sub : 1;\n+\t\tu64 prc_par3 : 1;\n+\t\tu64 prc_par2 : 1;\n+\t\tu64 prc_par1 : 1;\n+\t\tu64 prc_par0 : 1;\n+\t} s;\n+\tstruct cvmx_ipd_int_enb_cn30xx {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 bp_sub : 1;\n+\t\tu64 prc_par3 : 1;\n+\t\tu64 prc_par2 : 1;\n+\t\tu64 prc_par1 : 1;\n+\t\tu64 prc_par0 : 1;\n+\t} cn30xx;\n+\tstruct cvmx_ipd_int_enb_cn30xx cn31xx;\n+\tstruct cvmx_ipd_int_enb_cn38xx {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 bc_ovr : 1;\n+\t\tu64 d_coll : 1;\n+\t\tu64 c_coll : 1;\n+\t\tu64 cc_ovr : 1;\n+\t\tu64 dc_ovr : 1;\n+\t\tu64 bp_sub : 1;\n+\t\tu64 prc_par3 : 1;\n+\t\tu64 prc_par2 : 1;\n+\t\tu64 prc_par1 : 1;\n+\t\tu64 prc_par0 : 1;\n+\t} cn38xx;\n+\tstruct cvmx_ipd_int_enb_cn30xx cn38xxp2;\n+\tstruct cvmx_ipd_int_enb_cn38xx cn50xx;\n+\tstruct cvmx_ipd_int_enb_cn52xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 pq_sub : 1;\n+\t\tu64 pq_add : 1;\n+\t\tu64 bc_ovr : 1;\n+\t\tu64 d_coll : 1;\n+\t\tu64 c_coll : 1;\n+\t\tu64 cc_ovr : 1;\n+\t\tu64 dc_ovr : 1;\n+\t\tu64 bp_sub : 1;\n+\t\tu64 prc_par3 : 1;\n+\t\tu64 prc_par2 : 1;\n+\t\tu64 prc_par1 : 1;\n+\t\tu64 prc_par0 : 1;\n+\t} cn52xx;\n+\tstruct cvmx_ipd_int_enb_cn52xx cn52xxp1;\n+\tstruct cvmx_ipd_int_enb_cn52xx cn56xx;\n+\tstruct cvmx_ipd_int_enb_cn52xx cn56xxp1;\n+\tstruct cvmx_ipd_int_enb_cn38xx cn58xx;\n+\tstruct cvmx_ipd_int_enb_cn38xx cn58xxp1;\n+\tstruct cvmx_ipd_int_enb_cn52xx cn61xx;\n+\tstruct cvmx_ipd_int_enb_cn52xx cn63xx;\n+\tstruct cvmx_ipd_int_enb_cn52xx cn63xxp1;\n+\tstruct cvmx_ipd_int_enb_cn52xx cn66xx;\n+\tstruct cvmx_ipd_int_enb_s cn68xx;\n+\tstruct cvmx_ipd_int_enb_s cn68xxp1;\n+\tstruct cvmx_ipd_int_enb_cn52xx cn70xx;\n+\tstruct cvmx_ipd_int_enb_cn52xx cn70xxp1;\n+\tstruct cvmx_ipd_int_enb_cn52xx cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_int_enb cvmx_ipd_int_enb_t;\n+\n+/**\n+ * cvmx_ipd_int_sum\n+ *\n+ * IPD_INTERRUPT_SUM = IPD Interrupt Summary Register\n+ * Set when an interrupt condition occurs, write '1' to clear.\n+ */\n+union cvmx_ipd_int_sum {\n+\tu64 u64;\n+\tstruct cvmx_ipd_int_sum_s {\n+\t\tu64 reserved_23_63 : 41;\n+\t\tu64 pw3_dbe : 1;\n+\t\tu64 pw3_sbe : 1;\n+\t\tu64 pw2_dbe : 1;\n+\t\tu64 pw2_sbe : 1;\n+\t\tu64 pw1_dbe : 1;\n+\t\tu64 pw1_sbe : 1;\n+\t\tu64 pw0_dbe : 1;\n+\t\tu64 pw0_sbe : 1;\n+\t\tu64 dat : 1;\n+\t\tu64 eop : 1;\n+\t\tu64 sop : 1;\n+\t\tu64 pq_sub : 1;\n+\t\tu64 pq_add : 1;\n+\t\tu64 bc_ovr : 1;\n+\t\tu64 d_coll : 1;\n+\t\tu64 c_coll : 1;\n+\t\tu64 cc_ovr : 1;\n+\t\tu64 dc_ovr : 1;\n+\t\tu64 bp_sub : 1;\n+\t\tu64 prc_par3 : 1;\n+\t\tu64 prc_par2 : 1;\n+\t\tu64 prc_par1 : 1;\n+\t\tu64 prc_par0 : 1;\n+\t} s;\n+\tstruct cvmx_ipd_int_sum_cn30xx {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 bp_sub : 1;\n+\t\tu64 prc_par3 : 1;\n+\t\tu64 prc_par2 : 1;\n+\t\tu64 prc_par1 : 1;\n+\t\tu64 prc_par0 : 1;\n+\t} cn30xx;\n+\tstruct cvmx_ipd_int_sum_cn30xx cn31xx;\n+\tstruct cvmx_ipd_int_sum_cn38xx {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 bc_ovr : 1;\n+\t\tu64 d_coll : 1;\n+\t\tu64 c_coll : 1;\n+\t\tu64 cc_ovr : 1;\n+\t\tu64 dc_ovr : 1;\n+\t\tu64 bp_sub : 1;\n+\t\tu64 prc_par3 : 1;\n+\t\tu64 prc_par2 : 1;\n+\t\tu64 prc_par1 : 1;\n+\t\tu64 prc_par0 : 1;\n+\t} cn38xx;\n+\tstruct cvmx_ipd_int_sum_cn30xx cn38xxp2;\n+\tstruct cvmx_ipd_int_sum_cn38xx cn50xx;\n+\tstruct cvmx_ipd_int_sum_cn52xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 pq_sub : 1;\n+\t\tu64 pq_add : 1;\n+\t\tu64 bc_ovr : 1;\n+\t\tu64 d_coll : 1;\n+\t\tu64 c_coll : 1;\n+\t\tu64 cc_ovr : 1;\n+\t\tu64 dc_ovr : 1;\n+\t\tu64 bp_sub : 1;\n+\t\tu64 prc_par3 : 1;\n+\t\tu64 prc_par2 : 1;\n+\t\tu64 prc_par1 : 1;\n+\t\tu64 prc_par0 : 1;\n+\t} cn52xx;\n+\tstruct cvmx_ipd_int_sum_cn52xx cn52xxp1;\n+\tstruct cvmx_ipd_int_sum_cn52xx cn56xx;\n+\tstruct cvmx_ipd_int_sum_cn52xx cn56xxp1;\n+\tstruct cvmx_ipd_int_sum_cn38xx cn58xx;\n+\tstruct cvmx_ipd_int_sum_cn38xx cn58xxp1;\n+\tstruct cvmx_ipd_int_sum_cn52xx cn61xx;\n+\tstruct cvmx_ipd_int_sum_cn52xx cn63xx;\n+\tstruct cvmx_ipd_int_sum_cn52xx cn63xxp1;\n+\tstruct cvmx_ipd_int_sum_cn52xx cn66xx;\n+\tstruct cvmx_ipd_int_sum_s cn68xx;\n+\tstruct cvmx_ipd_int_sum_s cn68xxp1;\n+\tstruct cvmx_ipd_int_sum_cn52xx cn70xx;\n+\tstruct cvmx_ipd_int_sum_cn52xx cn70xxp1;\n+\tstruct cvmx_ipd_int_sum_cn52xx cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_int_sum cvmx_ipd_int_sum_t;\n+\n+/**\n+ * cvmx_ipd_next_pkt_ptr\n+ *\n+ * IPD_NEXT_PKT_PTR = IPD's Next Packet Pointer\n+ *\n+ * The value of the packet-pointer fetched and in the valid register.\n+ */\n+union cvmx_ipd_next_pkt_ptr {\n+\tu64 u64;\n+\tstruct cvmx_ipd_next_pkt_ptr_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 ptr : 33;\n+\t} s;\n+\tstruct cvmx_ipd_next_pkt_ptr_s cn68xx;\n+\tstruct cvmx_ipd_next_pkt_ptr_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_next_pkt_ptr cvmx_ipd_next_pkt_ptr_t;\n+\n+/**\n+ * cvmx_ipd_next_wqe_ptr\n+ *\n+ * IPD_NEXT_WQE_PTR = IPD's NEXT_WQE Pointer\n+ *\n+ * The value of the WQE-pointer fetched and in the valid register.\n+ */\n+union cvmx_ipd_next_wqe_ptr {\n+\tu64 u64;\n+\tstruct cvmx_ipd_next_wqe_ptr_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 ptr : 33;\n+\t} s;\n+\tstruct cvmx_ipd_next_wqe_ptr_s cn68xx;\n+\tstruct cvmx_ipd_next_wqe_ptr_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_next_wqe_ptr cvmx_ipd_next_wqe_ptr_t;\n+\n+/**\n+ * cvmx_ipd_not_1st_mbuff_skip\n+ *\n+ * The number of words that the IPD will skip when writing any MBUFF that is not the first.\n+ *\n+ */\n+union cvmx_ipd_not_1st_mbuff_skip {\n+\tu64 u64;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 skip_sz : 6;\n+\t} s;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn30xx;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn31xx;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn38xx;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn38xxp2;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn50xx;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn52xx;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn52xxp1;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn56xx;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn61xx;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn63xx;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn66xx;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn68xx;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn68xxp1;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn70xx;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cn70xxp1;\n+\tstruct cvmx_ipd_not_1st_mbuff_skip_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_not_1st_mbuff_skip cvmx_ipd_not_1st_mbuff_skip_t;\n+\n+/**\n+ * cvmx_ipd_on_bp_drop_pkt#\n+ *\n+ * RESERVE SPACE UPTO 0x3FFF\n+ *\n+ *\n+ * RESERVED FOR FORMER IPD_SUB_PKIND_FCS - MOVED TO PIP\n+ *\n+ * RESERVE 4008 - 40FF\n+ *\n+ *\n+ * IPD_ON_BP_DROP_PKT = IPD On Backpressure Drop Packet\n+ *\n+ * When IPD applies backpressure to a BPID and the corresponding bit in this register is set,\n+ * then previously received packets will be dropped when processed.\n+ */\n+union cvmx_ipd_on_bp_drop_pktx {\n+\tu64 u64;\n+\tstruct cvmx_ipd_on_bp_drop_pktx_s {\n+\t\tu64 prt_enb : 64;\n+\t} s;\n+\tstruct cvmx_ipd_on_bp_drop_pktx_s cn68xx;\n+\tstruct cvmx_ipd_on_bp_drop_pktx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_on_bp_drop_pktx cvmx_ipd_on_bp_drop_pktx_t;\n+\n+/**\n+ * cvmx_ipd_packet_mbuff_size\n+ *\n+ * The number of words in a MBUFF used for packet data store.\n+ *\n+ */\n+union cvmx_ipd_packet_mbuff_size {\n+\tu64 u64;\n+\tstruct cvmx_ipd_packet_mbuff_size_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 mb_size : 12;\n+\t} s;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn30xx;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn31xx;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn38xx;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn38xxp2;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn50xx;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn52xx;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn52xxp1;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn56xx;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn56xxp1;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn58xx;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn58xxp1;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn61xx;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn63xx;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn63xxp1;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn66xx;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn68xx;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn68xxp1;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn70xx;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cn70xxp1;\n+\tstruct cvmx_ipd_packet_mbuff_size_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_packet_mbuff_size cvmx_ipd_packet_mbuff_size_t;\n+\n+/**\n+ * cvmx_ipd_pkt_err\n+ *\n+ * IPD_PKT_ERR = IPD Packet Error Register\n+ *\n+ * Provides status about the failing packet recevie error.\n+ */\n+union cvmx_ipd_pkt_err {\n+\tu64 u64;\n+\tstruct cvmx_ipd_pkt_err_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 reasm : 6;\n+\t} s;\n+\tstruct cvmx_ipd_pkt_err_s cn68xx;\n+\tstruct cvmx_ipd_pkt_err_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_pkt_err cvmx_ipd_pkt_err_t;\n+\n+/**\n+ * cvmx_ipd_pkt_ptr_valid\n+ *\n+ * The value of the packet-pointer fetched and in the valid register.\n+ *\n+ */\n+union cvmx_ipd_pkt_ptr_valid {\n+\tu64 u64;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 ptr : 29;\n+\t} s;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn30xx;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn31xx;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn38xx;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn50xx;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn52xx;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn52xxp1;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn56xx;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn56xxp1;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn58xx;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn58xxp1;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn61xx;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn63xx;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn63xxp1;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn66xx;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn70xx;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cn70xxp1;\n+\tstruct cvmx_ipd_pkt_ptr_valid_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_pkt_ptr_valid cvmx_ipd_pkt_ptr_valid_t;\n+\n+/**\n+ * cvmx_ipd_port#_bp_page_cnt\n+ *\n+ * IPD_PORTX_BP_PAGE_CNT = IPD Port Backpressure Page Count\n+ * The number of pages in use by the port that when exceeded, backpressure will be applied to the\n+ * port.\n+ * See also IPD_PORTX_BP_PAGE_CNT2\n+ * See also IPD_PORTX_BP_PAGE_CNT3\n+ */\n+union cvmx_ipd_portx_bp_page_cnt {\n+\tu64 u64;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 bp_enb : 1;\n+\t\tu64 page_cnt : 17;\n+\t} s;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn30xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn31xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn38xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn38xxp2;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn50xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn52xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn52xxp1;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn56xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn58xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn61xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn63xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn66xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn70xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cn70xxp1;\n+\tstruct cvmx_ipd_portx_bp_page_cnt_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_portx_bp_page_cnt cvmx_ipd_portx_bp_page_cnt_t;\n+\n+/**\n+ * cvmx_ipd_port#_bp_page_cnt2\n+ *\n+ * IPD_PORTX_BP_PAGE_CNT2 = IPD Port Backpressure Page Count\n+ * The number of pages in use by the port that when exceeded, backpressure will be applied to the\n+ * port.\n+ * See also IPD_PORTX_BP_PAGE_CNT\n+ * See also IPD_PORTX_BP_PAGE_CNT3\n+ * 0x368-0x380\n+ */\n+union cvmx_ipd_portx_bp_page_cnt2 {\n+\tu64 u64;\n+\tstruct cvmx_ipd_portx_bp_page_cnt2_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 bp_enb : 1;\n+\t\tu64 page_cnt : 17;\n+\t} s;\n+\tstruct cvmx_ipd_portx_bp_page_cnt2_s cn52xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;\n+\tstruct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;\n+\tstruct cvmx_ipd_portx_bp_page_cnt2_s cn61xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt2_s cn63xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1;\n+\tstruct cvmx_ipd_portx_bp_page_cnt2_s cn66xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt2_s cn70xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt2_s cn70xxp1;\n+\tstruct cvmx_ipd_portx_bp_page_cnt2_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_portx_bp_page_cnt2 cvmx_ipd_portx_bp_page_cnt2_t;\n+\n+/**\n+ * cvmx_ipd_port#_bp_page_cnt3\n+ *\n+ * IPD_PORTX_BP_PAGE_CNT3 = IPD Port Backpressure Page Count\n+ * The number of pages in use by the port that when exceeded, backpressure will be applied to the\n+ * port.\n+ * See also IPD_PORTX_BP_PAGE_CNT\n+ * See also IPD_PORTX_BP_PAGE_CNT2\n+ * 0x3d0-408\n+ */\n+union cvmx_ipd_portx_bp_page_cnt3 {\n+\tu64 u64;\n+\tstruct cvmx_ipd_portx_bp_page_cnt3_s {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 bp_enb : 1;\n+\t\tu64 page_cnt : 17;\n+\t} s;\n+\tstruct cvmx_ipd_portx_bp_page_cnt3_s cn61xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt3_s cn63xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1;\n+\tstruct cvmx_ipd_portx_bp_page_cnt3_s cn66xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt3_s cn70xx;\n+\tstruct cvmx_ipd_portx_bp_page_cnt3_s cn70xxp1;\n+\tstruct cvmx_ipd_portx_bp_page_cnt3_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_portx_bp_page_cnt3 cvmx_ipd_portx_bp_page_cnt3_t;\n+\n+/**\n+ * cvmx_ipd_port_bp_counters2_pair#\n+ *\n+ * See also IPD_PORT_BP_COUNTERS_PAIRX\n+ * See also IPD_PORT_BP_COUNTERS3_PAIRX\n+ * 0x388-0x3a0\n+ */\n+union cvmx_ipd_port_bp_counters2_pairx {\n+\tu64 u64;\n+\tstruct cvmx_ipd_port_bp_counters2_pairx_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 cnt_val : 25;\n+\t} s;\n+\tstruct cvmx_ipd_port_bp_counters2_pairx_s cn52xx;\n+\tstruct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;\n+\tstruct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;\n+\tstruct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;\n+\tstruct cvmx_ipd_port_bp_counters2_pairx_s cn61xx;\n+\tstruct cvmx_ipd_port_bp_counters2_pairx_s cn63xx;\n+\tstruct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1;\n+\tstruct cvmx_ipd_port_bp_counters2_pairx_s cn66xx;\n+\tstruct cvmx_ipd_port_bp_counters2_pairx_s cn70xx;\n+\tstruct cvmx_ipd_port_bp_counters2_pairx_s cn70xxp1;\n+\tstruct cvmx_ipd_port_bp_counters2_pairx_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_port_bp_counters2_pairx cvmx_ipd_port_bp_counters2_pairx_t;\n+\n+/**\n+ * cvmx_ipd_port_bp_counters3_pair#\n+ *\n+ * See also IPD_PORT_BP_COUNTERS_PAIRX\n+ * See also IPD_PORT_BP_COUNTERS2_PAIRX\n+ * 0x3b0-0x3c8\n+ */\n+union cvmx_ipd_port_bp_counters3_pairx {\n+\tu64 u64;\n+\tstruct cvmx_ipd_port_bp_counters3_pairx_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 cnt_val : 25;\n+\t} s;\n+\tstruct cvmx_ipd_port_bp_counters3_pairx_s cn61xx;\n+\tstruct cvmx_ipd_port_bp_counters3_pairx_s cn63xx;\n+\tstruct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1;\n+\tstruct cvmx_ipd_port_bp_counters3_pairx_s cn66xx;\n+\tstruct cvmx_ipd_port_bp_counters3_pairx_s cn70xx;\n+\tstruct cvmx_ipd_port_bp_counters3_pairx_s cn70xxp1;\n+\tstruct cvmx_ipd_port_bp_counters3_pairx_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_port_bp_counters3_pairx cvmx_ipd_port_bp_counters3_pairx_t;\n+\n+/**\n+ * cvmx_ipd_port_bp_counters4_pair#\n+ *\n+ * See also IPD_PORT_BP_COUNTERS_PAIRX\n+ * See also IPD_PORT_BP_COUNTERS2_PAIRX\n+ * 0x410-0x3c8\n+ */\n+union cvmx_ipd_port_bp_counters4_pairx {\n+\tu64 u64;\n+\tstruct cvmx_ipd_port_bp_counters4_pairx_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 cnt_val : 25;\n+\t} s;\n+\tstruct cvmx_ipd_port_bp_counters4_pairx_s cn61xx;\n+\tstruct cvmx_ipd_port_bp_counters4_pairx_s cn66xx;\n+\tstruct cvmx_ipd_port_bp_counters4_pairx_s cn70xx;\n+\tstruct cvmx_ipd_port_bp_counters4_pairx_s cn70xxp1;\n+\tstruct cvmx_ipd_port_bp_counters4_pairx_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_port_bp_counters4_pairx cvmx_ipd_port_bp_counters4_pairx_t;\n+\n+/**\n+ * cvmx_ipd_port_bp_counters_pair#\n+ *\n+ * See also IPD_PORT_BP_COUNTERS2_PAIRX\n+ * See also IPD_PORT_BP_COUNTERS3_PAIRX\n+ * 0x1b8-0x2d0\n+ */\n+union cvmx_ipd_port_bp_counters_pairx {\n+\tu64 u64;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 cnt_val : 25;\n+\t} s;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn30xx;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn31xx;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn38xx;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn50xx;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn52xx;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn56xx;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn58xx;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn61xx;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn63xx;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn66xx;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn70xx;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cn70xxp1;\n+\tstruct cvmx_ipd_port_bp_counters_pairx_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_port_bp_counters_pairx cvmx_ipd_port_bp_counters_pairx_t;\n+\n+/**\n+ * cvmx_ipd_port_ptr_fifo_ctl\n+ *\n+ * IPD_PORT_PTR_FIFO_CTL = IPD's Reasm-Id Pointer FIFO Control\n+ *\n+ * Allows reading of the Page-Pointers stored in the IPD's Reasm-Id Fifo.\n+ */\n+union cvmx_ipd_port_ptr_fifo_ctl {\n+\tu64 u64;\n+\tstruct cvmx_ipd_port_ptr_fifo_ctl_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 ptr : 33;\n+\t\tu64 max_pkt : 7;\n+\t\tu64 cena : 1;\n+\t\tu64 raddr : 7;\n+\t} s;\n+\tstruct cvmx_ipd_port_ptr_fifo_ctl_s cn68xx;\n+\tstruct cvmx_ipd_port_ptr_fifo_ctl_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_port_ptr_fifo_ctl cvmx_ipd_port_ptr_fifo_ctl_t;\n+\n+/**\n+ * cvmx_ipd_port_qos_#_cnt\n+ *\n+ * IPD_PORT_QOS_X_CNT = IPD PortX QOS-0 Count\n+ * A counter per port/qos. Counter are originzed in sequence where the first 8 counter (0-7)\n+ * belong to Port-0\n+ * QOS 0-7 respectively followed by port 1 at (8-15), etc\n+ * Ports 0-3, 32-43\n+ */\n+union cvmx_ipd_port_qos_x_cnt {\n+\tu64 u64;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s {\n+\t\tu64 wmark : 32;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s cn52xx;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s cn52xxp1;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s cn56xx;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s cn56xxp1;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s cn61xx;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s cn63xx;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s cn63xxp1;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s cn66xx;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s cn68xx;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s cn68xxp1;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s cn70xx;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s cn70xxp1;\n+\tstruct cvmx_ipd_port_qos_x_cnt_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_port_qos_x_cnt cvmx_ipd_port_qos_x_cnt_t;\n+\n+/**\n+ * cvmx_ipd_port_qos_int#\n+ *\n+ * See the description for IPD_PORT_QOS_X_CNT\n+ * 0=P0-7; 1=P8-15; 2=P16-23; 3=P24-31; 4=P32-39; 5=P40-47; 6=P48-55; 7=P56-63\n+ * Only ports used are: P0-3, p16-19, P24, P32-39. Therefore only IPD_PORT_QOS_INT0 ([63:32] ==\n+ * Reserved), IPD_PORT_QOS_INT2 ([63:32] == Reserved), IPD_PORT_QOS_INT3 ([63:8] == Reserved),\n+ * IPD_PORT_QOS_INT4\n+ */\n+union cvmx_ipd_port_qos_intx {\n+\tu64 u64;\n+\tstruct cvmx_ipd_port_qos_intx_s {\n+\t\tu64 intr : 64;\n+\t} s;\n+\tstruct cvmx_ipd_port_qos_intx_s cn52xx;\n+\tstruct cvmx_ipd_port_qos_intx_s cn52xxp1;\n+\tstruct cvmx_ipd_port_qos_intx_s cn56xx;\n+\tstruct cvmx_ipd_port_qos_intx_s cn56xxp1;\n+\tstruct cvmx_ipd_port_qos_intx_s cn61xx;\n+\tstruct cvmx_ipd_port_qos_intx_s cn63xx;\n+\tstruct cvmx_ipd_port_qos_intx_s cn63xxp1;\n+\tstruct cvmx_ipd_port_qos_intx_s cn66xx;\n+\tstruct cvmx_ipd_port_qos_intx_s cn68xx;\n+\tstruct cvmx_ipd_port_qos_intx_s cn68xxp1;\n+\tstruct cvmx_ipd_port_qos_intx_s cn70xx;\n+\tstruct cvmx_ipd_port_qos_intx_s cn70xxp1;\n+\tstruct cvmx_ipd_port_qos_intx_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_port_qos_intx cvmx_ipd_port_qos_intx_t;\n+\n+/**\n+ * cvmx_ipd_port_qos_int_enb#\n+ *\n+ * \"When the IPD_PORT_QOS_INTX[\\#] is '1' and IPD_PORT_QOS_INT_ENBX[\\#] is '1' a interrupt will be\n+ * generated.\"\n+ */\n+union cvmx_ipd_port_qos_int_enbx {\n+\tu64 u64;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s {\n+\t\tu64 enb : 64;\n+\t} s;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s cn52xx;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s cn52xxp1;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s cn56xx;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s cn56xxp1;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s cn61xx;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s cn63xx;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s cn63xxp1;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s cn66xx;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s cn68xx;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s cn68xxp1;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s cn70xx;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s cn70xxp1;\n+\tstruct cvmx_ipd_port_qos_int_enbx_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_port_qos_int_enbx cvmx_ipd_port_qos_int_enbx_t;\n+\n+/**\n+ * cvmx_ipd_port_sop#\n+ *\n+ * IPD_PORT_SOP = IPD Reasm-Id SOP\n+ *\n+ * Set when a SOP is detected on a reasm-num. Where the reasm-num value set the bit vector of this register.\n+ */\n+union cvmx_ipd_port_sopx {\n+\tu64 u64;\n+\tstruct cvmx_ipd_port_sopx_s {\n+\t\tu64 sop : 64;\n+\t} s;\n+\tstruct cvmx_ipd_port_sopx_s cn68xx;\n+\tstruct cvmx_ipd_port_sopx_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_port_sopx cvmx_ipd_port_sopx_t;\n+\n+/**\n+ * cvmx_ipd_prc_hold_ptr_fifo_ctl\n+ *\n+ * Allows reading of the Page-Pointers stored in the IPD's PRC Holding Fifo.\n+ *\n+ */\n+union cvmx_ipd_prc_hold_ptr_fifo_ctl {\n+\tu64 u64;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s {\n+\t\tu64 reserved_39_63 : 25;\n+\t\tu64 max_pkt : 3;\n+\t\tu64 praddr : 3;\n+\t\tu64 ptr : 29;\n+\t\tu64 cena : 1;\n+\t\tu64 raddr : 3;\n+\t} s;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn61xx;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn66xx;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn70xx;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn70xxp1;\n+\tstruct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_prc_hold_ptr_fifo_ctl cvmx_ipd_prc_hold_ptr_fifo_ctl_t;\n+\n+/**\n+ * cvmx_ipd_prc_port_ptr_fifo_ctl\n+ *\n+ * Allows reading of the Page-Pointers stored in the IPD's PRC PORT Fifo.\n+ *\n+ */\n+union cvmx_ipd_prc_port_ptr_fifo_ctl {\n+\tu64 u64;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 max_pkt : 7;\n+\t\tu64 ptr : 29;\n+\t\tu64 cena : 1;\n+\t\tu64 raddr : 7;\n+\t} s;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn61xx;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn66xx;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn70xx;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn70xxp1;\n+\tstruct cvmx_ipd_prc_port_ptr_fifo_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_prc_port_ptr_fifo_ctl cvmx_ipd_prc_port_ptr_fifo_ctl_t;\n+\n+/**\n+ * cvmx_ipd_ptr_count\n+ *\n+ * Shows the number of WQE and Packet Page Pointers stored in the IPD.\n+ *\n+ */\n+union cvmx_ipd_ptr_count {\n+\tu64 u64;\n+\tstruct cvmx_ipd_ptr_count_s {\n+\t\tu64 reserved_19_63 : 45;\n+\t\tu64 pktv_cnt : 1;\n+\t\tu64 wqev_cnt : 1;\n+\t\tu64 pfif_cnt : 3;\n+\t\tu64 pkt_pcnt : 7;\n+\t\tu64 wqe_pcnt : 7;\n+\t} s;\n+\tstruct cvmx_ipd_ptr_count_s cn30xx;\n+\tstruct cvmx_ipd_ptr_count_s cn31xx;\n+\tstruct cvmx_ipd_ptr_count_s cn38xx;\n+\tstruct cvmx_ipd_ptr_count_s cn38xxp2;\n+\tstruct cvmx_ipd_ptr_count_s cn50xx;\n+\tstruct cvmx_ipd_ptr_count_s cn52xx;\n+\tstruct cvmx_ipd_ptr_count_s cn52xxp1;\n+\tstruct cvmx_ipd_ptr_count_s cn56xx;\n+\tstruct cvmx_ipd_ptr_count_s cn56xxp1;\n+\tstruct cvmx_ipd_ptr_count_s cn58xx;\n+\tstruct cvmx_ipd_ptr_count_s cn58xxp1;\n+\tstruct cvmx_ipd_ptr_count_s cn61xx;\n+\tstruct cvmx_ipd_ptr_count_s cn63xx;\n+\tstruct cvmx_ipd_ptr_count_s cn63xxp1;\n+\tstruct cvmx_ipd_ptr_count_s cn66xx;\n+\tstruct cvmx_ipd_ptr_count_s cn68xx;\n+\tstruct cvmx_ipd_ptr_count_s cn68xxp1;\n+\tstruct cvmx_ipd_ptr_count_s cn70xx;\n+\tstruct cvmx_ipd_ptr_count_s cn70xxp1;\n+\tstruct cvmx_ipd_ptr_count_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_ptr_count cvmx_ipd_ptr_count_t;\n+\n+/**\n+ * cvmx_ipd_pwp_ptr_fifo_ctl\n+ *\n+ * Allows reading of the Page-Pointers stored in the IPD's PWP Fifo.\n+ *\n+ */\n+union cvmx_ipd_pwp_ptr_fifo_ctl {\n+\tu64 u64;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s {\n+\t\tu64 reserved_61_63 : 3;\n+\t\tu64 max_cnts : 7;\n+\t\tu64 wraddr : 8;\n+\t\tu64 praddr : 8;\n+\t\tu64 ptr : 29;\n+\t\tu64 cena : 1;\n+\t\tu64 raddr : 8;\n+\t} s;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn38xx;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn50xx;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xx;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xxp1;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xx;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn61xx;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn66xx;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn70xx;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cn70xxp1;\n+\tstruct cvmx_ipd_pwp_ptr_fifo_ctl_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_pwp_ptr_fifo_ctl cvmx_ipd_pwp_ptr_fifo_ctl_t;\n+\n+/**\n+ * cvmx_ipd_qos#_red_marks\n+ *\n+ * Set the pass-drop marks for qos level.\n+ *\n+ */\n+union cvmx_ipd_qosx_red_marks {\n+\tu64 u64;\n+\tstruct cvmx_ipd_qosx_red_marks_s {\n+\t\tu64 drop : 32;\n+\t\tu64 pass : 32;\n+\t} s;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn30xx;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn31xx;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn38xx;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn38xxp2;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn50xx;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn52xx;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn52xxp1;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn56xx;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn56xxp1;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn58xx;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn58xxp1;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn61xx;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn63xx;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn63xxp1;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn66xx;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn68xx;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn68xxp1;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn70xx;\n+\tstruct cvmx_ipd_qosx_red_marks_s cn70xxp1;\n+\tstruct cvmx_ipd_qosx_red_marks_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_qosx_red_marks cvmx_ipd_qosx_red_marks_t;\n+\n+/**\n+ * cvmx_ipd_que0_free_page_cnt\n+ *\n+ * Number of Free-Page Pointer that are available for use in the FPA for Queue-0.\n+ *\n+ */\n+union cvmx_ipd_que0_free_page_cnt {\n+\tu64 u64;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 q0_pcnt : 32;\n+\t} s;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn30xx;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn31xx;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn38xx;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn38xxp2;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn50xx;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn52xx;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn52xxp1;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn56xx;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn58xx;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn61xx;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn63xx;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn63xxp1;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn66xx;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn68xx;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn68xxp1;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn70xx;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cn70xxp1;\n+\tstruct cvmx_ipd_que0_free_page_cnt_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_que0_free_page_cnt cvmx_ipd_que0_free_page_cnt_t;\n+\n+/**\n+ * cvmx_ipd_red_bpid_enable#\n+ *\n+ * IPD_RED_BPID_ENABLE = IPD RED BPID Enable\n+ *\n+ * Set the pass-drop marks for qos level.\n+ */\n+union cvmx_ipd_red_bpid_enablex {\n+\tu64 u64;\n+\tstruct cvmx_ipd_red_bpid_enablex_s {\n+\t\tu64 prt_enb : 64;\n+\t} s;\n+\tstruct cvmx_ipd_red_bpid_enablex_s cn68xx;\n+\tstruct cvmx_ipd_red_bpid_enablex_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_red_bpid_enablex cvmx_ipd_red_bpid_enablex_t;\n+\n+/**\n+ * cvmx_ipd_red_delay\n+ *\n+ * IPD_RED_DELAY = IPD RED BPID Enable\n+ *\n+ * Set the pass-drop marks for qos level.\n+ */\n+union cvmx_ipd_red_delay {\n+\tu64 u64;\n+\tstruct cvmx_ipd_red_delay_s {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 prb_dly : 14;\n+\t\tu64 avg_dly : 14;\n+\t} s;\n+\tstruct cvmx_ipd_red_delay_s cn68xx;\n+\tstruct cvmx_ipd_red_delay_s cn68xxp1;\n+};\n+\n+typedef union cvmx_ipd_red_delay cvmx_ipd_red_delay_t;\n+\n+/**\n+ * cvmx_ipd_red_port_enable\n+ *\n+ * Set the pass-drop marks for qos level.\n+ *\n+ */\n+union cvmx_ipd_red_port_enable {\n+\tu64 u64;\n+\tstruct cvmx_ipd_red_port_enable_s {\n+\t\tu64 prb_dly : 14;\n+\t\tu64 avg_dly : 14;\n+\t\tu64 prt_enb : 36;\n+\t} s;\n+\tstruct cvmx_ipd_red_port_enable_s cn30xx;\n+\tstruct cvmx_ipd_red_port_enable_s cn31xx;\n+\tstruct cvmx_ipd_red_port_enable_s cn38xx;\n+\tstruct cvmx_ipd_red_port_enable_s cn38xxp2;\n+\tstruct cvmx_ipd_red_port_enable_s cn50xx;\n+\tstruct cvmx_ipd_red_port_enable_s cn52xx;\n+\tstruct cvmx_ipd_red_port_enable_s cn52xxp1;\n+\tstruct cvmx_ipd_red_port_enable_s cn56xx;\n+\tstruct cvmx_ipd_red_port_enable_s cn56xxp1;\n+\tstruct cvmx_ipd_red_port_enable_s cn58xx;\n+\tstruct cvmx_ipd_red_port_enable_s cn58xxp1;\n+\tstruct cvmx_ipd_red_port_enable_s cn61xx;\n+\tstruct cvmx_ipd_red_port_enable_s cn63xx;\n+\tstruct cvmx_ipd_red_port_enable_s cn63xxp1;\n+\tstruct cvmx_ipd_red_port_enable_s cn66xx;\n+\tstruct cvmx_ipd_red_port_enable_s cn70xx;\n+\tstruct cvmx_ipd_red_port_enable_s cn70xxp1;\n+\tstruct cvmx_ipd_red_port_enable_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_red_port_enable cvmx_ipd_red_port_enable_t;\n+\n+/**\n+ * cvmx_ipd_red_port_enable2\n+ *\n+ * Set the pass-drop marks for qos level.\n+ *\n+ */\n+union cvmx_ipd_red_port_enable2 {\n+\tu64 u64;\n+\tstruct cvmx_ipd_red_port_enable2_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 prt_enb : 12;\n+\t} s;\n+\tstruct cvmx_ipd_red_port_enable2_cn52xx {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 prt_enb : 4;\n+\t} cn52xx;\n+\tstruct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1;\n+\tstruct cvmx_ipd_red_port_enable2_cn52xx cn56xx;\n+\tstruct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1;\n+\tstruct cvmx_ipd_red_port_enable2_s cn61xx;\n+\tstruct cvmx_ipd_red_port_enable2_cn63xx {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 prt_enb : 8;\n+\t} cn63xx;\n+\tstruct cvmx_ipd_red_port_enable2_cn63xx cn63xxp1;\n+\tstruct cvmx_ipd_red_port_enable2_s cn66xx;\n+\tstruct cvmx_ipd_red_port_enable2_s cn70xx;\n+\tstruct cvmx_ipd_red_port_enable2_s cn70xxp1;\n+\tstruct cvmx_ipd_red_port_enable2_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_red_port_enable2 cvmx_ipd_red_port_enable2_t;\n+\n+/**\n+ * cvmx_ipd_red_que#_param\n+ *\n+ * Value control the Passing and Dropping of packets by the red engine for QOS Level-0.\n+ *\n+ */\n+union cvmx_ipd_red_quex_param {\n+\tu64 u64;\n+\tstruct cvmx_ipd_red_quex_param_s {\n+\t\tu64 reserved_49_63 : 15;\n+\t\tu64 use_pcnt : 1;\n+\t\tu64 new_con : 8;\n+\t\tu64 avg_con : 8;\n+\t\tu64 prb_con : 32;\n+\t} s;\n+\tstruct cvmx_ipd_red_quex_param_s cn30xx;\n+\tstruct cvmx_ipd_red_quex_param_s cn31xx;\n+\tstruct cvmx_ipd_red_quex_param_s cn38xx;\n+\tstruct cvmx_ipd_red_quex_param_s cn38xxp2;\n+\tstruct cvmx_ipd_red_quex_param_s cn50xx;\n+\tstruct cvmx_ipd_red_quex_param_s cn52xx;\n+\tstruct cvmx_ipd_red_quex_param_s cn52xxp1;\n+\tstruct cvmx_ipd_red_quex_param_s cn56xx;\n+\tstruct cvmx_ipd_red_quex_param_s cn56xxp1;\n+\tstruct cvmx_ipd_red_quex_param_s cn58xx;\n+\tstruct cvmx_ipd_red_quex_param_s cn58xxp1;\n+\tstruct cvmx_ipd_red_quex_param_s cn61xx;\n+\tstruct cvmx_ipd_red_quex_param_s cn63xx;\n+\tstruct cvmx_ipd_red_quex_param_s cn63xxp1;\n+\tstruct cvmx_ipd_red_quex_param_s cn66xx;\n+\tstruct cvmx_ipd_red_quex_param_s cn68xx;\n+\tstruct cvmx_ipd_red_quex_param_s cn68xxp1;\n+\tstruct cvmx_ipd_red_quex_param_s cn70xx;\n+\tstruct cvmx_ipd_red_quex_param_s cn70xxp1;\n+\tstruct cvmx_ipd_red_quex_param_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_red_quex_param cvmx_ipd_red_quex_param_t;\n+\n+/**\n+ * cvmx_ipd_req_wgt\n+ *\n+ * IPD_REQ_WGT = IPD REQ weights\n+ *\n+ * There are 8 devices that can request to send packet traffic to the IPD. These weights are used for the Weighted Round Robin\n+ * grant generated by the IPD to requestors.\n+ */\n+union cvmx_ipd_req_wgt {\n+\tu64 u64;\n+\tstruct cvmx_ipd_req_wgt_s {\n+\t\tu64 wgt7 : 8;\n+\t\tu64 wgt6 : 8;\n+\t\tu64 wgt5 : 8;\n+\t\tu64 wgt4 : 8;\n+\t\tu64 wgt3 : 8;\n+\t\tu64 wgt2 : 8;\n+\t\tu64 wgt1 : 8;\n+\t\tu64 wgt0 : 8;\n+\t} s;\n+\tstruct cvmx_ipd_req_wgt_s cn68xx;\n+};\n+\n+typedef union cvmx_ipd_req_wgt cvmx_ipd_req_wgt_t;\n+\n+/**\n+ * cvmx_ipd_sub_port_bp_page_cnt\n+ *\n+ * Will add the value to the indicated port count register, the number of pages supplied. The\n+ * value added should\n+ * be the 2's complement of the value that needs to be subtracted. Users add 2's complement\n+ * values to the\n+ * port-mbuf-count register to return (lower the count) mbufs to the counter in order to avoid\n+ * port-level\n+ * backpressure being applied to the port. Backpressure is applied when the MBUF used count of a\n+ * port exceeds the\n+ * value in the IPD_PORTX_BP_PAGE_CNT, IPD_PORTX_BP_PAGE_CNT2, and IPD_PORTX_BP_PAGE_CNT3.\n+ * This register can't be written from the PCI via a window write.\n+ */\n+union cvmx_ipd_sub_port_bp_page_cnt {\n+\tu64 u64;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s {\n+\t\tu64 reserved_31_63 : 33;\n+\t\tu64 port : 6;\n+\t\tu64 page_cnt : 25;\n+\t} s;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn61xx;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn66xx;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn68xx;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn68xxp1;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn70xx;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cn70xxp1;\n+\tstruct cvmx_ipd_sub_port_bp_page_cnt_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_sub_port_bp_page_cnt cvmx_ipd_sub_port_bp_page_cnt_t;\n+\n+/**\n+ * cvmx_ipd_sub_port_fcs\n+ *\n+ * When set '1' the port corresponding to the bit set will subtract 4 bytes from the end of\n+ * the packet.\n+ */\n+union cvmx_ipd_sub_port_fcs {\n+\tu64 u64;\n+\tstruct cvmx_ipd_sub_port_fcs_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 port_bit2 : 4;\n+\t\tu64 reserved_32_35 : 4;\n+\t\tu64 port_bit : 32;\n+\t} s;\n+\tstruct cvmx_ipd_sub_port_fcs_cn30xx {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 port_bit : 3;\n+\t} cn30xx;\n+\tstruct cvmx_ipd_sub_port_fcs_cn30xx cn31xx;\n+\tstruct cvmx_ipd_sub_port_fcs_cn38xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 port_bit : 32;\n+\t} cn38xx;\n+\tstruct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2;\n+\tstruct cvmx_ipd_sub_port_fcs_cn30xx cn50xx;\n+\tstruct cvmx_ipd_sub_port_fcs_s cn52xx;\n+\tstruct cvmx_ipd_sub_port_fcs_s cn52xxp1;\n+\tstruct cvmx_ipd_sub_port_fcs_s cn56xx;\n+\tstruct cvmx_ipd_sub_port_fcs_s cn56xxp1;\n+\tstruct cvmx_ipd_sub_port_fcs_cn38xx cn58xx;\n+\tstruct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1;\n+\tstruct cvmx_ipd_sub_port_fcs_s cn61xx;\n+\tstruct cvmx_ipd_sub_port_fcs_s cn63xx;\n+\tstruct cvmx_ipd_sub_port_fcs_s cn63xxp1;\n+\tstruct cvmx_ipd_sub_port_fcs_s cn66xx;\n+\tstruct cvmx_ipd_sub_port_fcs_s cn70xx;\n+\tstruct cvmx_ipd_sub_port_fcs_s cn70xxp1;\n+\tstruct cvmx_ipd_sub_port_fcs_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_sub_port_fcs cvmx_ipd_sub_port_fcs_t;\n+\n+/**\n+ * cvmx_ipd_sub_port_qos_cnt\n+ *\n+ * Will add the value (CNT) to the indicated Port-QOS register (PORT_QOS). The value added must\n+ * be\n+ * be the 2's complement of the value that needs to be subtracted.\n+ */\n+union cvmx_ipd_sub_port_qos_cnt {\n+\tu64 u64;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s {\n+\t\tu64 reserved_41_63 : 23;\n+\t\tu64 port_qos : 9;\n+\t\tu64 cnt : 32;\n+\t} s;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s cn52xx;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s cn56xx;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s cn61xx;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s cn63xx;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s cn66xx;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s cn68xx;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s cn68xxp1;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s cn70xx;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s cn70xxp1;\n+\tstruct cvmx_ipd_sub_port_qos_cnt_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_sub_port_qos_cnt cvmx_ipd_sub_port_qos_cnt_t;\n+\n+/**\n+ * cvmx_ipd_wqe_fpa_queue\n+ *\n+ * Which FPA Queue (0-7) to fetch page-pointers from for WQE's\n+ *\n+ */\n+union cvmx_ipd_wqe_fpa_queue {\n+\tu64 u64;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 wqe_pool : 3;\n+\t} s;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn30xx;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn31xx;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn38xx;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn38xxp2;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn50xx;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn52xx;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn52xxp1;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn56xx;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn56xxp1;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn58xx;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn58xxp1;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn61xx;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn63xx;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn63xxp1;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn66xx;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn68xx;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn68xxp1;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn70xx;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cn70xxp1;\n+\tstruct cvmx_ipd_wqe_fpa_queue_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_wqe_fpa_queue cvmx_ipd_wqe_fpa_queue_t;\n+\n+/**\n+ * cvmx_ipd_wqe_ptr_valid\n+ *\n+ * The value of the WQE-pointer fetched and in the valid register.\n+ *\n+ */\n+union cvmx_ipd_wqe_ptr_valid {\n+\tu64 u64;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 ptr : 29;\n+\t} s;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn30xx;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn31xx;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn38xx;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn50xx;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn52xx;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn52xxp1;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn56xx;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn56xxp1;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn58xx;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn58xxp1;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn61xx;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn63xx;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn63xxp1;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn66xx;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn70xx;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cn70xxp1;\n+\tstruct cvmx_ipd_wqe_ptr_valid_s cnf71xx;\n+};\n+\n+typedef union cvmx_ipd_wqe_ptr_valid cvmx_ipd_wqe_ptr_valid_t;\n+\n+#endif\n", "prefixes": [ "v1", "13/50" ] }