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{
    "id": 1414989,
    "url": "http://patchwork.ozlabs.org/api/patches/1414989/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-11-sr@denx.de/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
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        "list_archive_url_format": "",
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    },
    "msgid": "<20201211160612.1498780-11-sr@denx.de>",
    "list_archive_url": null,
    "date": "2020-12-11T16:05:32",
    "name": "[v1,10/50] mips: octeon: Add cvmx-fpa-defs.h header file",
    "commit_ref": "fc3e91081c36b043b651b501565f90b75ca5a4ca",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "a4ad783ef84512727a3fec8474cbd38adc669f0d",
    "submitter": {
        "id": 13,
        "url": "http://patchwork.ozlabs.org/api/people/13/?format=api",
        "name": "Stefan Roese",
        "email": "sr@denx.de"
    },
    "delegate": {
        "id": 4307,
        "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api",
        "username": "danielschwierzeck",
        "first_name": "Daniel",
        "last_name": "Schwierzeck",
        "email": "daniel.schwierzeck@googlemail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-11-sr@denx.de/mbox/",
    "series": [
        {
            "id": 220054,
            "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054",
            "date": "2020-12-11T16:05:23",
            "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1414989/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1414989/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Stefan Roese <sr@denx.de>",
        "To": "u-boot@lists.denx.de",
        "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com",
        "Subject": "[PATCH v1 10/50] mips: octeon: Add cvmx-fpa-defs.h header file",
        "Date": "Fri, 11 Dec 2020 17:05:32 +0100",
        "Message-Id": "<20201211160612.1498780-11-sr@denx.de>",
        "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>",
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    "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-fpa-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-fpa-defs.h  | 1866 +++++++++++++++++\n 1 file changed, 1866 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-fpa-defs.h",
    "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-fpa-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-fpa-defs.h\nnew file mode 100644\nindex 0000000000..13ce7d8c96\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-fpa-defs.h\n@@ -0,0 +1,1866 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon fpa.\n+ */\n+\n+#ifndef __CVMX_FPA_DEFS_H__\n+#define __CVMX_FPA_DEFS_H__\n+\n+#define CVMX_FPA_ADDR_RANGE_ERROR CVMX_FPA_ADDR_RANGE_ERROR_FUNC()\n+static inline u64 CVMX_FPA_ADDR_RANGE_ERROR_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180028000458ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0001280000000458ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0001280000000458ull;\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001280000000458ull;\n+\t}\n+\treturn 0x0001280000000458ull;\n+}\n+\n+#define CVMX_FPA_AURAX_CFG(offset)\t     (0x0001280020100000ull + ((offset) & 1023) * 8)\n+#define CVMX_FPA_AURAX_CNT(offset)\t     (0x0001280020200000ull + ((offset) & 1023) * 8)\n+#define CVMX_FPA_AURAX_CNT_ADD(offset)\t     (0x0001280020300000ull + ((offset) & 1023) * 8)\n+#define CVMX_FPA_AURAX_CNT_LEVELS(offset)    (0x0001280020800000ull + ((offset) & 1023) * 8)\n+#define CVMX_FPA_AURAX_CNT_LIMIT(offset)     (0x0001280020400000ull + ((offset) & 1023) * 8)\n+#define CVMX_FPA_AURAX_CNT_THRESHOLD(offset) (0x0001280020500000ull + ((offset) & 1023) * 8)\n+#define CVMX_FPA_AURAX_INT(offset)\t     (0x0001280020600000ull + ((offset) & 1023) * 8)\n+#define CVMX_FPA_AURAX_POOL(offset)\t     (0x0001280020000000ull + ((offset) & 1023) * 8)\n+#define CVMX_FPA_AURAX_POOL_LEVELS(offset)   (0x0001280020700000ull + ((offset) & 1023) * 8)\n+#define CVMX_FPA_BIST_STATUS\t\t     CVMX_FPA_BIST_STATUS_FUNC()\n+static inline u64 CVMX_FPA_BIST_STATUS_FUNC(void)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00011800280000E8ull;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x00012800000000E8ull;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x00012800000000E8ull;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x00012800000000E8ull;\n+\t}\n+\treturn 0x00012800000000E8ull;\n+}\n+\n+#ifndef CVMX_FPA_CLK_COUNT // test-only (also in octeon_ddr.h)\n+#define CVMX_FPA_CLK_COUNT (0x00012800000000F0ull)\n+#endif\n+#define CVMX_FPA_CTL_STATUS\t\t (0x0001180028000050ull)\n+#define CVMX_FPA_ECC_CTL\t\t (0x0001280000000058ull)\n+#define CVMX_FPA_ECC_INT\t\t (0x0001280000000068ull)\n+#define CVMX_FPA_ERR_INT\t\t (0x0001280000000040ull)\n+#define CVMX_FPA_FPF0_MARKS\t\t (0x0001180028000000ull)\n+#define CVMX_FPA_FPF0_SIZE\t\t (0x0001180028000058ull)\n+#define CVMX_FPA_FPF1_MARKS\t\t CVMX_FPA_FPFX_MARKS(1)\n+#define CVMX_FPA_FPF2_MARKS\t\t CVMX_FPA_FPFX_MARKS(2)\n+#define CVMX_FPA_FPF3_MARKS\t\t CVMX_FPA_FPFX_MARKS(3)\n+#define CVMX_FPA_FPF4_MARKS\t\t CVMX_FPA_FPFX_MARKS(4)\n+#define CVMX_FPA_FPF5_MARKS\t\t CVMX_FPA_FPFX_MARKS(5)\n+#define CVMX_FPA_FPF6_MARKS\t\t CVMX_FPA_FPFX_MARKS(6)\n+#define CVMX_FPA_FPF7_MARKS\t\t CVMX_FPA_FPFX_MARKS(7)\n+#define CVMX_FPA_FPF8_MARKS\t\t (0x0001180028000240ull)\n+#define CVMX_FPA_FPF8_SIZE\t\t (0x0001180028000248ull)\n+#define CVMX_FPA_FPFX_MARKS(offset)\t (0x0001180028000008ull + ((offset) & 7) * 8 - 8 * 1)\n+#define CVMX_FPA_FPFX_SIZE(offset)\t (0x0001180028000060ull + ((offset) & 7) * 8 - 8 * 1)\n+#define CVMX_FPA_GEN_CFG\t\t (0x0001280000000050ull)\n+#define CVMX_FPA_INT_ENB\t\t (0x0001180028000048ull)\n+#define CVMX_FPA_INT_SUM\t\t (0x0001180028000040ull)\n+#define CVMX_FPA_PACKET_THRESHOLD\t (0x0001180028000460ull)\n+#define CVMX_FPA_POOLX_AVAILABLE(offset) (0x0001280010300000ull + ((offset) & 63) * 8)\n+#define CVMX_FPA_POOLX_CFG(offset)\t (0x0001280010000000ull + ((offset) & 63) * 8)\n+static inline u64 CVMX_FPA_POOLX_END_ADDR(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180028000358ull + (offset) * 8;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180028000358ull + (offset) * 8;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001280010600000ull + (offset) * 8;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0001280010600000ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0001280010600000ull + (offset) * 8;\n+\t}\n+\treturn 0x0001280010600000ull + (offset) * 8;\n+}\n+\n+#define CVMX_FPA_POOLX_FPF_MARKS(offset)  (0x0001280010100000ull + ((offset) & 63) * 8)\n+#define CVMX_FPA_POOLX_INT(offset)\t  (0x0001280010A00000ull + ((offset) & 63) * 8)\n+#define CVMX_FPA_POOLX_OP_PC(offset)\t  (0x0001280010F00000ull + ((offset) & 63) * 8)\n+#define CVMX_FPA_POOLX_STACK_ADDR(offset) (0x0001280010900000ull + ((offset) & 63) * 8)\n+#define CVMX_FPA_POOLX_STACK_BASE(offset) (0x0001280010700000ull + ((offset) & 63) * 8)\n+#define CVMX_FPA_POOLX_STACK_END(offset)  (0x0001280010800000ull + ((offset) & 63) * 8)\n+static inline u64 CVMX_FPA_POOLX_START_ADDR(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180028000258ull + (offset) * 8;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180028000258ull + (offset) * 8;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001280010500000ull + (offset) * 8;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0001280010500000ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0001280010500000ull + (offset) * 8;\n+\t}\n+\treturn 0x0001280010500000ull + (offset) * 8;\n+}\n+\n+static inline u64 CVMX_FPA_POOLX_THRESHOLD(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180028000140ull + (offset) * 8;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001180028000140ull + (offset) * 8;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001280010400000ull + (offset) * 8;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0001280010400000ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0001280010400000ull + (offset) * 8;\n+\t}\n+\treturn 0x0001280010400000ull + (offset) * 8;\n+}\n+\n+#define CVMX_FPA_QUE0_PAGE_INDEX\t CVMX_FPA_QUEX_PAGE_INDEX(0)\n+#define CVMX_FPA_QUE1_PAGE_INDEX\t CVMX_FPA_QUEX_PAGE_INDEX(1)\n+#define CVMX_FPA_QUE2_PAGE_INDEX\t CVMX_FPA_QUEX_PAGE_INDEX(2)\n+#define CVMX_FPA_QUE3_PAGE_INDEX\t CVMX_FPA_QUEX_PAGE_INDEX(3)\n+#define CVMX_FPA_QUE4_PAGE_INDEX\t CVMX_FPA_QUEX_PAGE_INDEX(4)\n+#define CVMX_FPA_QUE5_PAGE_INDEX\t CVMX_FPA_QUEX_PAGE_INDEX(5)\n+#define CVMX_FPA_QUE6_PAGE_INDEX\t CVMX_FPA_QUEX_PAGE_INDEX(6)\n+#define CVMX_FPA_QUE7_PAGE_INDEX\t CVMX_FPA_QUEX_PAGE_INDEX(7)\n+#define CVMX_FPA_QUE8_PAGE_INDEX\t (0x0001180028000250ull)\n+#define CVMX_FPA_QUEX_AVAILABLE(offset)\t (0x0001180028000098ull + ((offset) & 15) * 8)\n+#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (0x00011800280000F0ull + ((offset) & 7) * 8)\n+#define CVMX_FPA_QUE_ACT\t\t (0x0001180028000138ull)\n+#define CVMX_FPA_QUE_EXP\t\t (0x0001180028000130ull)\n+#define CVMX_FPA_RD_LATENCY_PC\t\t (0x0001280000000610ull)\n+#define CVMX_FPA_RD_REQ_PC\t\t (0x0001280000000600ull)\n+#define CVMX_FPA_RED_DELAY\t\t (0x0001280000000100ull)\n+#define CVMX_FPA_SFT_RST\t\t (0x0001280000000000ull)\n+#define CVMX_FPA_WART_CTL\t\t (0x00011800280000D8ull)\n+#define CVMX_FPA_WART_STATUS\t\t (0x00011800280000E0ull)\n+#define CVMX_FPA_WQE_THRESHOLD\t\t (0x0001180028000468ull)\n+\n+/**\n+ * cvmx_fpa_addr_range_error\n+ *\n+ * When any FPA_POOL()_INT[RANGE] error occurs, this register is latched with additional\n+ * error information.\n+ */\n+union cvmx_fpa_addr_range_error {\n+\tu64 u64;\n+\tstruct cvmx_fpa_addr_range_error_s {\n+\t\tu64 reserved_0_63 : 64;\n+\t} s;\n+\tstruct cvmx_fpa_addr_range_error_cn61xx {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 pool : 5;\n+\t\tu64 addr : 33;\n+\t} cn61xx;\n+\tstruct cvmx_fpa_addr_range_error_cn61xx cn66xx;\n+\tstruct cvmx_fpa_addr_range_error_cn61xx cn68xx;\n+\tstruct cvmx_fpa_addr_range_error_cn61xx cn68xxp1;\n+\tstruct cvmx_fpa_addr_range_error_cn61xx cn70xx;\n+\tstruct cvmx_fpa_addr_range_error_cn61xx cn70xxp1;\n+\tstruct cvmx_fpa_addr_range_error_cn73xx {\n+\t\tu64 reserved_54_63 : 10;\n+\t\tu64 pool : 6;\n+\t\tu64 reserved_42_47 : 6;\n+\t\tu64 addr : 42;\n+\t} cn73xx;\n+\tstruct cvmx_fpa_addr_range_error_cn73xx cn78xx;\n+\tstruct cvmx_fpa_addr_range_error_cn73xx cn78xxp1;\n+\tstruct cvmx_fpa_addr_range_error_cn61xx cnf71xx;\n+\tstruct cvmx_fpa_addr_range_error_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_addr_range_error cvmx_fpa_addr_range_error_t;\n+\n+/**\n+ * cvmx_fpa_aura#_cfg\n+ *\n+ * This register configures aura backpressure, etc.\n+ *\n+ */\n+union cvmx_fpa_aurax_cfg {\n+\tu64 u64;\n+\tstruct cvmx_fpa_aurax_cfg_s {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 ptr_dis : 1;\n+\t\tu64 avg_con : 9;\n+\t} s;\n+\tstruct cvmx_fpa_aurax_cfg_s cn73xx;\n+\tstruct cvmx_fpa_aurax_cfg_s cn78xx;\n+\tstruct cvmx_fpa_aurax_cfg_s cn78xxp1;\n+\tstruct cvmx_fpa_aurax_cfg_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_aurax_cfg cvmx_fpa_aurax_cfg_t;\n+\n+/**\n+ * cvmx_fpa_aura#_cnt\n+ */\n+union cvmx_fpa_aurax_cnt {\n+\tu64 u64;\n+\tstruct cvmx_fpa_aurax_cnt_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 cnt : 40;\n+\t} s;\n+\tstruct cvmx_fpa_aurax_cnt_s cn73xx;\n+\tstruct cvmx_fpa_aurax_cnt_s cn78xx;\n+\tstruct cvmx_fpa_aurax_cnt_s cn78xxp1;\n+\tstruct cvmx_fpa_aurax_cnt_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_aurax_cnt cvmx_fpa_aurax_cnt_t;\n+\n+/**\n+ * cvmx_fpa_aura#_cnt_add\n+ */\n+union cvmx_fpa_aurax_cnt_add {\n+\tu64 u64;\n+\tstruct cvmx_fpa_aurax_cnt_add_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 cnt : 40;\n+\t} s;\n+\tstruct cvmx_fpa_aurax_cnt_add_s cn73xx;\n+\tstruct cvmx_fpa_aurax_cnt_add_s cn78xx;\n+\tstruct cvmx_fpa_aurax_cnt_add_s cn78xxp1;\n+\tstruct cvmx_fpa_aurax_cnt_add_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_aurax_cnt_add cvmx_fpa_aurax_cnt_add_t;\n+\n+/**\n+ * cvmx_fpa_aura#_cnt_levels\n+ */\n+union cvmx_fpa_aurax_cnt_levels {\n+\tu64 u64;\n+\tstruct cvmx_fpa_aurax_cnt_levels_s {\n+\t\tu64 reserved_41_63 : 23;\n+\t\tu64 drop_dis : 1;\n+\t\tu64 bp_ena : 1;\n+\t\tu64 red_ena : 1;\n+\t\tu64 shift : 6;\n+\t\tu64 bp : 8;\n+\t\tu64 drop : 8;\n+\t\tu64 pass : 8;\n+\t\tu64 level : 8;\n+\t} s;\n+\tstruct cvmx_fpa_aurax_cnt_levels_s cn73xx;\n+\tstruct cvmx_fpa_aurax_cnt_levels_s cn78xx;\n+\tstruct cvmx_fpa_aurax_cnt_levels_s cn78xxp1;\n+\tstruct cvmx_fpa_aurax_cnt_levels_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_aurax_cnt_levels cvmx_fpa_aurax_cnt_levels_t;\n+\n+/**\n+ * cvmx_fpa_aura#_cnt_limit\n+ */\n+union cvmx_fpa_aurax_cnt_limit {\n+\tu64 u64;\n+\tstruct cvmx_fpa_aurax_cnt_limit_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 limit : 40;\n+\t} s;\n+\tstruct cvmx_fpa_aurax_cnt_limit_s cn73xx;\n+\tstruct cvmx_fpa_aurax_cnt_limit_s cn78xx;\n+\tstruct cvmx_fpa_aurax_cnt_limit_s cn78xxp1;\n+\tstruct cvmx_fpa_aurax_cnt_limit_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_aurax_cnt_limit cvmx_fpa_aurax_cnt_limit_t;\n+\n+/**\n+ * cvmx_fpa_aura#_cnt_threshold\n+ */\n+union cvmx_fpa_aurax_cnt_threshold {\n+\tu64 u64;\n+\tstruct cvmx_fpa_aurax_cnt_threshold_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 thresh : 40;\n+\t} s;\n+\tstruct cvmx_fpa_aurax_cnt_threshold_s cn73xx;\n+\tstruct cvmx_fpa_aurax_cnt_threshold_s cn78xx;\n+\tstruct cvmx_fpa_aurax_cnt_threshold_s cn78xxp1;\n+\tstruct cvmx_fpa_aurax_cnt_threshold_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_aurax_cnt_threshold cvmx_fpa_aurax_cnt_threshold_t;\n+\n+/**\n+ * cvmx_fpa_aura#_int\n+ */\n+union cvmx_fpa_aurax_int {\n+\tu64 u64;\n+\tstruct cvmx_fpa_aurax_int_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 thresh : 1;\n+\t} s;\n+\tstruct cvmx_fpa_aurax_int_s cn73xx;\n+\tstruct cvmx_fpa_aurax_int_s cn78xx;\n+\tstruct cvmx_fpa_aurax_int_s cn78xxp1;\n+\tstruct cvmx_fpa_aurax_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_aurax_int cvmx_fpa_aurax_int_t;\n+\n+/**\n+ * cvmx_fpa_aura#_pool\n+ *\n+ * Provides the mapping from each aura to the pool number.\n+ *\n+ */\n+union cvmx_fpa_aurax_pool {\n+\tu64 u64;\n+\tstruct cvmx_fpa_aurax_pool_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 pool : 6;\n+\t} s;\n+\tstruct cvmx_fpa_aurax_pool_s cn73xx;\n+\tstruct cvmx_fpa_aurax_pool_s cn78xx;\n+\tstruct cvmx_fpa_aurax_pool_s cn78xxp1;\n+\tstruct cvmx_fpa_aurax_pool_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_aurax_pool cvmx_fpa_aurax_pool_t;\n+\n+/**\n+ * cvmx_fpa_aura#_pool_levels\n+ */\n+union cvmx_fpa_aurax_pool_levels {\n+\tu64 u64;\n+\tstruct cvmx_fpa_aurax_pool_levels_s {\n+\t\tu64 reserved_41_63 : 23;\n+\t\tu64 drop_dis : 1;\n+\t\tu64 bp_ena : 1;\n+\t\tu64 red_ena : 1;\n+\t\tu64 shift : 6;\n+\t\tu64 bp : 8;\n+\t\tu64 drop : 8;\n+\t\tu64 pass : 8;\n+\t\tu64 level : 8;\n+\t} s;\n+\tstruct cvmx_fpa_aurax_pool_levels_s cn73xx;\n+\tstruct cvmx_fpa_aurax_pool_levels_s cn78xx;\n+\tstruct cvmx_fpa_aurax_pool_levels_s cn78xxp1;\n+\tstruct cvmx_fpa_aurax_pool_levels_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_aurax_pool_levels cvmx_fpa_aurax_pool_levels_t;\n+\n+/**\n+ * cvmx_fpa_bist_status\n+ *\n+ * This register provides the result of the BIST run on the FPA memories.\n+ *\n+ */\n+union cvmx_fpa_bist_status {\n+\tu64 u64;\n+\tstruct cvmx_fpa_bist_status_s {\n+\t\tu64 reserved_0_63 : 64;\n+\t} s;\n+\tstruct cvmx_fpa_bist_status_cn30xx {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 frd : 1;\n+\t\tu64 fpf0 : 1;\n+\t\tu64 fpf1 : 1;\n+\t\tu64 ffr : 1;\n+\t\tu64 fdr : 1;\n+\t} cn30xx;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn31xx;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn38xx;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn38xxp2;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn50xx;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn52xx;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn52xxp1;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn56xx;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn56xxp1;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn58xx;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn58xxp1;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn61xx;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn63xx;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn63xxp1;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn66xx;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn68xx;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn68xxp1;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn70xx;\n+\tstruct cvmx_fpa_bist_status_cn30xx cn70xxp1;\n+\tstruct cvmx_fpa_bist_status_cn73xx {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 status : 38;\n+\t} cn73xx;\n+\tstruct cvmx_fpa_bist_status_cn73xx cn78xx;\n+\tstruct cvmx_fpa_bist_status_cn73xx cn78xxp1;\n+\tstruct cvmx_fpa_bist_status_cn30xx cnf71xx;\n+\tstruct cvmx_fpa_bist_status_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_bist_status cvmx_fpa_bist_status_t;\n+\n+/**\n+ * cvmx_fpa_clk_count\n+ *\n+ * This register counts the number of coprocessor-clock cycles since the deassertion of reset.\n+ *\n+ */\n+union cvmx_fpa_clk_count {\n+\tu64 u64;\n+\tstruct cvmx_fpa_clk_count_s {\n+\t\tu64 clk_cnt : 64;\n+\t} s;\n+\tstruct cvmx_fpa_clk_count_s cn73xx;\n+\tstruct cvmx_fpa_clk_count_s cn78xx;\n+\tstruct cvmx_fpa_clk_count_s cn78xxp1;\n+\tstruct cvmx_fpa_clk_count_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_clk_count cvmx_fpa_clk_count_t;\n+\n+/**\n+ * cvmx_fpa_ctl_status\n+ *\n+ * The FPA's interrupt enable register.\n+ *\n+ */\n+union cvmx_fpa_ctl_status {\n+\tu64 u64;\n+\tstruct cvmx_fpa_ctl_status_s {\n+\t\tu64 reserved_21_63 : 43;\n+\t\tu64 free_en : 1;\n+\t\tu64 ret_off : 1;\n+\t\tu64 req_off : 1;\n+\t\tu64 reset : 1;\n+\t\tu64 use_ldt : 1;\n+\t\tu64 use_stt : 1;\n+\t\tu64 enb : 1;\n+\t\tu64 mem1_err : 7;\n+\t\tu64 mem0_err : 7;\n+\t} s;\n+\tstruct cvmx_fpa_ctl_status_cn30xx {\n+\t\tu64 reserved_18_63 : 46;\n+\t\tu64 reset : 1;\n+\t\tu64 use_ldt : 1;\n+\t\tu64 use_stt : 1;\n+\t\tu64 enb : 1;\n+\t\tu64 mem1_err : 7;\n+\t\tu64 mem0_err : 7;\n+\t} cn30xx;\n+\tstruct cvmx_fpa_ctl_status_cn30xx cn31xx;\n+\tstruct cvmx_fpa_ctl_status_cn30xx cn38xx;\n+\tstruct cvmx_fpa_ctl_status_cn30xx cn38xxp2;\n+\tstruct cvmx_fpa_ctl_status_cn30xx cn50xx;\n+\tstruct cvmx_fpa_ctl_status_cn30xx cn52xx;\n+\tstruct cvmx_fpa_ctl_status_cn30xx cn52xxp1;\n+\tstruct cvmx_fpa_ctl_status_cn30xx cn56xx;\n+\tstruct cvmx_fpa_ctl_status_cn30xx cn56xxp1;\n+\tstruct cvmx_fpa_ctl_status_cn30xx cn58xx;\n+\tstruct cvmx_fpa_ctl_status_cn30xx cn58xxp1;\n+\tstruct cvmx_fpa_ctl_status_s cn61xx;\n+\tstruct cvmx_fpa_ctl_status_s cn63xx;\n+\tstruct cvmx_fpa_ctl_status_cn30xx cn63xxp1;\n+\tstruct cvmx_fpa_ctl_status_s cn66xx;\n+\tstruct cvmx_fpa_ctl_status_s cn68xx;\n+\tstruct cvmx_fpa_ctl_status_s cn68xxp1;\n+\tstruct cvmx_fpa_ctl_status_s cn70xx;\n+\tstruct cvmx_fpa_ctl_status_s cn70xxp1;\n+\tstruct cvmx_fpa_ctl_status_s cnf71xx;\n+};\n+\n+typedef union cvmx_fpa_ctl_status cvmx_fpa_ctl_status_t;\n+\n+/**\n+ * cvmx_fpa_ecc_ctl\n+ *\n+ * This register allows inserting ECC errors for testing.\n+ *\n+ */\n+union cvmx_fpa_ecc_ctl {\n+\tu64 u64;\n+\tstruct cvmx_fpa_ecc_ctl_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 ram_flip1 : 20;\n+\t\tu64 reserved_41_41 : 1;\n+\t\tu64 ram_flip0 : 20;\n+\t\tu64 reserved_20_20 : 1;\n+\t\tu64 ram_cdis : 20;\n+\t} s;\n+\tstruct cvmx_fpa_ecc_ctl_s cn73xx;\n+\tstruct cvmx_fpa_ecc_ctl_s cn78xx;\n+\tstruct cvmx_fpa_ecc_ctl_s cn78xxp1;\n+\tstruct cvmx_fpa_ecc_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_ecc_ctl cvmx_fpa_ecc_ctl_t;\n+\n+/**\n+ * cvmx_fpa_ecc_int\n+ *\n+ * This register contains ECC error interrupt summary bits.\n+ *\n+ */\n+union cvmx_fpa_ecc_int {\n+\tu64 u64;\n+\tstruct cvmx_fpa_ecc_int_s {\n+\t\tu64 reserved_52_63 : 12;\n+\t\tu64 ram_dbe : 20;\n+\t\tu64 reserved_20_31 : 12;\n+\t\tu64 ram_sbe : 20;\n+\t} s;\n+\tstruct cvmx_fpa_ecc_int_s cn73xx;\n+\tstruct cvmx_fpa_ecc_int_s cn78xx;\n+\tstruct cvmx_fpa_ecc_int_s cn78xxp1;\n+\tstruct cvmx_fpa_ecc_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_ecc_int cvmx_fpa_ecc_int_t;\n+\n+/**\n+ * cvmx_fpa_err_int\n+ *\n+ * This register contains the global (non-pool) error interrupt summary bits of the FPA.\n+ *\n+ */\n+union cvmx_fpa_err_int {\n+\tu64 u64;\n+\tstruct cvmx_fpa_err_int_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 hw_sub : 1;\n+\t\tu64 hw_add : 1;\n+\t\tu64 cnt_sub : 1;\n+\t\tu64 cnt_add : 1;\n+\t} s;\n+\tstruct cvmx_fpa_err_int_s cn73xx;\n+\tstruct cvmx_fpa_err_int_s cn78xx;\n+\tstruct cvmx_fpa_err_int_s cn78xxp1;\n+\tstruct cvmx_fpa_err_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_err_int cvmx_fpa_err_int_t;\n+\n+/**\n+ * cvmx_fpa_fpf#_marks\n+ *\n+ * \"The high and low watermark register that determines when we write and read free pages from\n+ * L2C\n+ * for Queue 1. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend\n+ * value\n+ * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)\"\n+ */\n+union cvmx_fpa_fpfx_marks {\n+\tu64 u64;\n+\tstruct cvmx_fpa_fpfx_marks_s {\n+\t\tu64 reserved_22_63 : 42;\n+\t\tu64 fpf_wr : 11;\n+\t\tu64 fpf_rd : 11;\n+\t} s;\n+\tstruct cvmx_fpa_fpfx_marks_s cn38xx;\n+\tstruct cvmx_fpa_fpfx_marks_s cn38xxp2;\n+\tstruct cvmx_fpa_fpfx_marks_s cn56xx;\n+\tstruct cvmx_fpa_fpfx_marks_s cn56xxp1;\n+\tstruct cvmx_fpa_fpfx_marks_s cn58xx;\n+\tstruct cvmx_fpa_fpfx_marks_s cn58xxp1;\n+\tstruct cvmx_fpa_fpfx_marks_s cn61xx;\n+\tstruct cvmx_fpa_fpfx_marks_s cn63xx;\n+\tstruct cvmx_fpa_fpfx_marks_s cn63xxp1;\n+\tstruct cvmx_fpa_fpfx_marks_s cn66xx;\n+\tstruct cvmx_fpa_fpfx_marks_s cn68xx;\n+\tstruct cvmx_fpa_fpfx_marks_s cn68xxp1;\n+\tstruct cvmx_fpa_fpfx_marks_s cn70xx;\n+\tstruct cvmx_fpa_fpfx_marks_s cn70xxp1;\n+\tstruct cvmx_fpa_fpfx_marks_s cnf71xx;\n+};\n+\n+typedef union cvmx_fpa_fpfx_marks cvmx_fpa_fpfx_marks_t;\n+\n+/**\n+ * cvmx_fpa_fpf#_size\n+ *\n+ * \"FPA_FPFX_SIZE = FPA's Queue 1-7 Free Page FIFO Size\n+ * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are\n+ * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used.\n+ * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048.\"\n+ */\n+union cvmx_fpa_fpfx_size {\n+\tu64 u64;\n+\tstruct cvmx_fpa_fpfx_size_s {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 fpf_siz : 11;\n+\t} s;\n+\tstruct cvmx_fpa_fpfx_size_s cn38xx;\n+\tstruct cvmx_fpa_fpfx_size_s cn38xxp2;\n+\tstruct cvmx_fpa_fpfx_size_s cn56xx;\n+\tstruct cvmx_fpa_fpfx_size_s cn56xxp1;\n+\tstruct cvmx_fpa_fpfx_size_s cn58xx;\n+\tstruct cvmx_fpa_fpfx_size_s cn58xxp1;\n+\tstruct cvmx_fpa_fpfx_size_s cn61xx;\n+\tstruct cvmx_fpa_fpfx_size_s cn63xx;\n+\tstruct cvmx_fpa_fpfx_size_s cn63xxp1;\n+\tstruct cvmx_fpa_fpfx_size_s cn66xx;\n+\tstruct cvmx_fpa_fpfx_size_s cn68xx;\n+\tstruct cvmx_fpa_fpfx_size_s cn68xxp1;\n+\tstruct cvmx_fpa_fpfx_size_s cn70xx;\n+\tstruct cvmx_fpa_fpfx_size_s cn70xxp1;\n+\tstruct cvmx_fpa_fpfx_size_s cnf71xx;\n+};\n+\n+typedef union cvmx_fpa_fpfx_size cvmx_fpa_fpfx_size_t;\n+\n+/**\n+ * cvmx_fpa_fpf0_marks\n+ *\n+ * \"The high and low watermark register that determines when we write and read free pages from\n+ * L2C\n+ * for Queue 0. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend\n+ * value\n+ * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)\"\n+ */\n+union cvmx_fpa_fpf0_marks {\n+\tu64 u64;\n+\tstruct cvmx_fpa_fpf0_marks_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 fpf_wr : 12;\n+\t\tu64 fpf_rd : 12;\n+\t} s;\n+\tstruct cvmx_fpa_fpf0_marks_s cn38xx;\n+\tstruct cvmx_fpa_fpf0_marks_s cn38xxp2;\n+\tstruct cvmx_fpa_fpf0_marks_s cn56xx;\n+\tstruct cvmx_fpa_fpf0_marks_s cn56xxp1;\n+\tstruct cvmx_fpa_fpf0_marks_s cn58xx;\n+\tstruct cvmx_fpa_fpf0_marks_s cn58xxp1;\n+\tstruct cvmx_fpa_fpf0_marks_s cn61xx;\n+\tstruct cvmx_fpa_fpf0_marks_s cn63xx;\n+\tstruct cvmx_fpa_fpf0_marks_s cn63xxp1;\n+\tstruct cvmx_fpa_fpf0_marks_s cn66xx;\n+\tstruct cvmx_fpa_fpf0_marks_s cn68xx;\n+\tstruct cvmx_fpa_fpf0_marks_s cn68xxp1;\n+\tstruct cvmx_fpa_fpf0_marks_s cn70xx;\n+\tstruct cvmx_fpa_fpf0_marks_s cn70xxp1;\n+\tstruct cvmx_fpa_fpf0_marks_s cnf71xx;\n+};\n+\n+typedef union cvmx_fpa_fpf0_marks cvmx_fpa_fpf0_marks_t;\n+\n+/**\n+ * cvmx_fpa_fpf0_size\n+ *\n+ * \"The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are\n+ * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used.\n+ * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048.\"\n+ */\n+union cvmx_fpa_fpf0_size {\n+\tu64 u64;\n+\tstruct cvmx_fpa_fpf0_size_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 fpf_siz : 12;\n+\t} s;\n+\tstruct cvmx_fpa_fpf0_size_s cn38xx;\n+\tstruct cvmx_fpa_fpf0_size_s cn38xxp2;\n+\tstruct cvmx_fpa_fpf0_size_s cn56xx;\n+\tstruct cvmx_fpa_fpf0_size_s cn56xxp1;\n+\tstruct cvmx_fpa_fpf0_size_s cn58xx;\n+\tstruct cvmx_fpa_fpf0_size_s cn58xxp1;\n+\tstruct cvmx_fpa_fpf0_size_s cn61xx;\n+\tstruct cvmx_fpa_fpf0_size_s cn63xx;\n+\tstruct cvmx_fpa_fpf0_size_s cn63xxp1;\n+\tstruct cvmx_fpa_fpf0_size_s cn66xx;\n+\tstruct cvmx_fpa_fpf0_size_s cn68xx;\n+\tstruct cvmx_fpa_fpf0_size_s cn68xxp1;\n+\tstruct cvmx_fpa_fpf0_size_s cn70xx;\n+\tstruct cvmx_fpa_fpf0_size_s cn70xxp1;\n+\tstruct cvmx_fpa_fpf0_size_s cnf71xx;\n+};\n+\n+typedef union cvmx_fpa_fpf0_size cvmx_fpa_fpf0_size_t;\n+\n+/**\n+ * cvmx_fpa_fpf8_marks\n+ *\n+ * Reserved through 0x238 for additional thresholds\n+ *\n+ *                  FPA_FPF8_MARKS = FPA's Queue 8 Free Page FIFO Read Write Marks\n+ *\n+ * The high and low watermark register that determines when we write and read free pages from L2C\n+ * for Queue 8. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value\n+ * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)\n+ */\n+union cvmx_fpa_fpf8_marks {\n+\tu64 u64;\n+\tstruct cvmx_fpa_fpf8_marks_s {\n+\t\tu64 reserved_22_63 : 42;\n+\t\tu64 fpf_wr : 11;\n+\t\tu64 fpf_rd : 11;\n+\t} s;\n+\tstruct cvmx_fpa_fpf8_marks_s cn68xx;\n+\tstruct cvmx_fpa_fpf8_marks_s cn68xxp1;\n+};\n+\n+typedef union cvmx_fpa_fpf8_marks cvmx_fpa_fpf8_marks_t;\n+\n+/**\n+ * cvmx_fpa_fpf8_size\n+ *\n+ * FPA_FPF8_SIZE = FPA's Queue 8 Free Page FIFO Size\n+ *\n+ * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are\n+ * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used.\n+ * The sum of the 9 (0-8) FPA_FPF#_SIZE registers must be limited to 2048.\n+ */\n+union cvmx_fpa_fpf8_size {\n+\tu64 u64;\n+\tstruct cvmx_fpa_fpf8_size_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 fpf_siz : 12;\n+\t} s;\n+\tstruct cvmx_fpa_fpf8_size_s cn68xx;\n+\tstruct cvmx_fpa_fpf8_size_s cn68xxp1;\n+};\n+\n+typedef union cvmx_fpa_fpf8_size cvmx_fpa_fpf8_size_t;\n+\n+/**\n+ * cvmx_fpa_gen_cfg\n+ *\n+ * This register provides FPA control and status information.\n+ *\n+ */\n+union cvmx_fpa_gen_cfg {\n+\tu64 u64;\n+\tstruct cvmx_fpa_gen_cfg_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 halfrate : 1;\n+\t\tu64 ocla_bp : 1;\n+\t\tu64 lvl_dly : 6;\n+\t\tu64 pools : 2;\n+\t\tu64 avg_en : 1;\n+\t\tu64 clk_override : 1;\n+\t} s;\n+\tstruct cvmx_fpa_gen_cfg_s cn73xx;\n+\tstruct cvmx_fpa_gen_cfg_s cn78xx;\n+\tstruct cvmx_fpa_gen_cfg_s cn78xxp1;\n+\tstruct cvmx_fpa_gen_cfg_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_gen_cfg cvmx_fpa_gen_cfg_t;\n+\n+/**\n+ * cvmx_fpa_int_enb\n+ *\n+ * The FPA's interrupt enable register.\n+ *\n+ */\n+union cvmx_fpa_int_enb {\n+\tu64 u64;\n+\tstruct cvmx_fpa_int_enb_s {\n+\t\tu64 reserved_50_63 : 14;\n+\t\tu64 paddr_e : 1;\n+\t\tu64 reserved_44_48 : 5;\n+\t\tu64 free7 : 1;\n+\t\tu64 free6 : 1;\n+\t\tu64 free5 : 1;\n+\t\tu64 free4 : 1;\n+\t\tu64 free3 : 1;\n+\t\tu64 free2 : 1;\n+\t\tu64 free1 : 1;\n+\t\tu64 free0 : 1;\n+\t\tu64 pool7th : 1;\n+\t\tu64 pool6th : 1;\n+\t\tu64 pool5th : 1;\n+\t\tu64 pool4th : 1;\n+\t\tu64 pool3th : 1;\n+\t\tu64 pool2th : 1;\n+\t\tu64 pool1th : 1;\n+\t\tu64 pool0th : 1;\n+\t\tu64 q7_perr : 1;\n+\t\tu64 q7_coff : 1;\n+\t\tu64 q7_und : 1;\n+\t\tu64 q6_perr : 1;\n+\t\tu64 q6_coff : 1;\n+\t\tu64 q6_und : 1;\n+\t\tu64 q5_perr : 1;\n+\t\tu64 q5_coff : 1;\n+\t\tu64 q5_und : 1;\n+\t\tu64 q4_perr : 1;\n+\t\tu64 q4_coff : 1;\n+\t\tu64 q4_und : 1;\n+\t\tu64 q3_perr : 1;\n+\t\tu64 q3_coff : 1;\n+\t\tu64 q3_und : 1;\n+\t\tu64 q2_perr : 1;\n+\t\tu64 q2_coff : 1;\n+\t\tu64 q2_und : 1;\n+\t\tu64 q1_perr : 1;\n+\t\tu64 q1_coff : 1;\n+\t\tu64 q1_und : 1;\n+\t\tu64 q0_perr : 1;\n+\t\tu64 q0_coff : 1;\n+\t\tu64 q0_und : 1;\n+\t\tu64 fed1_dbe : 1;\n+\t\tu64 fed1_sbe : 1;\n+\t\tu64 fed0_dbe : 1;\n+\t\tu64 fed0_sbe : 1;\n+\t} s;\n+\tstruct cvmx_fpa_int_enb_cn30xx {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 q7_perr : 1;\n+\t\tu64 q7_coff : 1;\n+\t\tu64 q7_und : 1;\n+\t\tu64 q6_perr : 1;\n+\t\tu64 q6_coff : 1;\n+\t\tu64 q6_und : 1;\n+\t\tu64 q5_perr : 1;\n+\t\tu64 q5_coff : 1;\n+\t\tu64 q5_und : 1;\n+\t\tu64 q4_perr : 1;\n+\t\tu64 q4_coff : 1;\n+\t\tu64 q4_und : 1;\n+\t\tu64 q3_perr : 1;\n+\t\tu64 q3_coff : 1;\n+\t\tu64 q3_und : 1;\n+\t\tu64 q2_perr : 1;\n+\t\tu64 q2_coff : 1;\n+\t\tu64 q2_und : 1;\n+\t\tu64 q1_perr : 1;\n+\t\tu64 q1_coff : 1;\n+\t\tu64 q1_und : 1;\n+\t\tu64 q0_perr : 1;\n+\t\tu64 q0_coff : 1;\n+\t\tu64 q0_und : 1;\n+\t\tu64 fed1_dbe : 1;\n+\t\tu64 fed1_sbe : 1;\n+\t\tu64 fed0_dbe : 1;\n+\t\tu64 fed0_sbe : 1;\n+\t} cn30xx;\n+\tstruct cvmx_fpa_int_enb_cn30xx cn31xx;\n+\tstruct cvmx_fpa_int_enb_cn30xx cn38xx;\n+\tstruct cvmx_fpa_int_enb_cn30xx cn38xxp2;\n+\tstruct cvmx_fpa_int_enb_cn30xx cn50xx;\n+\tstruct cvmx_fpa_int_enb_cn30xx cn52xx;\n+\tstruct cvmx_fpa_int_enb_cn30xx cn52xxp1;\n+\tstruct cvmx_fpa_int_enb_cn30xx cn56xx;\n+\tstruct cvmx_fpa_int_enb_cn30xx cn56xxp1;\n+\tstruct cvmx_fpa_int_enb_cn30xx cn58xx;\n+\tstruct cvmx_fpa_int_enb_cn30xx cn58xxp1;\n+\tstruct cvmx_fpa_int_enb_cn61xx {\n+\t\tu64 reserved_50_63 : 14;\n+\t\tu64 paddr_e : 1;\n+\t\tu64 res_44 : 5;\n+\t\tu64 free7 : 1;\n+\t\tu64 free6 : 1;\n+\t\tu64 free5 : 1;\n+\t\tu64 free4 : 1;\n+\t\tu64 free3 : 1;\n+\t\tu64 free2 : 1;\n+\t\tu64 free1 : 1;\n+\t\tu64 free0 : 1;\n+\t\tu64 pool7th : 1;\n+\t\tu64 pool6th : 1;\n+\t\tu64 pool5th : 1;\n+\t\tu64 pool4th : 1;\n+\t\tu64 pool3th : 1;\n+\t\tu64 pool2th : 1;\n+\t\tu64 pool1th : 1;\n+\t\tu64 pool0th : 1;\n+\t\tu64 q7_perr : 1;\n+\t\tu64 q7_coff : 1;\n+\t\tu64 q7_und : 1;\n+\t\tu64 q6_perr : 1;\n+\t\tu64 q6_coff : 1;\n+\t\tu64 q6_und : 1;\n+\t\tu64 q5_perr : 1;\n+\t\tu64 q5_coff : 1;\n+\t\tu64 q5_und : 1;\n+\t\tu64 q4_perr : 1;\n+\t\tu64 q4_coff : 1;\n+\t\tu64 q4_und : 1;\n+\t\tu64 q3_perr : 1;\n+\t\tu64 q3_coff : 1;\n+\t\tu64 q3_und : 1;\n+\t\tu64 q2_perr : 1;\n+\t\tu64 q2_coff : 1;\n+\t\tu64 q2_und : 1;\n+\t\tu64 q1_perr : 1;\n+\t\tu64 q1_coff : 1;\n+\t\tu64 q1_und : 1;\n+\t\tu64 q0_perr : 1;\n+\t\tu64 q0_coff : 1;\n+\t\tu64 q0_und : 1;\n+\t\tu64 fed1_dbe : 1;\n+\t\tu64 fed1_sbe : 1;\n+\t\tu64 fed0_dbe : 1;\n+\t\tu64 fed0_sbe : 1;\n+\t} cn61xx;\n+\tstruct cvmx_fpa_int_enb_cn63xx {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 free7 : 1;\n+\t\tu64 free6 : 1;\n+\t\tu64 free5 : 1;\n+\t\tu64 free4 : 1;\n+\t\tu64 free3 : 1;\n+\t\tu64 free2 : 1;\n+\t\tu64 free1 : 1;\n+\t\tu64 free0 : 1;\n+\t\tu64 pool7th : 1;\n+\t\tu64 pool6th : 1;\n+\t\tu64 pool5th : 1;\n+\t\tu64 pool4th : 1;\n+\t\tu64 pool3th : 1;\n+\t\tu64 pool2th : 1;\n+\t\tu64 pool1th : 1;\n+\t\tu64 pool0th : 1;\n+\t\tu64 q7_perr : 1;\n+\t\tu64 q7_coff : 1;\n+\t\tu64 q7_und : 1;\n+\t\tu64 q6_perr : 1;\n+\t\tu64 q6_coff : 1;\n+\t\tu64 q6_und : 1;\n+\t\tu64 q5_perr : 1;\n+\t\tu64 q5_coff : 1;\n+\t\tu64 q5_und : 1;\n+\t\tu64 q4_perr : 1;\n+\t\tu64 q4_coff : 1;\n+\t\tu64 q4_und : 1;\n+\t\tu64 q3_perr : 1;\n+\t\tu64 q3_coff : 1;\n+\t\tu64 q3_und : 1;\n+\t\tu64 q2_perr : 1;\n+\t\tu64 q2_coff : 1;\n+\t\tu64 q2_und : 1;\n+\t\tu64 q1_perr : 1;\n+\t\tu64 q1_coff : 1;\n+\t\tu64 q1_und : 1;\n+\t\tu64 q0_perr : 1;\n+\t\tu64 q0_coff : 1;\n+\t\tu64 q0_und : 1;\n+\t\tu64 fed1_dbe : 1;\n+\t\tu64 fed1_sbe : 1;\n+\t\tu64 fed0_dbe : 1;\n+\t\tu64 fed0_sbe : 1;\n+\t} cn63xx;\n+\tstruct cvmx_fpa_int_enb_cn30xx cn63xxp1;\n+\tstruct cvmx_fpa_int_enb_cn61xx cn66xx;\n+\tstruct cvmx_fpa_int_enb_cn68xx {\n+\t\tu64 reserved_50_63 : 14;\n+\t\tu64 paddr_e : 1;\n+\t\tu64 pool8th : 1;\n+\t\tu64 q8_perr : 1;\n+\t\tu64 q8_coff : 1;\n+\t\tu64 q8_und : 1;\n+\t\tu64 free8 : 1;\n+\t\tu64 free7 : 1;\n+\t\tu64 free6 : 1;\n+\t\tu64 free5 : 1;\n+\t\tu64 free4 : 1;\n+\t\tu64 free3 : 1;\n+\t\tu64 free2 : 1;\n+\t\tu64 free1 : 1;\n+\t\tu64 free0 : 1;\n+\t\tu64 pool7th : 1;\n+\t\tu64 pool6th : 1;\n+\t\tu64 pool5th : 1;\n+\t\tu64 pool4th : 1;\n+\t\tu64 pool3th : 1;\n+\t\tu64 pool2th : 1;\n+\t\tu64 pool1th : 1;\n+\t\tu64 pool0th : 1;\n+\t\tu64 q7_perr : 1;\n+\t\tu64 q7_coff : 1;\n+\t\tu64 q7_und : 1;\n+\t\tu64 q6_perr : 1;\n+\t\tu64 q6_coff : 1;\n+\t\tu64 q6_und : 1;\n+\t\tu64 q5_perr : 1;\n+\t\tu64 q5_coff : 1;\n+\t\tu64 q5_und : 1;\n+\t\tu64 q4_perr : 1;\n+\t\tu64 q4_coff : 1;\n+\t\tu64 q4_und : 1;\n+\t\tu64 q3_perr : 1;\n+\t\tu64 q3_coff : 1;\n+\t\tu64 q3_und : 1;\n+\t\tu64 q2_perr : 1;\n+\t\tu64 q2_coff : 1;\n+\t\tu64 q2_und : 1;\n+\t\tu64 q1_perr : 1;\n+\t\tu64 q1_coff : 1;\n+\t\tu64 q1_und : 1;\n+\t\tu64 q0_perr : 1;\n+\t\tu64 q0_coff : 1;\n+\t\tu64 q0_und : 1;\n+\t\tu64 fed1_dbe : 1;\n+\t\tu64 fed1_sbe : 1;\n+\t\tu64 fed0_dbe : 1;\n+\t\tu64 fed0_sbe : 1;\n+\t} cn68xx;\n+\tstruct cvmx_fpa_int_enb_cn68xx cn68xxp1;\n+\tstruct cvmx_fpa_int_enb_cn61xx cn70xx;\n+\tstruct cvmx_fpa_int_enb_cn61xx cn70xxp1;\n+\tstruct cvmx_fpa_int_enb_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_fpa_int_enb cvmx_fpa_int_enb_t;\n+\n+/**\n+ * cvmx_fpa_int_sum\n+ *\n+ * Contains the different interrupt summary bits of the FPA.\n+ *\n+ */\n+union cvmx_fpa_int_sum {\n+\tu64 u64;\n+\tstruct cvmx_fpa_int_sum_s {\n+\t\tu64 reserved_50_63 : 14;\n+\t\tu64 paddr_e : 1;\n+\t\tu64 pool8th : 1;\n+\t\tu64 q8_perr : 1;\n+\t\tu64 q8_coff : 1;\n+\t\tu64 q8_und : 1;\n+\t\tu64 free8 : 1;\n+\t\tu64 free7 : 1;\n+\t\tu64 free6 : 1;\n+\t\tu64 free5 : 1;\n+\t\tu64 free4 : 1;\n+\t\tu64 free3 : 1;\n+\t\tu64 free2 : 1;\n+\t\tu64 free1 : 1;\n+\t\tu64 free0 : 1;\n+\t\tu64 pool7th : 1;\n+\t\tu64 pool6th : 1;\n+\t\tu64 pool5th : 1;\n+\t\tu64 pool4th : 1;\n+\t\tu64 pool3th : 1;\n+\t\tu64 pool2th : 1;\n+\t\tu64 pool1th : 1;\n+\t\tu64 pool0th : 1;\n+\t\tu64 q7_perr : 1;\n+\t\tu64 q7_coff : 1;\n+\t\tu64 q7_und : 1;\n+\t\tu64 q6_perr : 1;\n+\t\tu64 q6_coff : 1;\n+\t\tu64 q6_und : 1;\n+\t\tu64 q5_perr : 1;\n+\t\tu64 q5_coff : 1;\n+\t\tu64 q5_und : 1;\n+\t\tu64 q4_perr : 1;\n+\t\tu64 q4_coff : 1;\n+\t\tu64 q4_und : 1;\n+\t\tu64 q3_perr : 1;\n+\t\tu64 q3_coff : 1;\n+\t\tu64 q3_und : 1;\n+\t\tu64 q2_perr : 1;\n+\t\tu64 q2_coff : 1;\n+\t\tu64 q2_und : 1;\n+\t\tu64 q1_perr : 1;\n+\t\tu64 q1_coff : 1;\n+\t\tu64 q1_und : 1;\n+\t\tu64 q0_perr : 1;\n+\t\tu64 q0_coff : 1;\n+\t\tu64 q0_und : 1;\n+\t\tu64 fed1_dbe : 1;\n+\t\tu64 fed1_sbe : 1;\n+\t\tu64 fed0_dbe : 1;\n+\t\tu64 fed0_sbe : 1;\n+\t} s;\n+\tstruct cvmx_fpa_int_sum_cn30xx {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 q7_perr : 1;\n+\t\tu64 q7_coff : 1;\n+\t\tu64 q7_und : 1;\n+\t\tu64 q6_perr : 1;\n+\t\tu64 q6_coff : 1;\n+\t\tu64 q6_und : 1;\n+\t\tu64 q5_perr : 1;\n+\t\tu64 q5_coff : 1;\n+\t\tu64 q5_und : 1;\n+\t\tu64 q4_perr : 1;\n+\t\tu64 q4_coff : 1;\n+\t\tu64 q4_und : 1;\n+\t\tu64 q3_perr : 1;\n+\t\tu64 q3_coff : 1;\n+\t\tu64 q3_und : 1;\n+\t\tu64 q2_perr : 1;\n+\t\tu64 q2_coff : 1;\n+\t\tu64 q2_und : 1;\n+\t\tu64 q1_perr : 1;\n+\t\tu64 q1_coff : 1;\n+\t\tu64 q1_und : 1;\n+\t\tu64 q0_perr : 1;\n+\t\tu64 q0_coff : 1;\n+\t\tu64 q0_und : 1;\n+\t\tu64 fed1_dbe : 1;\n+\t\tu64 fed1_sbe : 1;\n+\t\tu64 fed0_dbe : 1;\n+\t\tu64 fed0_sbe : 1;\n+\t} cn30xx;\n+\tstruct cvmx_fpa_int_sum_cn30xx cn31xx;\n+\tstruct cvmx_fpa_int_sum_cn30xx cn38xx;\n+\tstruct cvmx_fpa_int_sum_cn30xx cn38xxp2;\n+\tstruct cvmx_fpa_int_sum_cn30xx cn50xx;\n+\tstruct cvmx_fpa_int_sum_cn30xx cn52xx;\n+\tstruct cvmx_fpa_int_sum_cn30xx cn52xxp1;\n+\tstruct cvmx_fpa_int_sum_cn30xx cn56xx;\n+\tstruct cvmx_fpa_int_sum_cn30xx cn56xxp1;\n+\tstruct cvmx_fpa_int_sum_cn30xx cn58xx;\n+\tstruct cvmx_fpa_int_sum_cn30xx cn58xxp1;\n+\tstruct cvmx_fpa_int_sum_cn61xx {\n+\t\tu64 reserved_50_63 : 14;\n+\t\tu64 paddr_e : 1;\n+\t\tu64 reserved_44_48 : 5;\n+\t\tu64 free7 : 1;\n+\t\tu64 free6 : 1;\n+\t\tu64 free5 : 1;\n+\t\tu64 free4 : 1;\n+\t\tu64 free3 : 1;\n+\t\tu64 free2 : 1;\n+\t\tu64 free1 : 1;\n+\t\tu64 free0 : 1;\n+\t\tu64 pool7th : 1;\n+\t\tu64 pool6th : 1;\n+\t\tu64 pool5th : 1;\n+\t\tu64 pool4th : 1;\n+\t\tu64 pool3th : 1;\n+\t\tu64 pool2th : 1;\n+\t\tu64 pool1th : 1;\n+\t\tu64 pool0th : 1;\n+\t\tu64 q7_perr : 1;\n+\t\tu64 q7_coff : 1;\n+\t\tu64 q7_und : 1;\n+\t\tu64 q6_perr : 1;\n+\t\tu64 q6_coff : 1;\n+\t\tu64 q6_und : 1;\n+\t\tu64 q5_perr : 1;\n+\t\tu64 q5_coff : 1;\n+\t\tu64 q5_und : 1;\n+\t\tu64 q4_perr : 1;\n+\t\tu64 q4_coff : 1;\n+\t\tu64 q4_und : 1;\n+\t\tu64 q3_perr : 1;\n+\t\tu64 q3_coff : 1;\n+\t\tu64 q3_und : 1;\n+\t\tu64 q2_perr : 1;\n+\t\tu64 q2_coff : 1;\n+\t\tu64 q2_und : 1;\n+\t\tu64 q1_perr : 1;\n+\t\tu64 q1_coff : 1;\n+\t\tu64 q1_und : 1;\n+\t\tu64 q0_perr : 1;\n+\t\tu64 q0_coff : 1;\n+\t\tu64 q0_und : 1;\n+\t\tu64 fed1_dbe : 1;\n+\t\tu64 fed1_sbe : 1;\n+\t\tu64 fed0_dbe : 1;\n+\t\tu64 fed0_sbe : 1;\n+\t} cn61xx;\n+\tstruct cvmx_fpa_int_sum_cn63xx {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 free7 : 1;\n+\t\tu64 free6 : 1;\n+\t\tu64 free5 : 1;\n+\t\tu64 free4 : 1;\n+\t\tu64 free3 : 1;\n+\t\tu64 free2 : 1;\n+\t\tu64 free1 : 1;\n+\t\tu64 free0 : 1;\n+\t\tu64 pool7th : 1;\n+\t\tu64 pool6th : 1;\n+\t\tu64 pool5th : 1;\n+\t\tu64 pool4th : 1;\n+\t\tu64 pool3th : 1;\n+\t\tu64 pool2th : 1;\n+\t\tu64 pool1th : 1;\n+\t\tu64 pool0th : 1;\n+\t\tu64 q7_perr : 1;\n+\t\tu64 q7_coff : 1;\n+\t\tu64 q7_und : 1;\n+\t\tu64 q6_perr : 1;\n+\t\tu64 q6_coff : 1;\n+\t\tu64 q6_und : 1;\n+\t\tu64 q5_perr : 1;\n+\t\tu64 q5_coff : 1;\n+\t\tu64 q5_und : 1;\n+\t\tu64 q4_perr : 1;\n+\t\tu64 q4_coff : 1;\n+\t\tu64 q4_und : 1;\n+\t\tu64 q3_perr : 1;\n+\t\tu64 q3_coff : 1;\n+\t\tu64 q3_und : 1;\n+\t\tu64 q2_perr : 1;\n+\t\tu64 q2_coff : 1;\n+\t\tu64 q2_und : 1;\n+\t\tu64 q1_perr : 1;\n+\t\tu64 q1_coff : 1;\n+\t\tu64 q1_und : 1;\n+\t\tu64 q0_perr : 1;\n+\t\tu64 q0_coff : 1;\n+\t\tu64 q0_und : 1;\n+\t\tu64 fed1_dbe : 1;\n+\t\tu64 fed1_sbe : 1;\n+\t\tu64 fed0_dbe : 1;\n+\t\tu64 fed0_sbe : 1;\n+\t} cn63xx;\n+\tstruct cvmx_fpa_int_sum_cn30xx cn63xxp1;\n+\tstruct cvmx_fpa_int_sum_cn61xx cn66xx;\n+\tstruct cvmx_fpa_int_sum_s cn68xx;\n+\tstruct cvmx_fpa_int_sum_s cn68xxp1;\n+\tstruct cvmx_fpa_int_sum_cn61xx cn70xx;\n+\tstruct cvmx_fpa_int_sum_cn61xx cn70xxp1;\n+\tstruct cvmx_fpa_int_sum_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_fpa_int_sum cvmx_fpa_int_sum_t;\n+\n+/**\n+ * cvmx_fpa_packet_threshold\n+ *\n+ * When the value of FPA_QUE0_AVAILABLE[QUE_SIZ] is Less than the value of this register a low\n+ * pool count signal is sent to the\n+ * PCIe packet instruction engine (to make it stop reading instructions) and to the Packet-\n+ * Arbiter informing it to not give grants\n+ * to packets MAC with the exception of the PCIe MAC.\n+ */\n+union cvmx_fpa_packet_threshold {\n+\tu64 u64;\n+\tstruct cvmx_fpa_packet_threshold_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 thresh : 32;\n+\t} s;\n+\tstruct cvmx_fpa_packet_threshold_s cn61xx;\n+\tstruct cvmx_fpa_packet_threshold_s cn63xx;\n+\tstruct cvmx_fpa_packet_threshold_s cn66xx;\n+\tstruct cvmx_fpa_packet_threshold_s cn68xx;\n+\tstruct cvmx_fpa_packet_threshold_s cn68xxp1;\n+\tstruct cvmx_fpa_packet_threshold_s cn70xx;\n+\tstruct cvmx_fpa_packet_threshold_s cn70xxp1;\n+\tstruct cvmx_fpa_packet_threshold_s cnf71xx;\n+};\n+\n+typedef union cvmx_fpa_packet_threshold cvmx_fpa_packet_threshold_t;\n+\n+/**\n+ * cvmx_fpa_pool#_available\n+ */\n+union cvmx_fpa_poolx_available {\n+\tu64 u64;\n+\tstruct cvmx_fpa_poolx_available_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 count : 36;\n+\t} s;\n+\tstruct cvmx_fpa_poolx_available_s cn73xx;\n+\tstruct cvmx_fpa_poolx_available_s cn78xx;\n+\tstruct cvmx_fpa_poolx_available_s cn78xxp1;\n+\tstruct cvmx_fpa_poolx_available_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_poolx_available cvmx_fpa_poolx_available_t;\n+\n+/**\n+ * cvmx_fpa_pool#_cfg\n+ */\n+union cvmx_fpa_poolx_cfg {\n+\tu64 u64;\n+\tstruct cvmx_fpa_poolx_cfg_s {\n+\t\tu64 reserved_43_63 : 21;\n+\t\tu64 buf_size : 11;\n+\t\tu64 reserved_31_31 : 1;\n+\t\tu64 buf_offset : 15;\n+\t\tu64 reserved_5_15 : 11;\n+\t\tu64 l_type : 2;\n+\t\tu64 s_type : 1;\n+\t\tu64 nat_align : 1;\n+\t\tu64 ena : 1;\n+\t} s;\n+\tstruct cvmx_fpa_poolx_cfg_s cn73xx;\n+\tstruct cvmx_fpa_poolx_cfg_s cn78xx;\n+\tstruct cvmx_fpa_poolx_cfg_s cn78xxp1;\n+\tstruct cvmx_fpa_poolx_cfg_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_poolx_cfg cvmx_fpa_poolx_cfg_t;\n+\n+/**\n+ * cvmx_fpa_pool#_end_addr\n+ *\n+ * Pointers sent to this pool after alignment must be equal to or less than this address.\n+ *\n+ */\n+union cvmx_fpa_poolx_end_addr {\n+\tu64 u64;\n+\tstruct cvmx_fpa_poolx_end_addr_s {\n+\t\tu64 reserved_0_63 : 64;\n+\t} s;\n+\tstruct cvmx_fpa_poolx_end_addr_cn61xx {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 addr : 33;\n+\t} cn61xx;\n+\tstruct cvmx_fpa_poolx_end_addr_cn61xx cn66xx;\n+\tstruct cvmx_fpa_poolx_end_addr_cn61xx cn68xx;\n+\tstruct cvmx_fpa_poolx_end_addr_cn61xx cn68xxp1;\n+\tstruct cvmx_fpa_poolx_end_addr_cn61xx cn70xx;\n+\tstruct cvmx_fpa_poolx_end_addr_cn61xx cn70xxp1;\n+\tstruct cvmx_fpa_poolx_end_addr_cn73xx {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 addr : 35;\n+\t\tu64 reserved_0_6 : 7;\n+\t} cn73xx;\n+\tstruct cvmx_fpa_poolx_end_addr_cn73xx cn78xx;\n+\tstruct cvmx_fpa_poolx_end_addr_cn73xx cn78xxp1;\n+\tstruct cvmx_fpa_poolx_end_addr_cn61xx cnf71xx;\n+\tstruct cvmx_fpa_poolx_end_addr_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_poolx_end_addr cvmx_fpa_poolx_end_addr_t;\n+\n+/**\n+ * cvmx_fpa_pool#_fpf_marks\n+ *\n+ * The low watermark register that determines when we read free pages from L2C.\n+ *\n+ */\n+union cvmx_fpa_poolx_fpf_marks {\n+\tu64 u64;\n+\tstruct cvmx_fpa_poolx_fpf_marks_s {\n+\t\tu64 reserved_27_63 : 37;\n+\t\tu64 fpf_rd : 11;\n+\t\tu64 reserved_11_15 : 5;\n+\t\tu64 fpf_level : 11;\n+\t} s;\n+\tstruct cvmx_fpa_poolx_fpf_marks_s cn73xx;\n+\tstruct cvmx_fpa_poolx_fpf_marks_s cn78xx;\n+\tstruct cvmx_fpa_poolx_fpf_marks_s cn78xxp1;\n+\tstruct cvmx_fpa_poolx_fpf_marks_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_poolx_fpf_marks cvmx_fpa_poolx_fpf_marks_t;\n+\n+/**\n+ * cvmx_fpa_pool#_int\n+ *\n+ * This register indicates pool interrupts.\n+ *\n+ */\n+union cvmx_fpa_poolx_int {\n+\tu64 u64;\n+\tstruct cvmx_fpa_poolx_int_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 thresh : 1;\n+\t\tu64 range : 1;\n+\t\tu64 crcerr : 1;\n+\t\tu64 ovfls : 1;\n+\t} s;\n+\tstruct cvmx_fpa_poolx_int_s cn73xx;\n+\tstruct cvmx_fpa_poolx_int_s cn78xx;\n+\tstruct cvmx_fpa_poolx_int_s cn78xxp1;\n+\tstruct cvmx_fpa_poolx_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_poolx_int cvmx_fpa_poolx_int_t;\n+\n+/**\n+ * cvmx_fpa_pool#_op_pc\n+ */\n+union cvmx_fpa_poolx_op_pc {\n+\tu64 u64;\n+\tstruct cvmx_fpa_poolx_op_pc_s {\n+\t\tu64 count : 64;\n+\t} s;\n+\tstruct cvmx_fpa_poolx_op_pc_s cn73xx;\n+\tstruct cvmx_fpa_poolx_op_pc_s cn78xx;\n+\tstruct cvmx_fpa_poolx_op_pc_s cn78xxp1;\n+\tstruct cvmx_fpa_poolx_op_pc_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_poolx_op_pc cvmx_fpa_poolx_op_pc_t;\n+\n+/**\n+ * cvmx_fpa_pool#_stack_addr\n+ */\n+union cvmx_fpa_poolx_stack_addr {\n+\tu64 u64;\n+\tstruct cvmx_fpa_poolx_stack_addr_s {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 addr : 35;\n+\t\tu64 reserved_0_6 : 7;\n+\t} s;\n+\tstruct cvmx_fpa_poolx_stack_addr_s cn73xx;\n+\tstruct cvmx_fpa_poolx_stack_addr_s cn78xx;\n+\tstruct cvmx_fpa_poolx_stack_addr_s cn78xxp1;\n+\tstruct cvmx_fpa_poolx_stack_addr_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_poolx_stack_addr cvmx_fpa_poolx_stack_addr_t;\n+\n+/**\n+ * cvmx_fpa_pool#_stack_base\n+ */\n+union cvmx_fpa_poolx_stack_base {\n+\tu64 u64;\n+\tstruct cvmx_fpa_poolx_stack_base_s {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 addr : 35;\n+\t\tu64 reserved_0_6 : 7;\n+\t} s;\n+\tstruct cvmx_fpa_poolx_stack_base_s cn73xx;\n+\tstruct cvmx_fpa_poolx_stack_base_s cn78xx;\n+\tstruct cvmx_fpa_poolx_stack_base_s cn78xxp1;\n+\tstruct cvmx_fpa_poolx_stack_base_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_poolx_stack_base cvmx_fpa_poolx_stack_base_t;\n+\n+/**\n+ * cvmx_fpa_pool#_stack_end\n+ */\n+union cvmx_fpa_poolx_stack_end {\n+\tu64 u64;\n+\tstruct cvmx_fpa_poolx_stack_end_s {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 addr : 35;\n+\t\tu64 reserved_0_6 : 7;\n+\t} s;\n+\tstruct cvmx_fpa_poolx_stack_end_s cn73xx;\n+\tstruct cvmx_fpa_poolx_stack_end_s cn78xx;\n+\tstruct cvmx_fpa_poolx_stack_end_s cn78xxp1;\n+\tstruct cvmx_fpa_poolx_stack_end_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_poolx_stack_end cvmx_fpa_poolx_stack_end_t;\n+\n+/**\n+ * cvmx_fpa_pool#_start_addr\n+ *\n+ * Pointers sent to this pool after alignment must be equal to or greater than this address.\n+ *\n+ */\n+union cvmx_fpa_poolx_start_addr {\n+\tu64 u64;\n+\tstruct cvmx_fpa_poolx_start_addr_s {\n+\t\tu64 reserved_0_63 : 64;\n+\t} s;\n+\tstruct cvmx_fpa_poolx_start_addr_cn61xx {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 addr : 33;\n+\t} cn61xx;\n+\tstruct cvmx_fpa_poolx_start_addr_cn61xx cn66xx;\n+\tstruct cvmx_fpa_poolx_start_addr_cn61xx cn68xx;\n+\tstruct cvmx_fpa_poolx_start_addr_cn61xx cn68xxp1;\n+\tstruct cvmx_fpa_poolx_start_addr_cn61xx cn70xx;\n+\tstruct cvmx_fpa_poolx_start_addr_cn61xx cn70xxp1;\n+\tstruct cvmx_fpa_poolx_start_addr_cn73xx {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 addr : 35;\n+\t\tu64 reserved_0_6 : 7;\n+\t} cn73xx;\n+\tstruct cvmx_fpa_poolx_start_addr_cn73xx cn78xx;\n+\tstruct cvmx_fpa_poolx_start_addr_cn73xx cn78xxp1;\n+\tstruct cvmx_fpa_poolx_start_addr_cn61xx cnf71xx;\n+\tstruct cvmx_fpa_poolx_start_addr_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_poolx_start_addr cvmx_fpa_poolx_start_addr_t;\n+\n+/**\n+ * cvmx_fpa_pool#_threshold\n+ *\n+ * FPA_POOLX_THRESHOLD = FPA's Pool 0-7 Threshold\n+ * When the value of FPA_QUEX_AVAILABLE is equal to FPA_POOLX_THRESHOLD[THRESH] when a pointer is\n+ * allocated\n+ * or deallocated, set interrupt FPA_INT_SUM[POOLXTH].\n+ */\n+union cvmx_fpa_poolx_threshold {\n+\tu64 u64;\n+\tstruct cvmx_fpa_poolx_threshold_s {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 thresh : 36;\n+\t} s;\n+\tstruct cvmx_fpa_poolx_threshold_cn61xx {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 thresh : 29;\n+\t} cn61xx;\n+\tstruct cvmx_fpa_poolx_threshold_cn61xx cn63xx;\n+\tstruct cvmx_fpa_poolx_threshold_cn61xx cn66xx;\n+\tstruct cvmx_fpa_poolx_threshold_cn68xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 thresh : 32;\n+\t} cn68xx;\n+\tstruct cvmx_fpa_poolx_threshold_cn68xx cn68xxp1;\n+\tstruct cvmx_fpa_poolx_threshold_cn61xx cn70xx;\n+\tstruct cvmx_fpa_poolx_threshold_cn61xx cn70xxp1;\n+\tstruct cvmx_fpa_poolx_threshold_s cn73xx;\n+\tstruct cvmx_fpa_poolx_threshold_s cn78xx;\n+\tstruct cvmx_fpa_poolx_threshold_s cn78xxp1;\n+\tstruct cvmx_fpa_poolx_threshold_cn61xx cnf71xx;\n+\tstruct cvmx_fpa_poolx_threshold_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_poolx_threshold cvmx_fpa_poolx_threshold_t;\n+\n+/**\n+ * cvmx_fpa_que#_available\n+ *\n+ * FPA_QUEX_PAGES_AVAILABLE = FPA's Queue 0-7 Free Page Available Register\n+ * The number of page pointers that are available in the FPA and local DRAM.\n+ */\n+union cvmx_fpa_quex_available {\n+\tu64 u64;\n+\tstruct cvmx_fpa_quex_available_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 que_siz : 32;\n+\t} s;\n+\tstruct cvmx_fpa_quex_available_cn30xx {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 que_siz : 29;\n+\t} cn30xx;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn31xx;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn38xx;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn38xxp2;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn50xx;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn52xx;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn52xxp1;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn56xx;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn56xxp1;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn58xx;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn58xxp1;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn61xx;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn63xx;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn63xxp1;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn66xx;\n+\tstruct cvmx_fpa_quex_available_s cn68xx;\n+\tstruct cvmx_fpa_quex_available_s cn68xxp1;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn70xx;\n+\tstruct cvmx_fpa_quex_available_cn30xx cn70xxp1;\n+\tstruct cvmx_fpa_quex_available_cn30xx cnf71xx;\n+};\n+\n+typedef union cvmx_fpa_quex_available cvmx_fpa_quex_available_t;\n+\n+/**\n+ * cvmx_fpa_que#_page_index\n+ *\n+ * The present index page for queue 0 of the FPA.\n+ * This number reflects the number of pages of pointers that have been written to memory\n+ * for this queue.\n+ */\n+union cvmx_fpa_quex_page_index {\n+\tu64 u64;\n+\tstruct cvmx_fpa_quex_page_index_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 pg_num : 25;\n+\t} s;\n+\tstruct cvmx_fpa_quex_page_index_s cn30xx;\n+\tstruct cvmx_fpa_quex_page_index_s cn31xx;\n+\tstruct cvmx_fpa_quex_page_index_s cn38xx;\n+\tstruct cvmx_fpa_quex_page_index_s cn38xxp2;\n+\tstruct cvmx_fpa_quex_page_index_s cn50xx;\n+\tstruct cvmx_fpa_quex_page_index_s cn52xx;\n+\tstruct cvmx_fpa_quex_page_index_s cn52xxp1;\n+\tstruct cvmx_fpa_quex_page_index_s cn56xx;\n+\tstruct cvmx_fpa_quex_page_index_s cn56xxp1;\n+\tstruct cvmx_fpa_quex_page_index_s cn58xx;\n+\tstruct cvmx_fpa_quex_page_index_s cn58xxp1;\n+\tstruct cvmx_fpa_quex_page_index_s cn61xx;\n+\tstruct cvmx_fpa_quex_page_index_s cn63xx;\n+\tstruct cvmx_fpa_quex_page_index_s cn63xxp1;\n+\tstruct cvmx_fpa_quex_page_index_s cn66xx;\n+\tstruct cvmx_fpa_quex_page_index_s cn68xx;\n+\tstruct cvmx_fpa_quex_page_index_s cn68xxp1;\n+\tstruct cvmx_fpa_quex_page_index_s cn70xx;\n+\tstruct cvmx_fpa_quex_page_index_s cn70xxp1;\n+\tstruct cvmx_fpa_quex_page_index_s cnf71xx;\n+};\n+\n+typedef union cvmx_fpa_quex_page_index cvmx_fpa_quex_page_index_t;\n+\n+/**\n+ * cvmx_fpa_que8_page_index\n+ *\n+ * FPA_QUE8_PAGE_INDEX = FPA's Queue7 Page Index\n+ *\n+ * The present index page for queue 7 of the FPA.\n+ * This number reflects the number of pages of pointers that have been written to memory\n+ * for this queue.\n+ * Because the address space is 38-bits the number of 128 byte pages could cause this register value to wrap.\n+ */\n+union cvmx_fpa_que8_page_index {\n+\tu64 u64;\n+\tstruct cvmx_fpa_que8_page_index_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 pg_num : 25;\n+\t} s;\n+\tstruct cvmx_fpa_que8_page_index_s cn68xx;\n+\tstruct cvmx_fpa_que8_page_index_s cn68xxp1;\n+};\n+\n+typedef union cvmx_fpa_que8_page_index cvmx_fpa_que8_page_index_t;\n+\n+/**\n+ * cvmx_fpa_que_act\n+ *\n+ * \"When a INT_SUM[PERR#] occurs this will be latched with the value read from L2C.\n+ * This is latched on the first error and will not latch again unitl all errors are cleared.\"\n+ */\n+union cvmx_fpa_que_act {\n+\tu64 u64;\n+\tstruct cvmx_fpa_que_act_s {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 act_que : 3;\n+\t\tu64 act_indx : 26;\n+\t} s;\n+\tstruct cvmx_fpa_que_act_s cn30xx;\n+\tstruct cvmx_fpa_que_act_s cn31xx;\n+\tstruct cvmx_fpa_que_act_s cn38xx;\n+\tstruct cvmx_fpa_que_act_s cn38xxp2;\n+\tstruct cvmx_fpa_que_act_s cn50xx;\n+\tstruct cvmx_fpa_que_act_s cn52xx;\n+\tstruct cvmx_fpa_que_act_s cn52xxp1;\n+\tstruct cvmx_fpa_que_act_s cn56xx;\n+\tstruct cvmx_fpa_que_act_s cn56xxp1;\n+\tstruct cvmx_fpa_que_act_s cn58xx;\n+\tstruct cvmx_fpa_que_act_s cn58xxp1;\n+\tstruct cvmx_fpa_que_act_s cn61xx;\n+\tstruct cvmx_fpa_que_act_s cn63xx;\n+\tstruct cvmx_fpa_que_act_s cn63xxp1;\n+\tstruct cvmx_fpa_que_act_s cn66xx;\n+\tstruct cvmx_fpa_que_act_s cn68xx;\n+\tstruct cvmx_fpa_que_act_s cn68xxp1;\n+\tstruct cvmx_fpa_que_act_s cn70xx;\n+\tstruct cvmx_fpa_que_act_s cn70xxp1;\n+\tstruct cvmx_fpa_que_act_s cnf71xx;\n+};\n+\n+typedef union cvmx_fpa_que_act cvmx_fpa_que_act_t;\n+\n+/**\n+ * cvmx_fpa_que_exp\n+ *\n+ * \"When a INT_SUM[PERR#] occurs this will be latched with the expected value.\n+ * This is latched on the first error and will not latch again unitl all errors are cleared.\"\n+ */\n+union cvmx_fpa_que_exp {\n+\tu64 u64;\n+\tstruct cvmx_fpa_que_exp_s {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 exp_que : 3;\n+\t\tu64 exp_indx : 26;\n+\t} s;\n+\tstruct cvmx_fpa_que_exp_s cn30xx;\n+\tstruct cvmx_fpa_que_exp_s cn31xx;\n+\tstruct cvmx_fpa_que_exp_s cn38xx;\n+\tstruct cvmx_fpa_que_exp_s cn38xxp2;\n+\tstruct cvmx_fpa_que_exp_s cn50xx;\n+\tstruct cvmx_fpa_que_exp_s cn52xx;\n+\tstruct cvmx_fpa_que_exp_s cn52xxp1;\n+\tstruct cvmx_fpa_que_exp_s cn56xx;\n+\tstruct cvmx_fpa_que_exp_s cn56xxp1;\n+\tstruct cvmx_fpa_que_exp_s cn58xx;\n+\tstruct cvmx_fpa_que_exp_s cn58xxp1;\n+\tstruct cvmx_fpa_que_exp_s cn61xx;\n+\tstruct cvmx_fpa_que_exp_s cn63xx;\n+\tstruct cvmx_fpa_que_exp_s cn63xxp1;\n+\tstruct cvmx_fpa_que_exp_s cn66xx;\n+\tstruct cvmx_fpa_que_exp_s cn68xx;\n+\tstruct cvmx_fpa_que_exp_s cn68xxp1;\n+\tstruct cvmx_fpa_que_exp_s cn70xx;\n+\tstruct cvmx_fpa_que_exp_s cn70xxp1;\n+\tstruct cvmx_fpa_que_exp_s cnf71xx;\n+};\n+\n+typedef union cvmx_fpa_que_exp cvmx_fpa_que_exp_t;\n+\n+/**\n+ * cvmx_fpa_rd_latency_pc\n+ */\n+union cvmx_fpa_rd_latency_pc {\n+\tu64 u64;\n+\tstruct cvmx_fpa_rd_latency_pc_s {\n+\t\tu64 count : 64;\n+\t} s;\n+\tstruct cvmx_fpa_rd_latency_pc_s cn73xx;\n+\tstruct cvmx_fpa_rd_latency_pc_s cn78xx;\n+\tstruct cvmx_fpa_rd_latency_pc_s cn78xxp1;\n+\tstruct cvmx_fpa_rd_latency_pc_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_rd_latency_pc cvmx_fpa_rd_latency_pc_t;\n+\n+/**\n+ * cvmx_fpa_rd_req_pc\n+ */\n+union cvmx_fpa_rd_req_pc {\n+\tu64 u64;\n+\tstruct cvmx_fpa_rd_req_pc_s {\n+\t\tu64 count : 64;\n+\t} s;\n+\tstruct cvmx_fpa_rd_req_pc_s cn73xx;\n+\tstruct cvmx_fpa_rd_req_pc_s cn78xx;\n+\tstruct cvmx_fpa_rd_req_pc_s cn78xxp1;\n+\tstruct cvmx_fpa_rd_req_pc_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_rd_req_pc cvmx_fpa_rd_req_pc_t;\n+\n+/**\n+ * cvmx_fpa_red_delay\n+ */\n+union cvmx_fpa_red_delay {\n+\tu64 u64;\n+\tstruct cvmx_fpa_red_delay_s {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 avg_dly : 14;\n+\t} s;\n+\tstruct cvmx_fpa_red_delay_s cn73xx;\n+\tstruct cvmx_fpa_red_delay_s cn78xx;\n+\tstruct cvmx_fpa_red_delay_s cn78xxp1;\n+\tstruct cvmx_fpa_red_delay_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_red_delay cvmx_fpa_red_delay_t;\n+\n+/**\n+ * cvmx_fpa_sft_rst\n+ *\n+ * Allows soft reset.\n+ *\n+ */\n+union cvmx_fpa_sft_rst {\n+\tu64 u64;\n+\tstruct cvmx_fpa_sft_rst_s {\n+\t\tu64 busy : 1;\n+\t\tu64 reserved_1_62 : 62;\n+\t\tu64 rst : 1;\n+\t} s;\n+\tstruct cvmx_fpa_sft_rst_s cn73xx;\n+\tstruct cvmx_fpa_sft_rst_s cn78xx;\n+\tstruct cvmx_fpa_sft_rst_s cn78xxp1;\n+\tstruct cvmx_fpa_sft_rst_s cnf75xx;\n+};\n+\n+typedef union cvmx_fpa_sft_rst cvmx_fpa_sft_rst_t;\n+\n+/**\n+ * cvmx_fpa_wart_ctl\n+ *\n+ * FPA_WART_CTL = FPA's WART Control\n+ *\n+ * Control and status for the WART block.\n+ */\n+union cvmx_fpa_wart_ctl {\n+\tu64 u64;\n+\tstruct cvmx_fpa_wart_ctl_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 ctl : 16;\n+\t} s;\n+\tstruct cvmx_fpa_wart_ctl_s cn30xx;\n+\tstruct cvmx_fpa_wart_ctl_s cn31xx;\n+\tstruct cvmx_fpa_wart_ctl_s cn38xx;\n+\tstruct cvmx_fpa_wart_ctl_s cn38xxp2;\n+\tstruct cvmx_fpa_wart_ctl_s cn50xx;\n+\tstruct cvmx_fpa_wart_ctl_s cn52xx;\n+\tstruct cvmx_fpa_wart_ctl_s cn52xxp1;\n+\tstruct cvmx_fpa_wart_ctl_s cn56xx;\n+\tstruct cvmx_fpa_wart_ctl_s cn56xxp1;\n+\tstruct cvmx_fpa_wart_ctl_s cn58xx;\n+\tstruct cvmx_fpa_wart_ctl_s cn58xxp1;\n+};\n+\n+typedef union cvmx_fpa_wart_ctl cvmx_fpa_wart_ctl_t;\n+\n+/**\n+ * cvmx_fpa_wart_status\n+ *\n+ * FPA_WART_STATUS = FPA's WART Status\n+ *\n+ * Control and status for the WART block.\n+ */\n+union cvmx_fpa_wart_status {\n+\tu64 u64;\n+\tstruct cvmx_fpa_wart_status_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 status : 32;\n+\t} s;\n+\tstruct cvmx_fpa_wart_status_s cn30xx;\n+\tstruct cvmx_fpa_wart_status_s cn31xx;\n+\tstruct cvmx_fpa_wart_status_s cn38xx;\n+\tstruct cvmx_fpa_wart_status_s cn38xxp2;\n+\tstruct cvmx_fpa_wart_status_s cn50xx;\n+\tstruct cvmx_fpa_wart_status_s cn52xx;\n+\tstruct cvmx_fpa_wart_status_s cn52xxp1;\n+\tstruct cvmx_fpa_wart_status_s cn56xx;\n+\tstruct cvmx_fpa_wart_status_s cn56xxp1;\n+\tstruct cvmx_fpa_wart_status_s cn58xx;\n+\tstruct cvmx_fpa_wart_status_s cn58xxp1;\n+};\n+\n+typedef union cvmx_fpa_wart_status cvmx_fpa_wart_status_t;\n+\n+/**\n+ * cvmx_fpa_wqe_threshold\n+ *\n+ * \"When the value of FPA_QUE#_AVAILABLE[QUE_SIZ] (\\# is determined by the value of\n+ * IPD_WQE_FPA_QUEUE) is Less than the value of this\n+ * register a low pool count signal is sent to the PCIe packet instruction engine (to make it\n+ * stop reading instructions) and to the\n+ * Packet-Arbiter informing it to not give grants to packets MAC with the exception of the PCIe\n+ * MAC.\"\n+ */\n+union cvmx_fpa_wqe_threshold {\n+\tu64 u64;\n+\tstruct cvmx_fpa_wqe_threshold_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 thresh : 32;\n+\t} s;\n+\tstruct cvmx_fpa_wqe_threshold_s cn61xx;\n+\tstruct cvmx_fpa_wqe_threshold_s cn63xx;\n+\tstruct cvmx_fpa_wqe_threshold_s cn66xx;\n+\tstruct cvmx_fpa_wqe_threshold_s cn68xx;\n+\tstruct cvmx_fpa_wqe_threshold_s cn68xxp1;\n+\tstruct cvmx_fpa_wqe_threshold_s cn70xx;\n+\tstruct cvmx_fpa_wqe_threshold_s cn70xxp1;\n+\tstruct cvmx_fpa_wqe_threshold_s cnf71xx;\n+};\n+\n+typedef union cvmx_fpa_wqe_threshold cvmx_fpa_wqe_threshold_t;\n+\n+#endif\n",
    "prefixes": [
        "v1",
        "10/50"
    ]
}