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{
    "id": 1414988,
    "url": "http://patchwork.ozlabs.org/api/patches/1414988/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-9-sr@denx.de/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
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        "list_archive_url": "",
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    },
    "msgid": "<20201211160612.1498780-9-sr@denx.de>",
    "list_archive_url": null,
    "date": "2020-12-11T16:05:30",
    "name": "[v1,08/50] mips: octeon: Add cvmx-dpi-defs.h header file",
    "commit_ref": "c5b1b18e4dcfabe0b723d0eae61ff982de53cabe",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "539ab12238e2d1c4893936df2fbe6068e9e1dea1",
    "submitter": {
        "id": 13,
        "url": "http://patchwork.ozlabs.org/api/people/13/?format=api",
        "name": "Stefan Roese",
        "email": "sr@denx.de"
    },
    "delegate": {
        "id": 4307,
        "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api",
        "username": "danielschwierzeck",
        "first_name": "Daniel",
        "last_name": "Schwierzeck",
        "email": "daniel.schwierzeck@googlemail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-9-sr@denx.de/mbox/",
    "series": [
        {
            "id": 220054,
            "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054",
            "date": "2020-12-11T16:05:23",
            "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1414988/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1414988/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Stefan Roese <sr@denx.de>",
        "To": "u-boot@lists.denx.de",
        "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com",
        "Subject": "[PATCH v1 08/50] mips: octeon: Add cvmx-dpi-defs.h header file",
        "Date": "Fri, 11 Dec 2020 17:05:30 +0100",
        "Message-Id": "<20201211160612.1498780-9-sr@denx.de>",
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    "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-dpi-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-dpi-defs.h  | 1460 +++++++++++++++++\n 1 file changed, 1460 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-dpi-defs.h",
    "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-dpi-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-dpi-defs.h\nnew file mode 100644\nindex 0000000000..680989463b\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-dpi-defs.h\n@@ -0,0 +1,1460 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon dpi.\n+ */\n+\n+#ifndef __CVMX_DPI_DEFS_H__\n+#define __CVMX_DPI_DEFS_H__\n+\n+#define CVMX_DPI_BIST_STATUS\t\t     (0x0001DF0000000000ull)\n+#define CVMX_DPI_CTL\t\t\t     (0x0001DF0000000040ull)\n+#define CVMX_DPI_DMAX_COUNTS(offset)\t     (0x0001DF0000000300ull + ((offset) & 7) * 8)\n+#define CVMX_DPI_DMAX_DBELL(offset)\t     (0x0001DF0000000200ull + ((offset) & 7) * 8)\n+#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (0x0001DF0000000A80ull + ((offset) & 7) * 8)\n+#define CVMX_DPI_DMAX_IBUFF_SADDR(offset)    (0x0001DF0000000280ull + ((offset) & 7) * 8)\n+#define CVMX_DPI_DMAX_IFLIGHT(offset)\t     (0x0001DF0000000A00ull + ((offset) & 7) * 8)\n+#define CVMX_DPI_DMAX_NADDR(offset)\t     (0x0001DF0000000380ull + ((offset) & 7) * 8)\n+#define CVMX_DPI_DMAX_REQBNK0(offset)\t     (0x0001DF0000000400ull + ((offset) & 7) * 8)\n+#define CVMX_DPI_DMAX_REQBNK1(offset)\t     (0x0001DF0000000480ull + ((offset) & 7) * 8)\n+#define CVMX_DPI_DMAX_REQQ_CTL(offset)\t     (0x0001DF0000000180ull + ((offset) & 7) * 8)\n+#define CVMX_DPI_DMA_CONTROL\t\t     (0x0001DF0000000048ull)\n+#define CVMX_DPI_DMA_ENGX_EN(offset)\t     (0x0001DF0000000080ull + ((offset) & 7) * 8)\n+static inline u64 CVMX_DPI_DMA_PPX_CNT(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001DF0000000B00ull + (offset) * 8;\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001DF0000000B00ull + (offset) * 8;\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001DF0000000C00ull + (offset) * 8;\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0001DF0000000C00ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0001DF0000000C00ull + (offset) * 8;\n+\t}\n+\treturn 0x0001DF0000000C00ull + (offset) * 8;\n+}\n+\n+#define CVMX_DPI_DMA_PP_INT\t      (0x0001DF0000000038ull)\n+#define CVMX_DPI_ECC_CTL\t      (0x0001DF0000000018ull)\n+#define CVMX_DPI_ECC_INT\t      (0x0001DF0000000020ull)\n+#define CVMX_DPI_ENGX_BUF(offset)     (0x0001DF0000000880ull + ((offset) & 7) * 8)\n+#define CVMX_DPI_INFO_REG\t      (0x0001DF0000000980ull)\n+#define CVMX_DPI_INT_EN\t\t      (0x0001DF0000000010ull)\n+#define CVMX_DPI_INT_REG\t      (0x0001DF0000000008ull)\n+#define CVMX_DPI_NCBX_CFG(offset)     (0x0001DF0000000800ull)\n+#define CVMX_DPI_NCB_CTL\t      (0x0001DF0000000028ull)\n+#define CVMX_DPI_PINT_INFO\t      (0x0001DF0000000830ull)\n+#define CVMX_DPI_PKT_ERR_RSP\t      (0x0001DF0000000078ull)\n+#define CVMX_DPI_REQ_ERR_RSP\t      (0x0001DF0000000058ull)\n+#define CVMX_DPI_REQ_ERR_RSP_EN\t      (0x0001DF0000000068ull)\n+#define CVMX_DPI_REQ_ERR_RST\t      (0x0001DF0000000060ull)\n+#define CVMX_DPI_REQ_ERR_RST_EN\t      (0x0001DF0000000070ull)\n+#define CVMX_DPI_REQ_ERR_SKIP_COMP    (0x0001DF0000000838ull)\n+#define CVMX_DPI_REQ_GBL_EN\t      (0x0001DF0000000050ull)\n+#define CVMX_DPI_SLI_PRTX_CFG(offset) (0x0001DF0000000900ull + ((offset) & 3) * 8)\n+static inline u64 CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)\n+{\n+\tswitch (cvmx_get_octeon_family()) {\n+\tcase OCTEON_CNF75XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN66XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN73XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN78XX & OCTEON_FAMILY_MASK:\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))\n+\t\t\treturn 0x0001DF0000000920ull + (offset) * 8;\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN78XX))\n+\t\t\treturn 0x0001DF0000000920ull + (offset) * 8;\n+\t\treturn 0x0001DF0000000920ull + (offset) * 8;\n+\tcase OCTEON_CNF71XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN61XX & OCTEON_FAMILY_MASK:\n+\tcase OCTEON_CN68XX & OCTEON_FAMILY_MASK:\n+\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))\n+\t\t\treturn 0x0001DF0000000928ull + (offset) * 8;\n+\n+\t\tif (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))\n+\t\t\treturn 0x0001DF0000000920ull + (offset) * 8;\n+\t\treturn 0x0001DF0000000920ull + (offset) * 8;\n+\tcase OCTEON_CN70XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001DF0000000920ull + (offset) * 8;\n+\tcase OCTEON_CN63XX & OCTEON_FAMILY_MASK:\n+\t\treturn 0x0001DF0000000928ull + (offset) * 8;\n+\t}\n+\treturn 0x0001DF0000000920ull + (offset) * 8;\n+}\n+\n+#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (0x0001DF0000000940ull + ((offset) & 3) * 8)\n+#define CVMX_DPI_SRIO_RX_BELLX(offset)\t   (0x0001DF0000080200ull + ((offset) & 31) * 8)\n+#define CVMX_DPI_SRIO_RX_BELL_SEQX(offset) (0x0001DF0000080400ull + ((offset) & 31) * 8)\n+#define CVMX_DPI_SWA_Q_VMID\t\t   (0x0001DF0000000030ull)\n+\n+/**\n+ * cvmx_dpi_bist_status\n+ *\n+ * This is the built-in self-test (BIST) status register. Each bit is the BIST result of an\n+ * individual memory (per bit, 0 = pass and 1 = fail).\n+ */\n+union cvmx_dpi_bist_status {\n+\tu64 u64;\n+\tstruct cvmx_dpi_bist_status_s {\n+\t\tu64 reserved_57_63 : 7;\n+\t\tu64 bist : 57;\n+\t} s;\n+\tstruct cvmx_dpi_bist_status_cn61xx {\n+\t\tu64 reserved_47_63 : 17;\n+\t\tu64 bist : 47;\n+\t} cn61xx;\n+\tstruct cvmx_dpi_bist_status_cn63xx {\n+\t\tu64 reserved_45_63 : 19;\n+\t\tu64 bist : 45;\n+\t} cn63xx;\n+\tstruct cvmx_dpi_bist_status_cn63xxp1 {\n+\t\tu64 reserved_37_63 : 27;\n+\t\tu64 bist : 37;\n+\t} cn63xxp1;\n+\tstruct cvmx_dpi_bist_status_cn61xx cn66xx;\n+\tstruct cvmx_dpi_bist_status_cn63xx cn68xx;\n+\tstruct cvmx_dpi_bist_status_cn63xx cn68xxp1;\n+\tstruct cvmx_dpi_bist_status_cn61xx cn70xx;\n+\tstruct cvmx_dpi_bist_status_cn61xx cn70xxp1;\n+\tstruct cvmx_dpi_bist_status_s cn73xx;\n+\tstruct cvmx_dpi_bist_status_s cn78xx;\n+\tstruct cvmx_dpi_bist_status_cn78xxp1 {\n+\t\tu64 reserved_51_63 : 13;\n+\t\tu64 bist : 51;\n+\t} cn78xxp1;\n+\tstruct cvmx_dpi_bist_status_cn61xx cnf71xx;\n+\tstruct cvmx_dpi_bist_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_bist_status cvmx_dpi_bist_status_t;\n+\n+/**\n+ * cvmx_dpi_ctl\n+ *\n+ * This register provides the enable bit for the DMA and packet state machines.\n+ *\n+ */\n+union cvmx_dpi_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dpi_ctl_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 clk : 1;\n+\t\tu64 en : 1;\n+\t} s;\n+\tstruct cvmx_dpi_ctl_cn61xx {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 en : 1;\n+\t} cn61xx;\n+\tstruct cvmx_dpi_ctl_s cn63xx;\n+\tstruct cvmx_dpi_ctl_s cn63xxp1;\n+\tstruct cvmx_dpi_ctl_s cn66xx;\n+\tstruct cvmx_dpi_ctl_s cn68xx;\n+\tstruct cvmx_dpi_ctl_s cn68xxp1;\n+\tstruct cvmx_dpi_ctl_cn61xx cn70xx;\n+\tstruct cvmx_dpi_ctl_cn61xx cn70xxp1;\n+\tstruct cvmx_dpi_ctl_cn61xx cn73xx;\n+\tstruct cvmx_dpi_ctl_cn61xx cn78xx;\n+\tstruct cvmx_dpi_ctl_cn61xx cn78xxp1;\n+\tstruct cvmx_dpi_ctl_cn61xx cnf71xx;\n+\tstruct cvmx_dpi_ctl_cn61xx cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_ctl cvmx_dpi_ctl_t;\n+\n+/**\n+ * cvmx_dpi_dma#_counts\n+ *\n+ * These registers provide values for determining the number of instructions in the local\n+ * instruction FIFO.\n+ */\n+union cvmx_dpi_dmax_counts {\n+\tu64 u64;\n+\tstruct cvmx_dpi_dmax_counts_s {\n+\t\tu64 reserved_39_63 : 25;\n+\t\tu64 fcnt : 7;\n+\t\tu64 dbell : 32;\n+\t} s;\n+\tstruct cvmx_dpi_dmax_counts_s cn61xx;\n+\tstruct cvmx_dpi_dmax_counts_s cn63xx;\n+\tstruct cvmx_dpi_dmax_counts_s cn63xxp1;\n+\tstruct cvmx_dpi_dmax_counts_s cn66xx;\n+\tstruct cvmx_dpi_dmax_counts_s cn68xx;\n+\tstruct cvmx_dpi_dmax_counts_s cn68xxp1;\n+\tstruct cvmx_dpi_dmax_counts_s cn70xx;\n+\tstruct cvmx_dpi_dmax_counts_s cn70xxp1;\n+\tstruct cvmx_dpi_dmax_counts_s cn73xx;\n+\tstruct cvmx_dpi_dmax_counts_s cn78xx;\n+\tstruct cvmx_dpi_dmax_counts_s cn78xxp1;\n+\tstruct cvmx_dpi_dmax_counts_s cnf71xx;\n+\tstruct cvmx_dpi_dmax_counts_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_dmax_counts cvmx_dpi_dmax_counts_t;\n+\n+/**\n+ * cvmx_dpi_dma#_dbell\n+ *\n+ * This is the door bell register for the eight DMA instruction queues.\n+ *\n+ */\n+union cvmx_dpi_dmax_dbell {\n+\tu64 u64;\n+\tstruct cvmx_dpi_dmax_dbell_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 dbell : 16;\n+\t} s;\n+\tstruct cvmx_dpi_dmax_dbell_s cn61xx;\n+\tstruct cvmx_dpi_dmax_dbell_s cn63xx;\n+\tstruct cvmx_dpi_dmax_dbell_s cn63xxp1;\n+\tstruct cvmx_dpi_dmax_dbell_s cn66xx;\n+\tstruct cvmx_dpi_dmax_dbell_s cn68xx;\n+\tstruct cvmx_dpi_dmax_dbell_s cn68xxp1;\n+\tstruct cvmx_dpi_dmax_dbell_s cn70xx;\n+\tstruct cvmx_dpi_dmax_dbell_s cn70xxp1;\n+\tstruct cvmx_dpi_dmax_dbell_s cn73xx;\n+\tstruct cvmx_dpi_dmax_dbell_s cn78xx;\n+\tstruct cvmx_dpi_dmax_dbell_s cn78xxp1;\n+\tstruct cvmx_dpi_dmax_dbell_s cnf71xx;\n+\tstruct cvmx_dpi_dmax_dbell_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_dmax_dbell cvmx_dpi_dmax_dbell_t;\n+\n+/**\n+ * cvmx_dpi_dma#_err_rsp_status\n+ */\n+union cvmx_dpi_dmax_err_rsp_status {\n+\tu64 u64;\n+\tstruct cvmx_dpi_dmax_err_rsp_status_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 status : 6;\n+\t} s;\n+\tstruct cvmx_dpi_dmax_err_rsp_status_s cn61xx;\n+\tstruct cvmx_dpi_dmax_err_rsp_status_s cn66xx;\n+\tstruct cvmx_dpi_dmax_err_rsp_status_s cn68xx;\n+\tstruct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;\n+\tstruct cvmx_dpi_dmax_err_rsp_status_s cn70xx;\n+\tstruct cvmx_dpi_dmax_err_rsp_status_s cn70xxp1;\n+\tstruct cvmx_dpi_dmax_err_rsp_status_s cn73xx;\n+\tstruct cvmx_dpi_dmax_err_rsp_status_s cn78xx;\n+\tstruct cvmx_dpi_dmax_err_rsp_status_s cn78xxp1;\n+\tstruct cvmx_dpi_dmax_err_rsp_status_s cnf71xx;\n+\tstruct cvmx_dpi_dmax_err_rsp_status_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_dmax_err_rsp_status cvmx_dpi_dmax_err_rsp_status_t;\n+\n+/**\n+ * cvmx_dpi_dma#_ibuff_saddr\n+ *\n+ * These registers provide the address to start reading instructions for the eight DMA\n+ * instruction queues.\n+ */\n+union cvmx_dpi_dmax_ibuff_saddr {\n+\tu64 u64;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 csize : 14;\n+\t\tu64 reserved_0_47 : 48;\n+\t} s;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_cn61xx {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 csize : 14;\n+\t\tu64 reserved_41_47 : 7;\n+\t\tu64 idle : 1;\n+\t\tu64 reserved_36_39 : 4;\n+\t\tu64 saddr : 29;\n+\t\tu64 reserved_0_6 : 7;\n+\t} cn61xx;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_cn68xx {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 csize : 14;\n+\t\tu64 reserved_41_47 : 7;\n+\t\tu64 idle : 1;\n+\t\tu64 saddr : 33;\n+\t\tu64 reserved_0_6 : 7;\n+\t} cn68xx;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_cn68xx cn68xxp1;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn70xx;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn70xxp1;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_cn73xx {\n+\t\tu64 idle : 1;\n+\t\tu64 reserved_62_62 : 1;\n+\t\tu64 csize : 14;\n+\t\tu64 reserved_42_47 : 6;\n+\t\tu64 saddr : 35;\n+\t\tu64 reserved_0_6 : 7;\n+\t} cn73xx;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_cn73xx cn78xx;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_cn73xx cn78xxp1;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx;\n+\tstruct cvmx_dpi_dmax_ibuff_saddr_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_dmax_ibuff_saddr cvmx_dpi_dmax_ibuff_saddr_t;\n+\n+/**\n+ * cvmx_dpi_dma#_iflight\n+ */\n+union cvmx_dpi_dmax_iflight {\n+\tu64 u64;\n+\tstruct cvmx_dpi_dmax_iflight_s {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 cnt : 3;\n+\t} s;\n+\tstruct cvmx_dpi_dmax_iflight_s cn61xx;\n+\tstruct cvmx_dpi_dmax_iflight_s cn66xx;\n+\tstruct cvmx_dpi_dmax_iflight_s cn68xx;\n+\tstruct cvmx_dpi_dmax_iflight_s cn68xxp1;\n+\tstruct cvmx_dpi_dmax_iflight_s cn70xx;\n+\tstruct cvmx_dpi_dmax_iflight_s cn70xxp1;\n+\tstruct cvmx_dpi_dmax_iflight_s cn73xx;\n+\tstruct cvmx_dpi_dmax_iflight_s cn78xx;\n+\tstruct cvmx_dpi_dmax_iflight_s cn78xxp1;\n+\tstruct cvmx_dpi_dmax_iflight_s cnf71xx;\n+\tstruct cvmx_dpi_dmax_iflight_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_dmax_iflight cvmx_dpi_dmax_iflight_t;\n+\n+/**\n+ * cvmx_dpi_dma#_naddr\n+ *\n+ * These registers provide the L2C addresses to read the next Ichunk data.\n+ *\n+ */\n+union cvmx_dpi_dmax_naddr {\n+\tu64 u64;\n+\tstruct cvmx_dpi_dmax_naddr_s {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 addr : 42;\n+\t} s;\n+\tstruct cvmx_dpi_dmax_naddr_cn61xx {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 addr : 36;\n+\t} cn61xx;\n+\tstruct cvmx_dpi_dmax_naddr_cn61xx cn63xx;\n+\tstruct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;\n+\tstruct cvmx_dpi_dmax_naddr_cn61xx cn66xx;\n+\tstruct cvmx_dpi_dmax_naddr_cn68xx {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 addr : 40;\n+\t} cn68xx;\n+\tstruct cvmx_dpi_dmax_naddr_cn68xx cn68xxp1;\n+\tstruct cvmx_dpi_dmax_naddr_cn61xx cn70xx;\n+\tstruct cvmx_dpi_dmax_naddr_cn61xx cn70xxp1;\n+\tstruct cvmx_dpi_dmax_naddr_s cn73xx;\n+\tstruct cvmx_dpi_dmax_naddr_s cn78xx;\n+\tstruct cvmx_dpi_dmax_naddr_s cn78xxp1;\n+\tstruct cvmx_dpi_dmax_naddr_cn61xx cnf71xx;\n+\tstruct cvmx_dpi_dmax_naddr_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_dmax_naddr cvmx_dpi_dmax_naddr_t;\n+\n+/**\n+ * cvmx_dpi_dma#_reqbnk0\n+ *\n+ * These registers provide the current contents of the request state machine, bank 0.\n+ *\n+ */\n+union cvmx_dpi_dmax_reqbnk0 {\n+\tu64 u64;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s {\n+\t\tu64 state : 64;\n+\t} s;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s cn61xx;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s cn63xx;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s cn66xx;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s cn68xx;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s cn70xx;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s cn70xxp1;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s cn73xx;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s cn78xx;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s cn78xxp1;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s cnf71xx;\n+\tstruct cvmx_dpi_dmax_reqbnk0_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_dmax_reqbnk0 cvmx_dpi_dmax_reqbnk0_t;\n+\n+/**\n+ * cvmx_dpi_dma#_reqbnk1\n+ *\n+ * These registers provide the current contents of the request state machine, bank 1.\n+ *\n+ */\n+union cvmx_dpi_dmax_reqbnk1 {\n+\tu64 u64;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s {\n+\t\tu64 state : 64;\n+\t} s;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s cn61xx;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s cn63xx;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s cn66xx;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s cn68xx;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s cn70xx;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s cn70xxp1;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s cn73xx;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s cn78xx;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s cn78xxp1;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s cnf71xx;\n+\tstruct cvmx_dpi_dmax_reqbnk1_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_dmax_reqbnk1 cvmx_dpi_dmax_reqbnk1_t;\n+\n+/**\n+ * cvmx_dpi_dma#_reqq_ctl\n+ *\n+ * This register contains the control bits for transactions on the eight request queues.\n+ *\n+ */\n+union cvmx_dpi_dmax_reqq_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dpi_dmax_reqq_ctl_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 st_cmd : 1;\n+\t\tu64 reserved_2_7 : 6;\n+\t\tu64 ld_cmd : 2;\n+\t} s;\n+\tstruct cvmx_dpi_dmax_reqq_ctl_s cn73xx;\n+\tstruct cvmx_dpi_dmax_reqq_ctl_s cn78xx;\n+\tstruct cvmx_dpi_dmax_reqq_ctl_s cn78xxp1;\n+\tstruct cvmx_dpi_dmax_reqq_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_dmax_reqq_ctl cvmx_dpi_dmax_reqq_ctl_t;\n+\n+/**\n+ * cvmx_dpi_dma_control\n+ *\n+ * This register controls the operation of DMA input and output.\n+ *\n+ */\n+union cvmx_dpi_dma_control {\n+\tu64 u64;\n+\tstruct cvmx_dpi_dma_control_s {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 dici_mode : 1;\n+\t\tu64 pkt_en1 : 1;\n+\t\tu64 ffp_dis : 1;\n+\t\tu64 commit_mode : 1;\n+\t\tu64 pkt_hp : 1;\n+\t\tu64 pkt_en : 1;\n+\t\tu64 reserved_54_55 : 2;\n+\t\tu64 dma_enb : 6;\n+\t\tu64 wqecsdis : 1;\n+\t\tu64 wqecsoff : 7;\n+\t\tu64 zbwcsen : 1;\n+\t\tu64 wqecsmode : 2;\n+\t\tu64 reserved_35_36 : 2;\n+\t\tu64 ncb_tag : 1;\n+\t\tu64 b0_lend : 1;\n+\t\tu64 reserved_20_32 : 13;\n+\t\tu64 o_add1 : 1;\n+\t\tu64 o_ro : 1;\n+\t\tu64 o_ns : 1;\n+\t\tu64 o_es : 2;\n+\t\tu64 o_mode : 1;\n+\t\tu64 reserved_0_13 : 14;\n+\t} s;\n+\tstruct cvmx_dpi_dma_control_cn61xx {\n+\t\tu64 reserved_62_63 : 2;\n+\t\tu64 dici_mode : 1;\n+\t\tu64 pkt_en1 : 1;\n+\t\tu64 ffp_dis : 1;\n+\t\tu64 commit_mode : 1;\n+\t\tu64 pkt_hp : 1;\n+\t\tu64 pkt_en : 1;\n+\t\tu64 reserved_54_55 : 2;\n+\t\tu64 dma_enb : 6;\n+\t\tu64 reserved_34_47 : 14;\n+\t\tu64 b0_lend : 1;\n+\t\tu64 dwb_denb : 1;\n+\t\tu64 dwb_ichk : 9;\n+\t\tu64 fpa_que : 3;\n+\t\tu64 o_add1 : 1;\n+\t\tu64 o_ro : 1;\n+\t\tu64 o_ns : 1;\n+\t\tu64 o_es : 2;\n+\t\tu64 o_mode : 1;\n+\t\tu64 reserved_0_13 : 14;\n+\t} cn61xx;\n+\tstruct cvmx_dpi_dma_control_cn63xx {\n+\t\tu64 reserved_61_63 : 3;\n+\t\tu64 pkt_en1 : 1;\n+\t\tu64 ffp_dis : 1;\n+\t\tu64 commit_mode : 1;\n+\t\tu64 pkt_hp : 1;\n+\t\tu64 pkt_en : 1;\n+\t\tu64 reserved_54_55 : 2;\n+\t\tu64 dma_enb : 6;\n+\t\tu64 reserved_34_47 : 14;\n+\t\tu64 b0_lend : 1;\n+\t\tu64 dwb_denb : 1;\n+\t\tu64 dwb_ichk : 9;\n+\t\tu64 fpa_que : 3;\n+\t\tu64 o_add1 : 1;\n+\t\tu64 o_ro : 1;\n+\t\tu64 o_ns : 1;\n+\t\tu64 o_es : 2;\n+\t\tu64 o_mode : 1;\n+\t\tu64 reserved_0_13 : 14;\n+\t} cn63xx;\n+\tstruct cvmx_dpi_dma_control_cn63xxp1 {\n+\t\tu64 reserved_59_63 : 5;\n+\t\tu64 commit_mode : 1;\n+\t\tu64 pkt_hp : 1;\n+\t\tu64 pkt_en : 1;\n+\t\tu64 reserved_54_55 : 2;\n+\t\tu64 dma_enb : 6;\n+\t\tu64 reserved_34_47 : 14;\n+\t\tu64 b0_lend : 1;\n+\t\tu64 dwb_denb : 1;\n+\t\tu64 dwb_ichk : 9;\n+\t\tu64 fpa_que : 3;\n+\t\tu64 o_add1 : 1;\n+\t\tu64 o_ro : 1;\n+\t\tu64 o_ns : 1;\n+\t\tu64 o_es : 2;\n+\t\tu64 o_mode : 1;\n+\t\tu64 reserved_0_13 : 14;\n+\t} cn63xxp1;\n+\tstruct cvmx_dpi_dma_control_cn63xx cn66xx;\n+\tstruct cvmx_dpi_dma_control_cn61xx cn68xx;\n+\tstruct cvmx_dpi_dma_control_cn63xx cn68xxp1;\n+\tstruct cvmx_dpi_dma_control_cn61xx cn70xx;\n+\tstruct cvmx_dpi_dma_control_cn61xx cn70xxp1;\n+\tstruct cvmx_dpi_dma_control_cn73xx {\n+\t\tu64 reserved_60_63 : 4;\n+\t\tu64 ffp_dis : 1;\n+\t\tu64 commit_mode : 1;\n+\t\tu64 reserved_57_57 : 1;\n+\t\tu64 pkt_en : 1;\n+\t\tu64 reserved_54_55 : 2;\n+\t\tu64 dma_enb : 6;\n+\t\tu64 wqecsdis : 1;\n+\t\tu64 wqecsoff : 7;\n+\t\tu64 zbwcsen : 1;\n+\t\tu64 wqecsmode : 2;\n+\t\tu64 reserved_35_36 : 2;\n+\t\tu64 ncb_tag : 1;\n+\t\tu64 b0_lend : 1;\n+\t\tu64 ldwb : 1;\n+\t\tu64 aura_ichk : 12;\n+\t\tu64 o_add1 : 1;\n+\t\tu64 o_ro : 1;\n+\t\tu64 o_ns : 1;\n+\t\tu64 o_es : 2;\n+\t\tu64 o_mode : 1;\n+\t\tu64 reserved_0_13 : 14;\n+\t} cn73xx;\n+\tstruct cvmx_dpi_dma_control_cn73xx cn78xx;\n+\tstruct cvmx_dpi_dma_control_cn73xx cn78xxp1;\n+\tstruct cvmx_dpi_dma_control_cn61xx cnf71xx;\n+\tstruct cvmx_dpi_dma_control_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_dma_control cvmx_dpi_dma_control_t;\n+\n+/**\n+ * cvmx_dpi_dma_eng#_en\n+ *\n+ * These registers provide control for the DMA engines.\n+ *\n+ */\n+union cvmx_dpi_dma_engx_en {\n+\tu64 u64;\n+\tstruct cvmx_dpi_dma_engx_en_s {\n+\t\tu64 reserved_39_63 : 25;\n+\t\tu64 eng_molr : 7;\n+\t\tu64 reserved_8_31 : 24;\n+\t\tu64 qen : 8;\n+\t} s;\n+\tstruct cvmx_dpi_dma_engx_en_cn61xx {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 qen : 8;\n+\t} cn61xx;\n+\tstruct cvmx_dpi_dma_engx_en_cn61xx cn63xx;\n+\tstruct cvmx_dpi_dma_engx_en_cn61xx cn63xxp1;\n+\tstruct cvmx_dpi_dma_engx_en_cn61xx cn66xx;\n+\tstruct cvmx_dpi_dma_engx_en_cn61xx cn68xx;\n+\tstruct cvmx_dpi_dma_engx_en_cn61xx cn68xxp1;\n+\tstruct cvmx_dpi_dma_engx_en_cn61xx cn70xx;\n+\tstruct cvmx_dpi_dma_engx_en_cn61xx cn70xxp1;\n+\tstruct cvmx_dpi_dma_engx_en_s cn73xx;\n+\tstruct cvmx_dpi_dma_engx_en_s cn78xx;\n+\tstruct cvmx_dpi_dma_engx_en_s cn78xxp1;\n+\tstruct cvmx_dpi_dma_engx_en_cn61xx cnf71xx;\n+\tstruct cvmx_dpi_dma_engx_en_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_dma_engx_en cvmx_dpi_dma_engx_en_t;\n+\n+/**\n+ * cvmx_dpi_dma_pp#_cnt\n+ *\n+ * DPI_DMA_PP[0..3]_CNT  = DMA per PP Instr Done Counter\n+ * When DMA Instruction Completion Interrupt Mode DPI_DMA_CONTROL.DICI_MODE is enabled, every dma\n+ * instruction\n+ * that has the WQP=0 and a PTR value of 1..4 will incremrement DPI_DMA_PPx_CNT value-1 counter.\n+ * Instructions with WQP=0 and PTR values higher then 0x3F will still send a zero byte write.\n+ * Hardware reserves that values 5..63 for future use and will treat them as a PTR of 0 and do\n+ * nothing.\n+ */\n+union cvmx_dpi_dma_ppx_cnt {\n+\tu64 u64;\n+\tstruct cvmx_dpi_dma_ppx_cnt_s {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 cnt : 16;\n+\t} s;\n+\tstruct cvmx_dpi_dma_ppx_cnt_s cn61xx;\n+\tstruct cvmx_dpi_dma_ppx_cnt_s cn68xx;\n+\tstruct cvmx_dpi_dma_ppx_cnt_s cn70xx;\n+\tstruct cvmx_dpi_dma_ppx_cnt_s cn70xxp1;\n+\tstruct cvmx_dpi_dma_ppx_cnt_s cn73xx;\n+\tstruct cvmx_dpi_dma_ppx_cnt_s cn78xx;\n+\tstruct cvmx_dpi_dma_ppx_cnt_s cn78xxp1;\n+\tstruct cvmx_dpi_dma_ppx_cnt_s cnf71xx;\n+\tstruct cvmx_dpi_dma_ppx_cnt_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_dma_ppx_cnt cvmx_dpi_dma_ppx_cnt_t;\n+\n+/**\n+ * cvmx_dpi_dma_pp_int\n+ */\n+union cvmx_dpi_dma_pp_int {\n+\tu64 u64;\n+\tstruct cvmx_dpi_dma_pp_int_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 complete : 48;\n+\t} s;\n+\tstruct cvmx_dpi_dma_pp_int_cn73xx {\n+\t\tu64 reserved_16_63 : 48;\n+\t\tu64 complete : 16;\n+\t} cn73xx;\n+\tstruct cvmx_dpi_dma_pp_int_s cn78xx;\n+\tstruct cvmx_dpi_dma_pp_int_s cn78xxp1;\n+\tstruct cvmx_dpi_dma_pp_int_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_dma_pp_int cvmx_dpi_dma_pp_int_t;\n+\n+/**\n+ * cvmx_dpi_ecc_ctl\n+ *\n+ * This register allows inserting ECC errors for testing.\n+ *\n+ */\n+union cvmx_dpi_ecc_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dpi_ecc_ctl_s {\n+\t\tu64 reserved_33_63 : 31;\n+\t\tu64 ram_cdis : 1;\n+\t\tu64 reserved_17_31 : 15;\n+\t\tu64 ram_flip1 : 1;\n+\t\tu64 reserved_1_15 : 15;\n+\t\tu64 ram_flip0 : 1;\n+\t} s;\n+\tstruct cvmx_dpi_ecc_ctl_s cn73xx;\n+\tstruct cvmx_dpi_ecc_ctl_s cn78xx;\n+\tstruct cvmx_dpi_ecc_ctl_s cn78xxp1;\n+\tstruct cvmx_dpi_ecc_ctl_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_ecc_ctl cvmx_dpi_ecc_ctl_t;\n+\n+/**\n+ * cvmx_dpi_ecc_int\n+ *\n+ * This register contains ECC error interrupt summary bits.\n+ *\n+ */\n+union cvmx_dpi_ecc_int {\n+\tu64 u64;\n+\tstruct cvmx_dpi_ecc_int_s {\n+\t\tu64 reserved_47_63 : 17;\n+\t\tu64 ram_sbe : 15;\n+\t\tu64 reserved_15_31 : 17;\n+\t\tu64 ram_dbe : 15;\n+\t} s;\n+\tstruct cvmx_dpi_ecc_int_s cn73xx;\n+\tstruct cvmx_dpi_ecc_int_s cn78xx;\n+\tstruct cvmx_dpi_ecc_int_s cn78xxp1;\n+\tstruct cvmx_dpi_ecc_int_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_ecc_int cvmx_dpi_ecc_int_t;\n+\n+/**\n+ * cvmx_dpi_eng#_buf\n+ *\n+ * Notes:\n+ * The total amount of storage allocated to the 6 DPI DMA engines (via DPI_ENG*_BUF[BLKS]) must not exceed 8KB.\n+ *\n+ */\n+union cvmx_dpi_engx_buf {\n+\tu64 u64;\n+\tstruct cvmx_dpi_engx_buf_s {\n+\t\tu64 reserved_38_63 : 26;\n+\t\tu64 compblks : 6;\n+\t\tu64 reserved_10_31 : 22;\n+\t\tu64 base : 6;\n+\t\tu64 blks : 4;\n+\t} s;\n+\tstruct cvmx_dpi_engx_buf_cn61xx {\n+\t\tu64 reserved_37_63 : 27;\n+\t\tu64 compblks : 5;\n+\t\tu64 reserved_9_31 : 23;\n+\t\tu64 base : 5;\n+\t\tu64 blks : 4;\n+\t} cn61xx;\n+\tstruct cvmx_dpi_engx_buf_cn63xx {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 base : 4;\n+\t\tu64 blks : 4;\n+\t} cn63xx;\n+\tstruct cvmx_dpi_engx_buf_cn63xx cn63xxp1;\n+\tstruct cvmx_dpi_engx_buf_cn61xx cn66xx;\n+\tstruct cvmx_dpi_engx_buf_cn61xx cn68xx;\n+\tstruct cvmx_dpi_engx_buf_cn61xx cn68xxp1;\n+\tstruct cvmx_dpi_engx_buf_cn61xx cn70xx;\n+\tstruct cvmx_dpi_engx_buf_cn61xx cn70xxp1;\n+\tstruct cvmx_dpi_engx_buf_s cn73xx;\n+\tstruct cvmx_dpi_engx_buf_s cn78xx;\n+\tstruct cvmx_dpi_engx_buf_s cn78xxp1;\n+\tstruct cvmx_dpi_engx_buf_cn61xx cnf71xx;\n+\tstruct cvmx_dpi_engx_buf_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_engx_buf cvmx_dpi_engx_buf_t;\n+\n+/**\n+ * cvmx_dpi_info_reg\n+ */\n+union cvmx_dpi_info_reg {\n+\tu64 u64;\n+\tstruct cvmx_dpi_info_reg_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 ffp : 4;\n+\t\tu64 reserved_2_3 : 2;\n+\t\tu64 ncb : 1;\n+\t\tu64 rsl : 1;\n+\t} s;\n+\tstruct cvmx_dpi_info_reg_s cn61xx;\n+\tstruct cvmx_dpi_info_reg_s cn63xx;\n+\tstruct cvmx_dpi_info_reg_cn63xxp1 {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 ncb : 1;\n+\t\tu64 rsl : 1;\n+\t} cn63xxp1;\n+\tstruct cvmx_dpi_info_reg_s cn66xx;\n+\tstruct cvmx_dpi_info_reg_s cn68xx;\n+\tstruct cvmx_dpi_info_reg_s cn68xxp1;\n+\tstruct cvmx_dpi_info_reg_s cn70xx;\n+\tstruct cvmx_dpi_info_reg_s cn70xxp1;\n+\tstruct cvmx_dpi_info_reg_s cn73xx;\n+\tstruct cvmx_dpi_info_reg_s cn78xx;\n+\tstruct cvmx_dpi_info_reg_s cn78xxp1;\n+\tstruct cvmx_dpi_info_reg_s cnf71xx;\n+\tstruct cvmx_dpi_info_reg_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_info_reg cvmx_dpi_info_reg_t;\n+\n+/**\n+ * cvmx_dpi_int_en\n+ */\n+union cvmx_dpi_int_en {\n+\tu64 u64;\n+\tstruct cvmx_dpi_int_en_s {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 sprt3_rst : 1;\n+\t\tu64 sprt2_rst : 1;\n+\t\tu64 sprt1_rst : 1;\n+\t\tu64 sprt0_rst : 1;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 req_badfil : 1;\n+\t\tu64 req_inull : 1;\n+\t\tu64 req_anull : 1;\n+\t\tu64 req_undflw : 1;\n+\t\tu64 req_ovrflw : 1;\n+\t\tu64 req_badlen : 1;\n+\t\tu64 req_badadr : 1;\n+\t\tu64 dmadbo : 8;\n+\t\tu64 reserved_2_7 : 6;\n+\t\tu64 nfovr : 1;\n+\t\tu64 nderr : 1;\n+\t} s;\n+\tstruct cvmx_dpi_int_en_s cn61xx;\n+\tstruct cvmx_dpi_int_en_cn63xx {\n+\t\tu64 reserved_26_63 : 38;\n+\t\tu64 sprt1_rst : 1;\n+\t\tu64 sprt0_rst : 1;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 req_badfil : 1;\n+\t\tu64 req_inull : 1;\n+\t\tu64 req_anull : 1;\n+\t\tu64 req_undflw : 1;\n+\t\tu64 req_ovrflw : 1;\n+\t\tu64 req_badlen : 1;\n+\t\tu64 req_badadr : 1;\n+\t\tu64 dmadbo : 8;\n+\t\tu64 reserved_2_7 : 6;\n+\t\tu64 nfovr : 1;\n+\t\tu64 nderr : 1;\n+\t} cn63xx;\n+\tstruct cvmx_dpi_int_en_cn63xx cn63xxp1;\n+\tstruct cvmx_dpi_int_en_s cn66xx;\n+\tstruct cvmx_dpi_int_en_cn63xx cn68xx;\n+\tstruct cvmx_dpi_int_en_cn63xx cn68xxp1;\n+\tstruct cvmx_dpi_int_en_cn70xx {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 sprt3_rst : 1;\n+\t\tu64 sprt2_rst : 1;\n+\t\tu64 sprt1_rst : 1;\n+\t\tu64 sprt0_rst : 1;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 req_badfil : 1;\n+\t\tu64 req_inull : 1;\n+\t\tu64 req_anull : 1;\n+\t\tu64 req_undflw : 1;\n+\t\tu64 req_ovrflw : 1;\n+\t\tu64 req_badlen : 1;\n+\t\tu64 req_badadr : 1;\n+\t\tu64 dmadbo : 8;\n+\t\tu64 reserved_7_2 : 6;\n+\t\tu64 nfovr : 1;\n+\t\tu64 nderr : 1;\n+\t} cn70xx;\n+\tstruct cvmx_dpi_int_en_cn70xx cn70xxp1;\n+\tstruct cvmx_dpi_int_en_s cnf71xx;\n+};\n+\n+typedef union cvmx_dpi_int_en cvmx_dpi_int_en_t;\n+\n+/**\n+ * cvmx_dpi_int_reg\n+ *\n+ * This register contains error flags for DPI.\n+ *\n+ */\n+union cvmx_dpi_int_reg {\n+\tu64 u64;\n+\tstruct cvmx_dpi_int_reg_s {\n+\t\tu64 reserved_28_63 : 36;\n+\t\tu64 sprt3_rst : 1;\n+\t\tu64 sprt2_rst : 1;\n+\t\tu64 sprt1_rst : 1;\n+\t\tu64 sprt0_rst : 1;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 req_badfil : 1;\n+\t\tu64 req_inull : 1;\n+\t\tu64 req_anull : 1;\n+\t\tu64 req_undflw : 1;\n+\t\tu64 req_ovrflw : 1;\n+\t\tu64 req_badlen : 1;\n+\t\tu64 req_badadr : 1;\n+\t\tu64 dmadbo : 8;\n+\t\tu64 reserved_2_7 : 6;\n+\t\tu64 nfovr : 1;\n+\t\tu64 nderr : 1;\n+\t} s;\n+\tstruct cvmx_dpi_int_reg_s cn61xx;\n+\tstruct cvmx_dpi_int_reg_cn63xx {\n+\t\tu64 reserved_26_63 : 38;\n+\t\tu64 sprt1_rst : 1;\n+\t\tu64 sprt0_rst : 1;\n+\t\tu64 reserved_23_23 : 1;\n+\t\tu64 req_badfil : 1;\n+\t\tu64 req_inull : 1;\n+\t\tu64 req_anull : 1;\n+\t\tu64 req_undflw : 1;\n+\t\tu64 req_ovrflw : 1;\n+\t\tu64 req_badlen : 1;\n+\t\tu64 req_badadr : 1;\n+\t\tu64 dmadbo : 8;\n+\t\tu64 reserved_2_7 : 6;\n+\t\tu64 nfovr : 1;\n+\t\tu64 nderr : 1;\n+\t} cn63xx;\n+\tstruct cvmx_dpi_int_reg_cn63xx cn63xxp1;\n+\tstruct cvmx_dpi_int_reg_s cn66xx;\n+\tstruct cvmx_dpi_int_reg_cn63xx cn68xx;\n+\tstruct cvmx_dpi_int_reg_cn63xx cn68xxp1;\n+\tstruct cvmx_dpi_int_reg_s cn70xx;\n+\tstruct cvmx_dpi_int_reg_s cn70xxp1;\n+\tstruct cvmx_dpi_int_reg_cn73xx {\n+\t\tu64 reserved_23_63 : 41;\n+\t\tu64 req_badfil : 1;\n+\t\tu64 req_inull : 1;\n+\t\tu64 req_anull : 1;\n+\t\tu64 req_undflw : 1;\n+\t\tu64 req_ovrflw : 1;\n+\t\tu64 req_badlen : 1;\n+\t\tu64 req_badadr : 1;\n+\t\tu64 dmadbo : 8;\n+\t\tu64 reserved_2_7 : 6;\n+\t\tu64 nfovr : 1;\n+\t\tu64 nderr : 1;\n+\t} cn73xx;\n+\tstruct cvmx_dpi_int_reg_cn73xx cn78xx;\n+\tstruct cvmx_dpi_int_reg_s cn78xxp1;\n+\tstruct cvmx_dpi_int_reg_s cnf71xx;\n+\tstruct cvmx_dpi_int_reg_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_int_reg cvmx_dpi_int_reg_t;\n+\n+/**\n+ * cvmx_dpi_ncb#_cfg\n+ */\n+union cvmx_dpi_ncbx_cfg {\n+\tu64 u64;\n+\tstruct cvmx_dpi_ncbx_cfg_s {\n+\t\tu64 reserved_6_63 : 58;\n+\t\tu64 molr : 6;\n+\t} s;\n+\tstruct cvmx_dpi_ncbx_cfg_s cn61xx;\n+\tstruct cvmx_dpi_ncbx_cfg_s cn66xx;\n+\tstruct cvmx_dpi_ncbx_cfg_s cn68xx;\n+\tstruct cvmx_dpi_ncbx_cfg_s cn70xx;\n+\tstruct cvmx_dpi_ncbx_cfg_s cn70xxp1;\n+\tstruct cvmx_dpi_ncbx_cfg_s cn73xx;\n+\tstruct cvmx_dpi_ncbx_cfg_s cn78xx;\n+\tstruct cvmx_dpi_ncbx_cfg_s cn78xxp1;\n+\tstruct cvmx_dpi_ncbx_cfg_s cnf71xx;\n+\tstruct cvmx_dpi_ncbx_cfg_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_ncbx_cfg cvmx_dpi_ncbx_cfg_t;\n+\n+/**\n+ * cvmx_dpi_ncb_ctl\n+ *\n+ * This register chooses which NCB interface DPI uses for L2/DRAM reads/writes.\n+ *\n+ */\n+union cvmx_dpi_ncb_ctl {\n+\tu64 u64;\n+\tstruct cvmx_dpi_ncb_ctl_s {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 ncbsel_prt_xor_dis : 1;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 ncbsel_zbw : 1;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 ncbsel_req : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 ncbsel_dst : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 ncbsel_src : 1;\n+\t\tu64 reserved_1_7 : 7;\n+\t\tu64 prt : 1;\n+\t} s;\n+\tstruct cvmx_dpi_ncb_ctl_cn73xx {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 ncbsel_prt_xor_dis : 1;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 ncbsel_zbw : 1;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 ncbsel_req : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 ncbsel_dst : 1;\n+\t\tu64 reserved_9_11 : 3;\n+\t\tu64 ncbsel_src : 1;\n+\t\tu64 reserved_0_7 : 8;\n+\t} cn73xx;\n+\tstruct cvmx_dpi_ncb_ctl_s cn78xx;\n+\tstruct cvmx_dpi_ncb_ctl_s cn78xxp1;\n+\tstruct cvmx_dpi_ncb_ctl_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_ncb_ctl cvmx_dpi_ncb_ctl_t;\n+\n+/**\n+ * cvmx_dpi_pint_info\n+ *\n+ * This register provides DPI packet interrupt information.\n+ *\n+ */\n+union cvmx_dpi_pint_info {\n+\tu64 u64;\n+\tstruct cvmx_dpi_pint_info_s {\n+\t\tu64 reserved_14_63 : 50;\n+\t\tu64 iinfo : 6;\n+\t\tu64 reserved_6_7 : 2;\n+\t\tu64 sinfo : 6;\n+\t} s;\n+\tstruct cvmx_dpi_pint_info_s cn61xx;\n+\tstruct cvmx_dpi_pint_info_s cn63xx;\n+\tstruct cvmx_dpi_pint_info_s cn63xxp1;\n+\tstruct cvmx_dpi_pint_info_s cn66xx;\n+\tstruct cvmx_dpi_pint_info_s cn68xx;\n+\tstruct cvmx_dpi_pint_info_s cn68xxp1;\n+\tstruct cvmx_dpi_pint_info_s cn70xx;\n+\tstruct cvmx_dpi_pint_info_s cn70xxp1;\n+\tstruct cvmx_dpi_pint_info_s cn73xx;\n+\tstruct cvmx_dpi_pint_info_s cn78xx;\n+\tstruct cvmx_dpi_pint_info_s cn78xxp1;\n+\tstruct cvmx_dpi_pint_info_s cnf71xx;\n+\tstruct cvmx_dpi_pint_info_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_pint_info cvmx_dpi_pint_info_t;\n+\n+/**\n+ * cvmx_dpi_pkt_err_rsp\n+ */\n+union cvmx_dpi_pkt_err_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dpi_pkt_err_rsp_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 pkterr : 1;\n+\t} s;\n+\tstruct cvmx_dpi_pkt_err_rsp_s cn61xx;\n+\tstruct cvmx_dpi_pkt_err_rsp_s cn63xx;\n+\tstruct cvmx_dpi_pkt_err_rsp_s cn63xxp1;\n+\tstruct cvmx_dpi_pkt_err_rsp_s cn66xx;\n+\tstruct cvmx_dpi_pkt_err_rsp_s cn68xx;\n+\tstruct cvmx_dpi_pkt_err_rsp_s cn68xxp1;\n+\tstruct cvmx_dpi_pkt_err_rsp_s cn70xx;\n+\tstruct cvmx_dpi_pkt_err_rsp_s cn70xxp1;\n+\tstruct cvmx_dpi_pkt_err_rsp_s cn73xx;\n+\tstruct cvmx_dpi_pkt_err_rsp_s cn78xx;\n+\tstruct cvmx_dpi_pkt_err_rsp_s cn78xxp1;\n+\tstruct cvmx_dpi_pkt_err_rsp_s cnf71xx;\n+\tstruct cvmx_dpi_pkt_err_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_pkt_err_rsp cvmx_dpi_pkt_err_rsp_t;\n+\n+/**\n+ * cvmx_dpi_req_err_rsp\n+ */\n+union cvmx_dpi_req_err_rsp {\n+\tu64 u64;\n+\tstruct cvmx_dpi_req_err_rsp_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 qerr : 8;\n+\t} s;\n+\tstruct cvmx_dpi_req_err_rsp_s cn61xx;\n+\tstruct cvmx_dpi_req_err_rsp_s cn63xx;\n+\tstruct cvmx_dpi_req_err_rsp_s cn63xxp1;\n+\tstruct cvmx_dpi_req_err_rsp_s cn66xx;\n+\tstruct cvmx_dpi_req_err_rsp_s cn68xx;\n+\tstruct cvmx_dpi_req_err_rsp_s cn68xxp1;\n+\tstruct cvmx_dpi_req_err_rsp_s cn70xx;\n+\tstruct cvmx_dpi_req_err_rsp_s cn70xxp1;\n+\tstruct cvmx_dpi_req_err_rsp_s cn73xx;\n+\tstruct cvmx_dpi_req_err_rsp_s cn78xx;\n+\tstruct cvmx_dpi_req_err_rsp_s cn78xxp1;\n+\tstruct cvmx_dpi_req_err_rsp_s cnf71xx;\n+\tstruct cvmx_dpi_req_err_rsp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_req_err_rsp cvmx_dpi_req_err_rsp_t;\n+\n+/**\n+ * cvmx_dpi_req_err_rsp_en\n+ */\n+union cvmx_dpi_req_err_rsp_en {\n+\tu64 u64;\n+\tstruct cvmx_dpi_req_err_rsp_en_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 en : 8;\n+\t} s;\n+\tstruct cvmx_dpi_req_err_rsp_en_s cn61xx;\n+\tstruct cvmx_dpi_req_err_rsp_en_s cn63xx;\n+\tstruct cvmx_dpi_req_err_rsp_en_s cn63xxp1;\n+\tstruct cvmx_dpi_req_err_rsp_en_s cn66xx;\n+\tstruct cvmx_dpi_req_err_rsp_en_s cn68xx;\n+\tstruct cvmx_dpi_req_err_rsp_en_s cn68xxp1;\n+\tstruct cvmx_dpi_req_err_rsp_en_s cn70xx;\n+\tstruct cvmx_dpi_req_err_rsp_en_s cn70xxp1;\n+\tstruct cvmx_dpi_req_err_rsp_en_s cn73xx;\n+\tstruct cvmx_dpi_req_err_rsp_en_s cn78xx;\n+\tstruct cvmx_dpi_req_err_rsp_en_s cn78xxp1;\n+\tstruct cvmx_dpi_req_err_rsp_en_s cnf71xx;\n+\tstruct cvmx_dpi_req_err_rsp_en_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_req_err_rsp_en cvmx_dpi_req_err_rsp_en_t;\n+\n+/**\n+ * cvmx_dpi_req_err_rst\n+ */\n+union cvmx_dpi_req_err_rst {\n+\tu64 u64;\n+\tstruct cvmx_dpi_req_err_rst_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 qerr : 8;\n+\t} s;\n+\tstruct cvmx_dpi_req_err_rst_s cn61xx;\n+\tstruct cvmx_dpi_req_err_rst_s cn63xx;\n+\tstruct cvmx_dpi_req_err_rst_s cn63xxp1;\n+\tstruct cvmx_dpi_req_err_rst_s cn66xx;\n+\tstruct cvmx_dpi_req_err_rst_s cn68xx;\n+\tstruct cvmx_dpi_req_err_rst_s cn68xxp1;\n+\tstruct cvmx_dpi_req_err_rst_s cn70xx;\n+\tstruct cvmx_dpi_req_err_rst_s cn70xxp1;\n+\tstruct cvmx_dpi_req_err_rst_s cn73xx;\n+\tstruct cvmx_dpi_req_err_rst_s cn78xx;\n+\tstruct cvmx_dpi_req_err_rst_s cn78xxp1;\n+\tstruct cvmx_dpi_req_err_rst_s cnf71xx;\n+\tstruct cvmx_dpi_req_err_rst_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_req_err_rst cvmx_dpi_req_err_rst_t;\n+\n+/**\n+ * cvmx_dpi_req_err_rst_en\n+ */\n+union cvmx_dpi_req_err_rst_en {\n+\tu64 u64;\n+\tstruct cvmx_dpi_req_err_rst_en_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 en : 8;\n+\t} s;\n+\tstruct cvmx_dpi_req_err_rst_en_s cn61xx;\n+\tstruct cvmx_dpi_req_err_rst_en_s cn63xx;\n+\tstruct cvmx_dpi_req_err_rst_en_s cn63xxp1;\n+\tstruct cvmx_dpi_req_err_rst_en_s cn66xx;\n+\tstruct cvmx_dpi_req_err_rst_en_s cn68xx;\n+\tstruct cvmx_dpi_req_err_rst_en_s cn68xxp1;\n+\tstruct cvmx_dpi_req_err_rst_en_s cn70xx;\n+\tstruct cvmx_dpi_req_err_rst_en_s cn70xxp1;\n+\tstruct cvmx_dpi_req_err_rst_en_s cn73xx;\n+\tstruct cvmx_dpi_req_err_rst_en_s cn78xx;\n+\tstruct cvmx_dpi_req_err_rst_en_s cn78xxp1;\n+\tstruct cvmx_dpi_req_err_rst_en_s cnf71xx;\n+\tstruct cvmx_dpi_req_err_rst_en_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_req_err_rst_en cvmx_dpi_req_err_rst_en_t;\n+\n+/**\n+ * cvmx_dpi_req_err_skip_comp\n+ */\n+union cvmx_dpi_req_err_skip_comp {\n+\tu64 u64;\n+\tstruct cvmx_dpi_req_err_skip_comp_s {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 en_rst : 8;\n+\t\tu64 reserved_8_15 : 8;\n+\t\tu64 en_rsp : 8;\n+\t} s;\n+\tstruct cvmx_dpi_req_err_skip_comp_s cn61xx;\n+\tstruct cvmx_dpi_req_err_skip_comp_s cn66xx;\n+\tstruct cvmx_dpi_req_err_skip_comp_s cn68xx;\n+\tstruct cvmx_dpi_req_err_skip_comp_s cn68xxp1;\n+\tstruct cvmx_dpi_req_err_skip_comp_s cn70xx;\n+\tstruct cvmx_dpi_req_err_skip_comp_s cn70xxp1;\n+\tstruct cvmx_dpi_req_err_skip_comp_s cn73xx;\n+\tstruct cvmx_dpi_req_err_skip_comp_s cn78xx;\n+\tstruct cvmx_dpi_req_err_skip_comp_s cn78xxp1;\n+\tstruct cvmx_dpi_req_err_skip_comp_s cnf71xx;\n+\tstruct cvmx_dpi_req_err_skip_comp_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_req_err_skip_comp cvmx_dpi_req_err_skip_comp_t;\n+\n+/**\n+ * cvmx_dpi_req_gbl_en\n+ */\n+union cvmx_dpi_req_gbl_en {\n+\tu64 u64;\n+\tstruct cvmx_dpi_req_gbl_en_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 qen : 8;\n+\t} s;\n+\tstruct cvmx_dpi_req_gbl_en_s cn61xx;\n+\tstruct cvmx_dpi_req_gbl_en_s cn63xx;\n+\tstruct cvmx_dpi_req_gbl_en_s cn63xxp1;\n+\tstruct cvmx_dpi_req_gbl_en_s cn66xx;\n+\tstruct cvmx_dpi_req_gbl_en_s cn68xx;\n+\tstruct cvmx_dpi_req_gbl_en_s cn68xxp1;\n+\tstruct cvmx_dpi_req_gbl_en_s cn70xx;\n+\tstruct cvmx_dpi_req_gbl_en_s cn70xxp1;\n+\tstruct cvmx_dpi_req_gbl_en_s cn73xx;\n+\tstruct cvmx_dpi_req_gbl_en_s cn78xx;\n+\tstruct cvmx_dpi_req_gbl_en_s cn78xxp1;\n+\tstruct cvmx_dpi_req_gbl_en_s cnf71xx;\n+\tstruct cvmx_dpi_req_gbl_en_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_req_gbl_en cvmx_dpi_req_gbl_en_t;\n+\n+/**\n+ * cvmx_dpi_sli_prt#_cfg\n+ *\n+ * This register configures the max read request size, max payload size, and max number of SLI\n+ * tags in use. Indexed by SLI_PORT_E.\n+ */\n+union cvmx_dpi_sli_prtx_cfg {\n+\tu64 u64;\n+\tstruct cvmx_dpi_sli_prtx_cfg_s {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 ncbsel : 1;\n+\t\tu64 reserved_25_27 : 3;\n+\t\tu64 halt : 1;\n+\t\tu64 qlm_cfg : 4;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 rd_mode : 1;\n+\t\tu64 reserved_15_15 : 1;\n+\t\tu64 molr : 7;\n+\t\tu64 mps_lim : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 mps : 1;\n+\t\tu64 mrrs_lim : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 mrrs : 2;\n+\t} s;\n+\tstruct cvmx_dpi_sli_prtx_cfg_cn61xx {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 halt : 1;\n+\t\tu64 qlm_cfg : 4;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 rd_mode : 1;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 molr : 6;\n+\t\tu64 mps_lim : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 mps : 1;\n+\t\tu64 mrrs_lim : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 mrrs : 2;\n+\t} cn61xx;\n+\tstruct cvmx_dpi_sli_prtx_cfg_cn63xx {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 halt : 1;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 qlm_cfg : 1;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 rd_mode : 1;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 molr : 6;\n+\t\tu64 mps_lim : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 mps : 1;\n+\t\tu64 mrrs_lim : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 mrrs : 2;\n+\t} cn63xx;\n+\tstruct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;\n+\tstruct cvmx_dpi_sli_prtx_cfg_cn61xx cn66xx;\n+\tstruct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;\n+\tstruct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;\n+\tstruct cvmx_dpi_sli_prtx_cfg_cn70xx {\n+\t\tu64 reserved_25_63 : 39;\n+\t\tu64 halt : 1;\n+\t\tu64 reserved_17_23 : 7;\n+\t\tu64 rd_mode : 1;\n+\t\tu64 reserved_14_15 : 2;\n+\t\tu64 molr : 6;\n+\t\tu64 mps_lim : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 mps : 1;\n+\t\tu64 mrrs_lim : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 mrrs : 2;\n+\t} cn70xx;\n+\tstruct cvmx_dpi_sli_prtx_cfg_cn70xx cn70xxp1;\n+\tstruct cvmx_dpi_sli_prtx_cfg_cn73xx {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 ncbsel : 1;\n+\t\tu64 reserved_25_27 : 3;\n+\t\tu64 halt : 1;\n+\t\tu64 reserved_21_23 : 3;\n+\t\tu64 qlm_cfg : 1;\n+\t\tu64 reserved_17_19 : 3;\n+\t\tu64 rd_mode : 1;\n+\t\tu64 reserved_15_15 : 1;\n+\t\tu64 molr : 7;\n+\t\tu64 mps_lim : 1;\n+\t\tu64 reserved_5_6 : 2;\n+\t\tu64 mps : 1;\n+\t\tu64 mrrs_lim : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 mrrs : 2;\n+\t} cn73xx;\n+\tstruct cvmx_dpi_sli_prtx_cfg_cn73xx cn78xx;\n+\tstruct cvmx_dpi_sli_prtx_cfg_cn73xx cn78xxp1;\n+\tstruct cvmx_dpi_sli_prtx_cfg_cn61xx cnf71xx;\n+\tstruct cvmx_dpi_sli_prtx_cfg_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_sli_prtx_cfg cvmx_dpi_sli_prtx_cfg_t;\n+\n+/**\n+ * cvmx_dpi_sli_prt#_err\n+ *\n+ * This register logs the address associated with the reported SLI error response.\n+ * Indexed by SLI_PORT_E.\n+ */\n+union cvmx_dpi_sli_prtx_err {\n+\tu64 u64;\n+\tstruct cvmx_dpi_sli_prtx_err_s {\n+\t\tu64 addr : 61;\n+\t\tu64 reserved_0_2 : 3;\n+\t} s;\n+\tstruct cvmx_dpi_sli_prtx_err_s cn61xx;\n+\tstruct cvmx_dpi_sli_prtx_err_s cn63xx;\n+\tstruct cvmx_dpi_sli_prtx_err_s cn63xxp1;\n+\tstruct cvmx_dpi_sli_prtx_err_s cn66xx;\n+\tstruct cvmx_dpi_sli_prtx_err_s cn68xx;\n+\tstruct cvmx_dpi_sli_prtx_err_s cn68xxp1;\n+\tstruct cvmx_dpi_sli_prtx_err_s cn70xx;\n+\tstruct cvmx_dpi_sli_prtx_err_s cn70xxp1;\n+\tstruct cvmx_dpi_sli_prtx_err_s cn73xx;\n+\tstruct cvmx_dpi_sli_prtx_err_s cn78xx;\n+\tstruct cvmx_dpi_sli_prtx_err_s cn78xxp1;\n+\tstruct cvmx_dpi_sli_prtx_err_s cnf71xx;\n+\tstruct cvmx_dpi_sli_prtx_err_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_sli_prtx_err cvmx_dpi_sli_prtx_err_t;\n+\n+/**\n+ * cvmx_dpi_sli_prt#_err_info\n+ *\n+ * This register logs information associated with the reported SLI error response.\n+ * Indexed by SLI_PORT_E.\n+ */\n+union cvmx_dpi_sli_prtx_err_info {\n+\tu64 u64;\n+\tstruct cvmx_dpi_sli_prtx_err_info_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 lock : 1;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 type : 1;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 reqq : 3;\n+\t} s;\n+\tstruct cvmx_dpi_sli_prtx_err_info_s cn61xx;\n+\tstruct cvmx_dpi_sli_prtx_err_info_s cn63xx;\n+\tstruct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;\n+\tstruct cvmx_dpi_sli_prtx_err_info_s cn66xx;\n+\tstruct cvmx_dpi_sli_prtx_err_info_s cn68xx;\n+\tstruct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;\n+\tstruct cvmx_dpi_sli_prtx_err_info_s cn70xx;\n+\tstruct cvmx_dpi_sli_prtx_err_info_s cn70xxp1;\n+\tstruct cvmx_dpi_sli_prtx_err_info_cn73xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 pvf : 16;\n+\t\tu64 reserved_9_15 : 7;\n+\t\tu64 lock : 1;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 type : 1;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 reqq : 3;\n+\t} cn73xx;\n+\tstruct cvmx_dpi_sli_prtx_err_info_cn73xx cn78xx;\n+\tstruct cvmx_dpi_sli_prtx_err_info_cn78xxp1 {\n+\t\tu64 reserved_23_63 : 41;\n+\t\tu64 vf : 7;\n+\t\tu64 reserved_9_15 : 7;\n+\t\tu64 lock : 1;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 type : 1;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 reqq : 3;\n+\t} cn78xxp1;\n+\tstruct cvmx_dpi_sli_prtx_err_info_s cnf71xx;\n+\tstruct cvmx_dpi_sli_prtx_err_info_cn73xx cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_sli_prtx_err_info cvmx_dpi_sli_prtx_err_info_t;\n+\n+/**\n+ * cvmx_dpi_srio_rx_bell#\n+ *\n+ * Reading this register pops an entry off the corresponding SRIO RX doorbell FIFO.\n+ * The chip supports 16 FIFOs per SRIO interface for a total of 32 FIFOs/Registers.\n+ * The MSB of the registers indicates the MAC while the 4 LSBs indicate the FIFO.\n+ * Information on the doorbell allocation can be found in SRIO()_RX_BELL_CTRL.\n+ */\n+union cvmx_dpi_srio_rx_bellx {\n+\tu64 u64;\n+\tstruct cvmx_dpi_srio_rx_bellx_s {\n+\t\tu64 reserved_48_63 : 16;\n+\t\tu64 data : 16;\n+\t\tu64 sid : 16;\n+\t\tu64 count : 8;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 dest_id : 1;\n+\t\tu64 id16 : 1;\n+\t\tu64 reserved_2_2 : 1;\n+\t\tu64 dpriority : 2;\n+\t} s;\n+\tstruct cvmx_dpi_srio_rx_bellx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_srio_rx_bellx cvmx_dpi_srio_rx_bellx_t;\n+\n+/**\n+ * cvmx_dpi_srio_rx_bell_seq#\n+ *\n+ * This register contains the value of the sequence counter when the doorbell\n+ * was received and a shadow copy of the Bell FIFO Count that can be read without\n+ * emptying the FIFO.  This register must be read prior to corresponding\n+ * DPI_SRIO_RX_BELL register to link the doorbell and sequence number.\n+ *\n+ * Information on the Doorbell Allocation can be found in SRIO()_RX_BELL_CTRL.\n+ */\n+union cvmx_dpi_srio_rx_bell_seqx {\n+\tu64 u64;\n+\tstruct cvmx_dpi_srio_rx_bell_seqx_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 count : 8;\n+\t\tu64 sid : 32;\n+\t} s;\n+\tstruct cvmx_dpi_srio_rx_bell_seqx_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_srio_rx_bell_seqx cvmx_dpi_srio_rx_bell_seqx_t;\n+\n+/**\n+ * cvmx_dpi_swa_q_vmid\n+ *\n+ * Not used.\n+ *\n+ */\n+union cvmx_dpi_swa_q_vmid {\n+\tu64 u64;\n+\tstruct cvmx_dpi_swa_q_vmid_s {\n+\t\tu64 vmid7 : 8;\n+\t\tu64 vmid6 : 8;\n+\t\tu64 vmid5 : 8;\n+\t\tu64 vmid4 : 8;\n+\t\tu64 vmid3 : 8;\n+\t\tu64 vmid2 : 8;\n+\t\tu64 vmid1 : 8;\n+\t\tu64 vmid0 : 8;\n+\t} s;\n+\tstruct cvmx_dpi_swa_q_vmid_s cn73xx;\n+\tstruct cvmx_dpi_swa_q_vmid_s cn78xx;\n+\tstruct cvmx_dpi_swa_q_vmid_s cn78xxp1;\n+\tstruct cvmx_dpi_swa_q_vmid_s cnf75xx;\n+};\n+\n+typedef union cvmx_dpi_swa_q_vmid cvmx_dpi_swa_q_vmid_t;\n+\n+#endif\n",
    "prefixes": [
        "v1",
        "08/50"
    ]
}