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GET /api/patches/1414987/?format=api
{ "id": 1414987, "url": "http://patchwork.ozlabs.org/api/patches/1414987/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-16-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-16-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:37", "name": "[v1,15/50] mips: octeon: Add cvmx-mio-defs.h header file", "commit_ref": "779f25eee5b1f3e30cf2a4b6441e41d7c9718d4f", "pull_url": null, "state": "accepted", "archived": false, "hash": "439373fb62444652e3c055c02cee8c5a11def25d", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-16-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1414987/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1414987/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=nrGMDTCU;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4Cswff2Cf8z9sTL\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:07:38 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 624C782771;\n\tFri, 11 Dec 2020 17:06:52 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 1AE7382749; Fri, 11 Dec 2020 17:06:35 +0100 (CET)", "from mx2.mailbox.org (mx2.mailbox.org [80.241.60.215])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id B55A48261E\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:21 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id 848F7A0BBD;\n Fri, 11 Dec 2020 17:06:21 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter03.heinlein-hosting.de (spamfilter03.heinlein-hosting.de\n [80.241.56.117]) (amavisd-new, port 10030)\n with ESMTP id 1wSNfkiwkPmU; Fri, 11 Dec 2020 17:06:17 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702812;\n\tbh=VOxgdWH4rmD56AFOU5Fyxa1EIsssqhyQbDnvFcW76rA=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=nrGMDTCUzeZEdEUOIBjFaFDOvSoNtf/hd0fAvADtTe1bDKnAQyygrfn3p7ysyGdRo\n\t 0EAtQian7v/F/ykaCKnelSDeuI31lPpv1p/gYC+wPAERfxHklvZyDbZr4Y9sUJdUux\n\t 6d1dZNtfPXUwsp/K+DO0r9/3Pga0KzBIpPFwFzeztOd8GSNn3Nghe+lS1MLMQmuo93\n\t MZsIDhzCQYVfq535JrcM/gzowdDy7gCUu4nXYmqFHoOr5MrY4nDBVT5Ox1TtPNxIN9\n\t 2ngawAtoxsCc9MOajohxvMFpanuvhgyHRKGO/sOarTl84mbnrd6bkALozJ6Kvp+AKg\n\t LYrJ7PxWdClsQ==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 15/50] mips: octeon: Add cvmx-mio-defs.h header file", "Date": "Fri, 11 Dec 2020 17:05:37 +0100", "Message-Id": "<20201211160612.1498780-16-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "*", "X-Rspamd-Score": "0.44 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "7F0FF188D", "X-Rspamd-UID": "383557", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-mio-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-mio-defs.h | 353 ++++++++++++++++++\n 1 file changed, 353 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-mio-defs.h", "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-mio-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-mio-defs.h\nnew file mode 100644\nindex 0000000000..23a18be54e\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-mio-defs.h\n@@ -0,0 +1,353 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ */\n+\n+#ifndef __CVMX_MIO_DEFS_H__\n+#define __CVMX_MIO_DEFS_H__\n+\n+#define CVMX_MIO_PTP_CLOCK_CFG\t (0x0001070000000F00ull)\n+#define CVMX_MIO_PTP_EVT_CNT\t (0x0001070000000F28ull)\n+#define CVMX_MIO_RST_BOOT\t (0x0001180000001600ull)\n+#define CVMX_MIO_RST_CTLX(offset) (0x0001180000001618ull + ((offset) & 1))\n+#define CVMX_MIO_QLMX_CFG(offset) (0x0001180000001590ull + ((offset) & 7) * 8)\n+\n+/**\n+ * cvmx_mio_ptp_clock_cfg\n+ *\n+ * This register configures the timestamp architecture.\n+ *\n+ */\n+union cvmx_mio_ptp_clock_cfg {\n+\tu64 u64;\n+\tstruct cvmx_mio_ptp_clock_cfg_s {\n+\t\tu64 reserved_40_63 : 24;\n+\t\tu64 ext_clk_edge : 2;\n+\t\tu64 ckout_out4 : 1;\n+\t\tu64 pps_out : 5;\n+\t\tu64 pps_inv : 1;\n+\t\tu64 pps_en : 1;\n+\t\tu64 ckout_out : 4;\n+\t\tu64 ckout_inv : 1;\n+\t\tu64 ckout_en : 1;\n+\t\tu64 evcnt_in : 6;\n+\t\tu64 evcnt_edge : 1;\n+\t\tu64 evcnt_en : 1;\n+\t\tu64 tstmp_in : 6;\n+\t\tu64 tstmp_edge : 1;\n+\t\tu64 tstmp_en : 1;\n+\t\tu64 ext_clk_in : 6;\n+\t\tu64 ext_clk_en : 1;\n+\t\tu64 ptp_en : 1;\n+\t} s;\n+\tstruct cvmx_mio_ptp_clock_cfg_cn61xx {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 pps : 1;\n+\t\tu64 ckout : 1;\n+\t\tu64 ext_clk_edge : 2;\n+\t\tu64 ckout_out4 : 1;\n+\t\tu64 pps_out : 5;\n+\t\tu64 pps_inv : 1;\n+\t\tu64 pps_en : 1;\n+\t\tu64 ckout_out : 4;\n+\t\tu64 ckout_inv : 1;\n+\t\tu64 ckout_en : 1;\n+\t\tu64 evcnt_in : 6;\n+\t\tu64 evcnt_edge : 1;\n+\t\tu64 evcnt_en : 1;\n+\t\tu64 tstmp_in : 6;\n+\t\tu64 tstmp_edge : 1;\n+\t\tu64 tstmp_en : 1;\n+\t\tu64 ext_clk_in : 6;\n+\t\tu64 ext_clk_en : 1;\n+\t\tu64 ptp_en : 1;\n+\t} cn61xx;\n+\tstruct cvmx_mio_ptp_clock_cfg_cn63xx {\n+\t\tu64 reserved_24_63 : 40;\n+\t\tu64 evcnt_in : 6;\n+\t\tu64 evcnt_edge : 1;\n+\t\tu64 evcnt_en : 1;\n+\t\tu64 tstmp_in : 6;\n+\t\tu64 tstmp_edge : 1;\n+\t\tu64 tstmp_en : 1;\n+\t\tu64 ext_clk_in : 6;\n+\t\tu64 ext_clk_en : 1;\n+\t\tu64 ptp_en : 1;\n+\t} cn63xx;\n+\tstruct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1;\n+\tstruct cvmx_mio_ptp_clock_cfg_s cn66xx;\n+\tstruct cvmx_mio_ptp_clock_cfg_cn61xx cn68xx;\n+\tstruct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1;\n+\tstruct cvmx_mio_ptp_clock_cfg_cn70xx {\n+\t\tu64 reserved_42_63 : 22;\n+\t\tu64 ckout : 1;\n+\t\tu64 pps : 1;\n+\t\tu64 ext_clk_edge : 2;\n+\t\tu64 reserved_32_37 : 6;\n+\t\tu64 pps_inv : 1;\n+\t\tu64 pps_en : 1;\n+\t\tu64 reserved_26_29 : 4;\n+\t\tu64 ckout_inv : 1;\n+\t\tu64 ckout_en : 1;\n+\t\tu64 evcnt_in : 6;\n+\t\tu64 evcnt_edge : 1;\n+\t\tu64 evcnt_en : 1;\n+\t\tu64 tstmp_in : 6;\n+\t\tu64 tstmp_edge : 1;\n+\t\tu64 tstmp_en : 1;\n+\t\tu64 ext_clk_in : 6;\n+\t\tu64 ext_clk_en : 1;\n+\t\tu64 ptp_en : 1;\n+\t} cn70xx;\n+\tstruct cvmx_mio_ptp_clock_cfg_cn70xx cn70xxp1;\n+\tstruct cvmx_mio_ptp_clock_cfg_cn70xx cn73xx;\n+\tstruct cvmx_mio_ptp_clock_cfg_cn70xx cn78xx;\n+\tstruct cvmx_mio_ptp_clock_cfg_cn70xx cn78xxp1;\n+\tstruct cvmx_mio_ptp_clock_cfg_cn61xx cnf71xx;\n+\tstruct cvmx_mio_ptp_clock_cfg_cn70xx cnf75xx;\n+};\n+\n+typedef union cvmx_mio_ptp_clock_cfg cvmx_mio_ptp_clock_cfg_t;\n+\n+/**\n+ * cvmx_mio_ptp_evt_cnt\n+ *\n+ * This register contains the PTP event counter.\n+ *\n+ */\n+union cvmx_mio_ptp_evt_cnt {\n+\tu64 u64;\n+\tstruct cvmx_mio_ptp_evt_cnt_s {\n+\t\tu64 cntr : 64;\n+\t} s;\n+\tstruct cvmx_mio_ptp_evt_cnt_s cn61xx;\n+\tstruct cvmx_mio_ptp_evt_cnt_s cn63xx;\n+\tstruct cvmx_mio_ptp_evt_cnt_s cn63xxp1;\n+\tstruct cvmx_mio_ptp_evt_cnt_s cn66xx;\n+\tstruct cvmx_mio_ptp_evt_cnt_s cn68xx;\n+\tstruct cvmx_mio_ptp_evt_cnt_s cn68xxp1;\n+\tstruct cvmx_mio_ptp_evt_cnt_s cn70xx;\n+\tstruct cvmx_mio_ptp_evt_cnt_s cn70xxp1;\n+\tstruct cvmx_mio_ptp_evt_cnt_s cn73xx;\n+\tstruct cvmx_mio_ptp_evt_cnt_s cn78xx;\n+\tstruct cvmx_mio_ptp_evt_cnt_s cn78xxp1;\n+\tstruct cvmx_mio_ptp_evt_cnt_s cnf71xx;\n+\tstruct cvmx_mio_ptp_evt_cnt_s cnf75xx;\n+};\n+\n+typedef union cvmx_mio_ptp_evt_cnt cvmx_mio_ptp_evt_cnt_t;\n+\n+/**\n+ * cvmx_mio_rst_boot\n+ *\n+ * Notes:\n+ * JTCSRDIS, EJTAGDIS, ROMEN reset to 1 in authentik mode; in all other modes they reset to 0.\n+ *\n+ */\n+union cvmx_mio_rst_boot {\n+\tu64 u64;\n+\tstruct cvmx_mio_rst_boot_s {\n+\t\tu64 chipkill : 1;\n+\t\tu64 jtcsrdis : 1;\n+\t\tu64 ejtagdis : 1;\n+\t\tu64 romen : 1;\n+\t\tu64 ckill_ppdis : 1;\n+\t\tu64 jt_tstmode : 1;\n+\t\tu64 reserved_50_57 : 8;\n+\t\tu64 lboot_ext : 2;\n+\t\tu64 reserved_44_47 : 4;\n+\t\tu64 qlm4_spd : 4;\n+\t\tu64 qlm3_spd : 4;\n+\t\tu64 c_mul : 6;\n+\t\tu64 pnr_mul : 6;\n+\t\tu64 qlm2_spd : 4;\n+\t\tu64 qlm1_spd : 4;\n+\t\tu64 qlm0_spd : 4;\n+\t\tu64 lboot : 10;\n+\t\tu64 rboot : 1;\n+\t\tu64 rboot_pin : 1;\n+\t} s;\n+\tstruct cvmx_mio_rst_boot_cn61xx {\n+\t\tu64 chipkill : 1;\n+\t\tu64 jtcsrdis : 1;\n+\t\tu64 ejtagdis : 1;\n+\t\tu64 romen : 1;\n+\t\tu64 ckill_ppdis : 1;\n+\t\tu64 jt_tstmode : 1;\n+\t\tu64 reserved_50_57 : 8;\n+\t\tu64 lboot_ext : 2;\n+\t\tu64 reserved_36_47 : 12;\n+\t\tu64 c_mul : 6;\n+\t\tu64 pnr_mul : 6;\n+\t\tu64 qlm2_spd : 4;\n+\t\tu64 qlm1_spd : 4;\n+\t\tu64 qlm0_spd : 4;\n+\t\tu64 lboot : 10;\n+\t\tu64 rboot : 1;\n+\t\tu64 rboot_pin : 1;\n+\t} cn61xx;\n+\tstruct cvmx_mio_rst_boot_cn63xx {\n+\t\tu64 reserved_36_63 : 28;\n+\t\tu64 c_mul : 6;\n+\t\tu64 pnr_mul : 6;\n+\t\tu64 qlm2_spd : 4;\n+\t\tu64 qlm1_spd : 4;\n+\t\tu64 qlm0_spd : 4;\n+\t\tu64 lboot : 10;\n+\t\tu64 rboot : 1;\n+\t\tu64 rboot_pin : 1;\n+\t} cn63xx;\n+\tstruct cvmx_mio_rst_boot_cn63xx cn63xxp1;\n+\tstruct cvmx_mio_rst_boot_cn66xx {\n+\t\tu64 chipkill : 1;\n+\t\tu64 jtcsrdis : 1;\n+\t\tu64 ejtagdis : 1;\n+\t\tu64 romen : 1;\n+\t\tu64 ckill_ppdis : 1;\n+\t\tu64 reserved_50_58 : 9;\n+\t\tu64 lboot_ext : 2;\n+\t\tu64 reserved_36_47 : 12;\n+\t\tu64 c_mul : 6;\n+\t\tu64 pnr_mul : 6;\n+\t\tu64 qlm2_spd : 4;\n+\t\tu64 qlm1_spd : 4;\n+\t\tu64 qlm0_spd : 4;\n+\t\tu64 lboot : 10;\n+\t\tu64 rboot : 1;\n+\t\tu64 rboot_pin : 1;\n+\t} cn66xx;\n+\tstruct cvmx_mio_rst_boot_cn68xx {\n+\t\tu64 reserved_59_63 : 5;\n+\t\tu64 jt_tstmode : 1;\n+\t\tu64 reserved_44_57 : 14;\n+\t\tu64 qlm4_spd : 4;\n+\t\tu64 qlm3_spd : 4;\n+\t\tu64 c_mul : 6;\n+\t\tu64 pnr_mul : 6;\n+\t\tu64 qlm2_spd : 4;\n+\t\tu64 qlm1_spd : 4;\n+\t\tu64 qlm0_spd : 4;\n+\t\tu64 lboot : 10;\n+\t\tu64 rboot : 1;\n+\t\tu64 rboot_pin : 1;\n+\t} cn68xx;\n+\tstruct cvmx_mio_rst_boot_cn68xxp1 {\n+\t\tu64 reserved_44_63 : 20;\n+\t\tu64 qlm4_spd : 4;\n+\t\tu64 qlm3_spd : 4;\n+\t\tu64 c_mul : 6;\n+\t\tu64 pnr_mul : 6;\n+\t\tu64 qlm2_spd : 4;\n+\t\tu64 qlm1_spd : 4;\n+\t\tu64 qlm0_spd : 4;\n+\t\tu64 lboot : 10;\n+\t\tu64 rboot : 1;\n+\t\tu64 rboot_pin : 1;\n+\t} cn68xxp1;\n+\tstruct cvmx_mio_rst_boot_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_mio_rst_boot cvmx_mio_rst_boot_t;\n+\n+/**\n+ * cvmx_mio_rst_ctl#\n+ *\n+ * Notes:\n+ * GEN1_Only mode is enabled for PEM0 when QLM1_SPD[0] is set or when sclk < 550Mhz.\n+ * GEN1_Only mode is enabled for PEM1 when QLM1_SPD[1] is set or when sclk < 550Mhz.\n+ */\n+union cvmx_mio_rst_ctlx {\n+\tu64 u64;\n+\tstruct cvmx_mio_rst_ctlx_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 in_rev_ln : 1;\n+\t\tu64 rev_lanes : 1;\n+\t\tu64 gen1_only : 1;\n+\t\tu64 prst_link : 1;\n+\t\tu64 rst_done : 1;\n+\t\tu64 rst_link : 1;\n+\t\tu64 host_mode : 1;\n+\t\tu64 prtmode : 2;\n+\t\tu64 rst_drv : 1;\n+\t\tu64 rst_rcv : 1;\n+\t\tu64 rst_chip : 1;\n+\t\tu64 rst_val : 1;\n+\t} s;\n+\tstruct cvmx_mio_rst_ctlx_s cn61xx;\n+\tstruct cvmx_mio_rst_ctlx_cn63xx {\n+\t\tu64 reserved_10_63 : 54;\n+\t\tu64 prst_link : 1;\n+\t\tu64 rst_done : 1;\n+\t\tu64 rst_link : 1;\n+\t\tu64 host_mode : 1;\n+\t\tu64 prtmode : 2;\n+\t\tu64 rst_drv : 1;\n+\t\tu64 rst_rcv : 1;\n+\t\tu64 rst_chip : 1;\n+\t\tu64 rst_val : 1;\n+\t} cn63xx;\n+\tstruct cvmx_mio_rst_ctlx_cn63xxp1 {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 rst_done : 1;\n+\t\tu64 rst_link : 1;\n+\t\tu64 host_mode : 1;\n+\t\tu64 prtmode : 2;\n+\t\tu64 rst_drv : 1;\n+\t\tu64 rst_rcv : 1;\n+\t\tu64 rst_chip : 1;\n+\t\tu64 rst_val : 1;\n+\t} cn63xxp1;\n+\tstruct cvmx_mio_rst_ctlx_cn63xx cn66xx;\n+\tstruct cvmx_mio_rst_ctlx_cn63xx cn68xx;\n+\tstruct cvmx_mio_rst_ctlx_cn63xx cn68xxp1;\n+\tstruct cvmx_mio_rst_ctlx_s cnf71xx;\n+};\n+\n+typedef union cvmx_mio_rst_ctlx cvmx_mio_rst_ctlx_t;\n+\n+/**\n+ * cvmx_mio_qlm#_cfg\n+ *\n+ * Notes:\n+ * Certain QLM_SPD is valid only for certain QLM_CFG configuration, refer to HRM for valid\n+ * combinations. These csrs are reset only on COLD_RESET. The Reset values for QLM_SPD and QLM_CFG\n+ * are as follows: MIO_QLM0_CFG SPD=F, CFG=2 SGMII (AGX0)\n+ * MIO_QLM1_CFG SPD=0, CFG=1 PCIE 2x1 (PEM0/PEM1)\n+ */\n+union cvmx_mio_qlmx_cfg {\n+\tu64 u64;\n+\tstruct cvmx_mio_qlmx_cfg_s {\n+\t\tu64 reserved_15_63 : 49;\n+\t\tu64 prtmode : 1;\n+\t\tu64 reserved_12_13 : 2;\n+\t\tu64 qlm_spd : 4;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 qlm_cfg : 4;\n+\t} s;\n+\tstruct cvmx_mio_qlmx_cfg_cn61xx {\n+\t\tu64 reserved_15_63 : 49;\n+\t\tu64 prtmode : 1;\n+\t\tu64 reserved_12_13 : 2;\n+\t\tu64 qlm_spd : 4;\n+\t\tu64 reserved_2_7 : 6;\n+\t\tu64 qlm_cfg : 2;\n+\t} cn61xx;\n+\tstruct cvmx_mio_qlmx_cfg_cn66xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 qlm_spd : 4;\n+\t\tu64 reserved_4_7 : 4;\n+\t\tu64 qlm_cfg : 4;\n+\t} cn66xx;\n+\tstruct cvmx_mio_qlmx_cfg_cn68xx {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 qlm_spd : 4;\n+\t\tu64 reserved_3_7 : 5;\n+\t\tu64 qlm_cfg : 3;\n+\t} cn68xx;\n+\tstruct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1;\n+\tstruct cvmx_mio_qlmx_cfg_cn61xx cnf71xx;\n+};\n+\n+typedef union cvmx_mio_qlmx_cfg cvmx_mio_qlmx_cfg_t;\n+\n+#endif\n", "prefixes": [ "v1", "15/50" ] }