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GET /api/patches/1414986/?format=api
{ "id": 1414986, "url": "http://patchwork.ozlabs.org/api/patches/1414986/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-15-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-15-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:36", "name": "[v1,14/50] mips: octeon: Add cvmx-l2c-defs.h header file", "commit_ref": "cae9e5763f3715879b752ea542262b4b10ec063f", "pull_url": null, "state": "accepted", "archived": false, "hash": "571729b158f943fe429b9e3ea40d0b5c408cc734", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-15-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1414986/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1414986/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=KfO8na5t;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4CswfN5CjKz9sR4\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:07:24 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id BD5E78264E;\n\tFri, 11 Dec 2020 17:06:48 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 1E92282753; Fri, 11 Dec 2020 17:06:33 +0100 (CET)", "from mx2.mailbox.org (mx2.mailbox.org [80.241.60.215])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 31320825DF\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:21 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id E401EA0C01;\n Fri, 11 Dec 2020 17:06:20 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter05.heinlein-hosting.de (spamfilter05.heinlein-hosting.de\n [80.241.56.123]) (amavisd-new, port 10030)\n with ESMTP id OIvhdyww4MO0; Fri, 11 Dec 2020 17:06:17 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702809;\n\tbh=epO4ZhPlBwxGdf7l+KOUyerqieFJB64gRDnOuPZwsn0=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=KfO8na5tVj0cGCi9LRS5Z0AF7wdjWdzz/3gYqrfVZK4OFmsu1ZfTRp0cM5ZurJ7Nm\n\t mWiAGtj3NbRez1dC7Ezy1r0pKlEknJJCCOdRA3yxZV6Rg8pS0e9Pk5OGrzhXiWLnN8\n\t uOZ7KuySGJuE2KzLElABqxlyTh+fVzit2HvvdtPRBvqJc4ytBJ3AgFcbJdKWZ0yf/Q\n\t 5/M3OJg/eJuKMmCimVzofv9q9kF0i6XVKJs9UH1EJQUwr04dRT+FwxfQcBmLzJNhFd\n\t JBZp8Q6N0KRSSPxcgkNMN+ZdkEaWPNogeeNFE6bATm26zIbOKwUF7Npbzq91oTtlIp\n\t yL1cII3buAxIg==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 14/50] mips: octeon: Add cvmx-l2c-defs.h header file", "Date": "Fri, 11 Dec 2020 17:05:36 +0100", "Message-Id": "<20201211160612.1498780-15-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "*", "X-Rspamd-Score": "0.13 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "D5B791893", "X-Rspamd-UID": "3beccd", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-l2c-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-l2c-defs.h | 172 ++++++++++++++++++\n 1 file changed, 172 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-l2c-defs.h", "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-l2c-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-l2c-defs.h\nnew file mode 100644\nindex 0000000000..7fddcd6dfb\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-l2c-defs.h\n@@ -0,0 +1,172 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ */\n+\n+#ifndef __CVMX_L2C_DEFS_H_\n+#define __CVMX_L2C_DEFS_H_\n+\n+#define CVMX_L2C_CFG 0x0001180080000000ull\n+#define CVMX_L2C_CTL 0x0001180080800000ull\n+\n+/*\n+ * Mapping is done starting from 0x11800.80000000\n+ * Use _REL for relative mapping\n+ */\n+#define CVMX_L2C_CTL_REL\t 0x00800000\n+#define CVMX_L2C_BIG_CTL_REL\t 0x00800030\n+#define CVMX_L2C_TADX_INT_REL(i) (0x00a00028 + (((i) & 7) * 0x40000))\n+#define CVMX_L2C_MCIX_INT_REL(i) (0x00c00028 + (((i) & 3) * 0x40000))\n+\n+/**\n+ * cvmx_l2c_cfg\n+ *\n+ * Specify the RSL base addresses for the block\n+ *\n+ * L2C_CFG = L2C Configuration\n+ *\n+ * Description:\n+ */\n+union cvmx_l2c_cfg {\n+\tu64 u64;\n+\tstruct cvmx_l2c_cfg_s {\n+\t\tu64 reserved_20_63 : 44;\n+\t\tu64 bstrun : 1;\n+\t\tu64 lbist : 1;\n+\t\tu64 xor_bank : 1;\n+\t\tu64 dpres1 : 1;\n+\t\tu64 dpres0 : 1;\n+\t\tu64 dfill_dis : 1;\n+\t\tu64 fpexp : 4;\n+\t\tu64 fpempty : 1;\n+\t\tu64 fpen : 1;\n+\t\tu64 idxalias : 1;\n+\t\tu64 mwf_crd : 4;\n+\t\tu64 rsp_arb_mode : 1;\n+\t\tu64 rfb_arb_mode : 1;\n+\t\tu64 lrf_arb_mode : 1;\n+\t} s;\n+};\n+\n+/**\n+ * cvmx_l2c_ctl\n+ *\n+ * L2C_CTL = L2C Control\n+ *\n+ *\n+ * Notes:\n+ * (1) If MAXVAB is != 0, VAB_THRESH should be less than MAXVAB.\n+ *\n+ * (2) L2DFDBE and L2DFSBE allows software to generate L2DSBE, L2DDBE, VBFSBE,\n+ * and VBFDBE errors for the purposes of testing error handling code. When\n+ * one (or both) of these bits are set a PL2 which misses in the L2 will fill\n+ * with the appropriate error in the first 2 OWs of the fill. Software can\n+ * determine which OW pair gets the error by choosing the desired fill order\n+ * (address<6:5>). A PL2 which hits in the L2 will not inject any errors.\n+ * Therefore sending a WBIL2 prior to the PL2 is recommended to make a miss\n+ * likely (if multiple processors are involved software must be careful to be\n+ * sure no other processor or IO device can bring the block into the L2).\n+ *\n+ * To generate a VBFSBE or VBFDBE, software must first get the cache block\n+ * into the cache with an error using a PL2 which misses the L2. Then a\n+ * store partial to a portion of the cache block without the error must\n+ * change the block to dirty. Then, a subsequent WBL2/WBIL2/victim will\n+ * trigger the VBFSBE/VBFDBE error.\n+ */\n+union cvmx_l2c_ctl {\n+\tu64 u64;\n+\tstruct cvmx_l2c_ctl_s {\n+\t\tu64 reserved_29_63 : 35;\n+\t\tu64 rdf_fast : 1;\n+\t\tu64 disstgl2i : 1;\n+\t\tu64 l2dfsbe : 1;\n+\t\tu64 l2dfdbe : 1;\n+\t\tu64 discclk : 1;\n+\t\tu64 maxvab : 4;\n+\t\tu64 maxlfb : 4;\n+\t\tu64 rsp_arb_mode : 1;\n+\t\tu64 xmc_arb_mode : 1;\n+\t\tu64 reserved_2_13 : 12;\n+\t\tu64 disecc : 1;\n+\t\tu64 disidxalias : 1;\n+\t} s;\n+\n+\tstruct cvmx_l2c_ctl_cn73xx {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 ocla_qos : 3;\n+\t\tu64 reserved_28_28 : 1;\n+\t\tu64 disstgl2i : 1;\n+\t\tu64 reserved_25_26 : 2;\n+\t\tu64 discclk : 1;\n+\t\tu64 reserved_16_23 : 8;\n+\t\tu64 rsp_arb_mode : 1;\n+\t\tu64 xmc_arb_mode : 1;\n+\t\tu64 rdf_cnt : 8;\n+\t\tu64 reserved_4_5 : 2;\n+\t\tu64 disldwb : 1;\n+\t\tu64 dissblkdty : 1;\n+\t\tu64 disecc : 1;\n+\t\tu64 disidxalias : 1;\n+\t} cn73xx;\n+\n+\tstruct cvmx_l2c_ctl_cn73xx cn78xx;\n+};\n+\n+/**\n+ * cvmx_l2c_big_ctl\n+ *\n+ * L2C_BIG_CTL = L2C Big memory control register\n+ *\n+ *\n+ * Notes:\n+ * (1) BIGRD interrupts can occur during normal operation as the PP's are\n+ * allowed to prefetch to non-existent memory locations. Therefore,\n+ * BIGRD is for informational purposes only.\n+ *\n+ * (2) When HOLEWR/BIGWR blocks a store L2C_VER_ID, L2C_VER_PP, L2C_VER_IOB,\n+ * and L2C_VER_MSC will be loaded just like a store which is blocked by VRTWR.\n+ * Additionally, L2C_ERR_XMC will be loaded.\n+ */\n+union cvmx_l2c_big_ctl {\n+\tu64 u64;\n+\tstruct cvmx_l2c_big_ctl_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 maxdram : 4;\n+\t\tu64 reserved_0_3 : 4;\n+\t} s;\n+\tstruct cvmx_l2c_big_ctl_cn61xx {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 maxdram : 4;\n+\t\tu64 reserved_1_3 : 3;\n+\t\tu64 disable : 1;\n+\t} cn61xx;\n+\tstruct cvmx_l2c_big_ctl_cn61xx cn63xx;\n+\tstruct cvmx_l2c_big_ctl_cn61xx cn66xx;\n+\tstruct cvmx_l2c_big_ctl_cn61xx cn68xx;\n+\tstruct cvmx_l2c_big_ctl_cn61xx cn68xxp1;\n+\tstruct cvmx_l2c_big_ctl_cn70xx {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 maxdram : 4;\n+\t\tu64 reserved_1_3 : 3;\n+\t\tu64 disbig : 1;\n+\t} cn70xx;\n+\tstruct cvmx_l2c_big_ctl_cn70xx cn70xxp1;\n+\tstruct cvmx_l2c_big_ctl_cn70xx cn73xx;\n+\tstruct cvmx_l2c_big_ctl_cn70xx cn78xx;\n+\tstruct cvmx_l2c_big_ctl_cn70xx cn78xxp1;\n+\tstruct cvmx_l2c_big_ctl_cn61xx cnf71xx;\n+\tstruct cvmx_l2c_big_ctl_cn70xx cnf75xx;\n+};\n+\n+struct rlevel_byte_data {\n+\tint delay;\n+\tint loop_total;\n+\tint loop_count;\n+\tint best;\n+\tu64 bm;\n+\tint bmerrs;\n+\tint sqerrs;\n+\tint bestsq;\n+};\n+\n+#endif\n", "prefixes": [ "v1", "14/50" ] }