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GET /api/patches/1414985/?format=api
{ "id": 1414985, "url": "http://patchwork.ozlabs.org/api/patches/1414985/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-5-sr@denx.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201211160612.1498780-5-sr@denx.de>", "list_archive_url": null, "date": "2020-12-11T16:05:26", "name": "[v1,04/50] mips: octeon: Add cvmx-asxx-defs.h header file", "commit_ref": "1f659caaa577d4bca6001f7ee80adc85d7d8424c", "pull_url": null, "state": "accepted", "archived": false, "hash": "b8398b254915660325ab180db52f6fdf7105364e", "submitter": { "id": 13, "url": "http://patchwork.ozlabs.org/api/people/13/?format=api", "name": "Stefan Roese", "email": "sr@denx.de" }, "delegate": { "id": 4307, "url": "http://patchwork.ozlabs.org/api/users/4307/?format=api", "username": "danielschwierzeck", "first_name": "Daniel", "last_name": "Schwierzeck", "email": "daniel.schwierzeck@googlemail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201211160612.1498780-5-sr@denx.de/mbox/", "series": [ { "id": 220054, "url": "http://patchwork.ozlabs.org/api/series/220054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=220054", "date": "2020-12-11T16:05:23", "name": "mips: octeon: Add serdes and device helper support incl. DM PCIe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/220054/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1414985/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1414985/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=denx.de", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256\n header.s=phobos-20191101 header.b=JSjjw+C2;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=denx.de", "phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4Cswf729Zcz9sR4\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 12 Dec 2020 03:07:11 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 3902082773;\n\tFri, 11 Dec 2020 17:06:45 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id C966E826A8; Fri, 11 Dec 2020 17:06:28 +0100 (CET)", "from mx2.mailbox.org (mx2.mailbox.org [80.241.60.215])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 76DFC825DC\n for <u-boot@lists.denx.de>; Fri, 11 Dec 2020 17:06:18 +0100 (CET)", "from smtp1.mailbox.org (smtp1.mailbox.org\n [IPv6:2001:67c:2050:105:465:1:1:0])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest\n SHA256) (No client certificate requested)\n by mx2.mailbox.org (Postfix) with ESMTPS id 05D7DA0E06;\n Fri, 11 Dec 2020 17:06:17 +0100 (CET)", "from smtp1.mailbox.org ([80.241.60.240])\n by spamfilter01.heinlein-hosting.de (spamfilter01.heinlein-hosting.de\n [80.241.56.115]) (amavisd-new, port 10030)\n with ESMTP id BCwxRl54MHhf; Fri, 11 Dec 2020 17:06:14 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de;\n\ts=phobos-20191101; t=1607702805;\n\tbh=MMsnQTYz8pY+ZHVRuB04bhvFVfh7esb618v64/vYIyc=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=JSjjw+C2ME07PicCDOmtqWQlRGJod7p2k9Mhd+S/IlpiLlnI0T9djIYrw1W8/Yh8C\n\t HAMITF/MzOt92yzcmsKLbuN6Cg75Y1GBPAXg8u+snhaRe53Jk1vrTVmrTbCZ43Q1le\n\t OeX91mjC+Ps1cGpS1sOJVNOVD1HB6IP9IvjsVtIj1XouOWJHvb/dyk/eh92YefDu8l\n\t Ff3NVHOKg182CGv9zF+fiwPM8PhpScSMvmtL3ihlmN2xsjelG5O6esUkByTS0jZ/up\n\t nmcMVOK1NjIY5d3g9sABSgnL8ssy6DmOqDh0tWNWA3PSR4Z4dxygsJgNiE0+HzagZ8\n\t Y5XRSzOmj3CHg==", "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,\n SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2", "From": "Stefan Roese <sr@denx.de>", "To": "u-boot@lists.denx.de", "Cc": "daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com", "Subject": "[PATCH v1 04/50] mips: octeon: Add cvmx-asxx-defs.h header file", "Date": "Fri, 11 Dec 2020 17:05:26 +0100", "Message-Id": "<20201211160612.1498780-5-sr@denx.de>", "In-Reply-To": "<20201211160612.1498780-1-sr@denx.de>", "References": "<20201211160612.1498780-1-sr@denx.de>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-SPAM-Probability": "", "X-Rspamd-Score": "-0.71 / 15.00 / 15.00", "X-Rspamd-Queue-Id": "E1CB91882", "X-Rspamd-UID": "9a17bf", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Aaron Williams <awilliams@marvell.com>\n\nImport cvmx-asxx-defs.h header file from 2013 U-Boot. It will be used\nby the later added drivers to support PCIe and networking on the MIPS\nOcteon II / III platforms.\n\nSigned-off-by: Aaron Williams <awilliams@marvell.com>\nSigned-off-by: Stefan Roese <sr@denx.de>\n---\n\n .../mach-octeon/include/mach/cvmx-asxx-defs.h | 709 ++++++++++++++++++\n 1 file changed, 709 insertions(+)\n create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-asxx-defs.h", "diff": "diff --git a/arch/mips/mach-octeon/include/mach/cvmx-asxx-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-asxx-defs.h\nnew file mode 100644\nindex 0000000000..2af1a29d63\n--- /dev/null\n+++ b/arch/mips/mach-octeon/include/mach/cvmx-asxx-defs.h\n@@ -0,0 +1,709 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ *\n+ * Configuration and status register (CSR) type definitions for\n+ * Octeon asxx.\n+ */\n+\n+#ifndef __CVMX_ASXX_DEFS_H__\n+#define __CVMX_ASXX_DEFS_H__\n+\n+#define CVMX_ASXX_GMII_RX_CLK_SET(offset) (0x00011800B0000180ull)\n+#define CVMX_ASXX_GMII_RX_DAT_SET(offset) (0x00011800B0000188ull)\n+#define CVMX_ASXX_INT_EN(offset)\t (0x00011800B0000018ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_INT_REG(offset)\t (0x00011800B0000010ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_MII_RX_DAT_SET(offset) (0x00011800B0000190ull)\n+#define CVMX_ASXX_PRT_LOOP(offset)\t (0x00011800B0000040ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RLD_BYPASS(offset)\t (0x00011800B0000248ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RLD_BYPASS_SETTING(offset) (0x00011800B0000250ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RLD_COMP(offset)\t (0x00011800B0000220ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RLD_DATA_DRV(offset)\t (0x00011800B0000218ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RLD_FCRAM_MODE(offset) (0x00011800B0000210ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RLD_NCTL_STRONG(offset) (0x00011800B0000230ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RLD_NCTL_WEAK(offset)\t (0x00011800B0000240ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RLD_PCTL_STRONG(offset) (0x00011800B0000228ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RLD_PCTL_WEAK(offset)\t (0x00011800B0000238ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RLD_SETTING(offset)\t (0x00011800B0000258ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \\\n+\t(0x00011800B0000020ull + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)\n+#define CVMX_ASXX_RX_PRT_EN(offset) (0x00011800B0000000ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RX_WOL(offset) (0x00011800B0000100ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RX_WOL_MSK(offset) (0x00011800B0000108ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RX_WOL_POWOK(offset) (0x00011800B0000118ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_RX_WOL_SIG(offset) (0x00011800B0000110ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \\\n+\t(0x00011800B0000048ull + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)\n+#define CVMX_ASXX_TX_COMP_BYP(offset) (0x00011800B0000068ull + ((offset) & 1) * 0x8000000ull)\n+#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \\\n+\t(0x00011800B0000080ull + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)\n+#define CVMX_ASXX_TX_PRT_EN(offset) (0x00011800B0000008ull + ((offset) & 1) * 0x8000000ull)\n+\n+/**\n+ * cvmx_asx#_gmii_rx_clk_set\n+ *\n+ * ASX_GMII_RX_CLK_SET = GMII Clock delay setting\n+ *\n+ */\n+union cvmx_asxx_gmii_rx_clk_set {\n+\tu64 u64;\n+\tstruct cvmx_asxx_gmii_rx_clk_set_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 setting : 5;\n+\t} s;\n+\tstruct cvmx_asxx_gmii_rx_clk_set_s cn30xx;\n+\tstruct cvmx_asxx_gmii_rx_clk_set_s cn31xx;\n+\tstruct cvmx_asxx_gmii_rx_clk_set_s cn50xx;\n+};\n+\n+typedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t;\n+\n+/**\n+ * cvmx_asx#_gmii_rx_dat_set\n+ *\n+ * ASX_GMII_RX_DAT_SET = GMII Clock delay setting\n+ *\n+ */\n+union cvmx_asxx_gmii_rx_dat_set {\n+\tu64 u64;\n+\tstruct cvmx_asxx_gmii_rx_dat_set_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 setting : 5;\n+\t} s;\n+\tstruct cvmx_asxx_gmii_rx_dat_set_s cn30xx;\n+\tstruct cvmx_asxx_gmii_rx_dat_set_s cn31xx;\n+\tstruct cvmx_asxx_gmii_rx_dat_set_s cn50xx;\n+};\n+\n+typedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t;\n+\n+/**\n+ * cvmx_asx#_int_en\n+ *\n+ * ASX_INT_EN = Interrupt Enable\n+ *\n+ */\n+union cvmx_asxx_int_en {\n+\tu64 u64;\n+\tstruct cvmx_asxx_int_en_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 txpsh : 4;\n+\t\tu64 txpop : 4;\n+\t\tu64 ovrflw : 4;\n+\t} s;\n+\tstruct cvmx_asxx_int_en_cn30xx {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 txpsh : 3;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 txpop : 3;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 ovrflw : 3;\n+\t} cn30xx;\n+\tstruct cvmx_asxx_int_en_cn30xx cn31xx;\n+\tstruct cvmx_asxx_int_en_s cn38xx;\n+\tstruct cvmx_asxx_int_en_s cn38xxp2;\n+\tstruct cvmx_asxx_int_en_cn30xx cn50xx;\n+\tstruct cvmx_asxx_int_en_s cn58xx;\n+\tstruct cvmx_asxx_int_en_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_int_en cvmx_asxx_int_en_t;\n+\n+/**\n+ * cvmx_asx#_int_reg\n+ *\n+ * ASX_INT_REG = Interrupt Register\n+ *\n+ */\n+union cvmx_asxx_int_reg {\n+\tu64 u64;\n+\tstruct cvmx_asxx_int_reg_s {\n+\t\tu64 reserved_12_63 : 52;\n+\t\tu64 txpsh : 4;\n+\t\tu64 txpop : 4;\n+\t\tu64 ovrflw : 4;\n+\t} s;\n+\tstruct cvmx_asxx_int_reg_cn30xx {\n+\t\tu64 reserved_11_63 : 53;\n+\t\tu64 txpsh : 3;\n+\t\tu64 reserved_7_7 : 1;\n+\t\tu64 txpop : 3;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 ovrflw : 3;\n+\t} cn30xx;\n+\tstruct cvmx_asxx_int_reg_cn30xx cn31xx;\n+\tstruct cvmx_asxx_int_reg_s cn38xx;\n+\tstruct cvmx_asxx_int_reg_s cn38xxp2;\n+\tstruct cvmx_asxx_int_reg_cn30xx cn50xx;\n+\tstruct cvmx_asxx_int_reg_s cn58xx;\n+\tstruct cvmx_asxx_int_reg_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_int_reg cvmx_asxx_int_reg_t;\n+\n+/**\n+ * cvmx_asx#_mii_rx_dat_set\n+ *\n+ * ASX_MII_RX_DAT_SET = GMII Clock delay setting\n+ *\n+ */\n+union cvmx_asxx_mii_rx_dat_set {\n+\tu64 u64;\n+\tstruct cvmx_asxx_mii_rx_dat_set_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 setting : 5;\n+\t} s;\n+\tstruct cvmx_asxx_mii_rx_dat_set_s cn30xx;\n+\tstruct cvmx_asxx_mii_rx_dat_set_s cn50xx;\n+};\n+\n+typedef union cvmx_asxx_mii_rx_dat_set cvmx_asxx_mii_rx_dat_set_t;\n+\n+/**\n+ * cvmx_asx#_prt_loop\n+ *\n+ * ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins)\n+ *\n+ */\n+union cvmx_asxx_prt_loop {\n+\tu64 u64;\n+\tstruct cvmx_asxx_prt_loop_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 ext_loop : 4;\n+\t\tu64 int_loop : 4;\n+\t} s;\n+\tstruct cvmx_asxx_prt_loop_cn30xx {\n+\t\tu64 reserved_7_63 : 57;\n+\t\tu64 ext_loop : 3;\n+\t\tu64 reserved_3_3 : 1;\n+\t\tu64 int_loop : 3;\n+\t} cn30xx;\n+\tstruct cvmx_asxx_prt_loop_cn30xx cn31xx;\n+\tstruct cvmx_asxx_prt_loop_s cn38xx;\n+\tstruct cvmx_asxx_prt_loop_s cn38xxp2;\n+\tstruct cvmx_asxx_prt_loop_cn30xx cn50xx;\n+\tstruct cvmx_asxx_prt_loop_s cn58xx;\n+\tstruct cvmx_asxx_prt_loop_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_prt_loop cvmx_asxx_prt_loop_t;\n+\n+/**\n+ * cvmx_asx#_rld_bypass\n+ *\n+ * ASX_RLD_BYPASS\n+ *\n+ */\n+union cvmx_asxx_rld_bypass {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rld_bypass_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 bypass : 1;\n+\t} s;\n+\tstruct cvmx_asxx_rld_bypass_s cn38xx;\n+\tstruct cvmx_asxx_rld_bypass_s cn38xxp2;\n+\tstruct cvmx_asxx_rld_bypass_s cn58xx;\n+\tstruct cvmx_asxx_rld_bypass_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_t;\n+\n+/**\n+ * cvmx_asx#_rld_bypass_setting\n+ *\n+ * ASX_RLD_BYPASS_SETTING\n+ *\n+ */\n+union cvmx_asxx_rld_bypass_setting {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rld_bypass_setting_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 setting : 5;\n+\t} s;\n+\tstruct cvmx_asxx_rld_bypass_setting_s cn38xx;\n+\tstruct cvmx_asxx_rld_bypass_setting_s cn38xxp2;\n+\tstruct cvmx_asxx_rld_bypass_setting_s cn58xx;\n+\tstruct cvmx_asxx_rld_bypass_setting_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_rld_bypass_setting cvmx_asxx_rld_bypass_setting_t;\n+\n+/**\n+ * cvmx_asx#_rld_comp\n+ *\n+ * ASX_RLD_COMP\n+ *\n+ */\n+union cvmx_asxx_rld_comp {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rld_comp_s {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 pctl : 5;\n+\t\tu64 nctl : 4;\n+\t} s;\n+\tstruct cvmx_asxx_rld_comp_cn38xx {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 pctl : 4;\n+\t\tu64 nctl : 4;\n+\t} cn38xx;\n+\tstruct cvmx_asxx_rld_comp_cn38xx cn38xxp2;\n+\tstruct cvmx_asxx_rld_comp_s cn58xx;\n+\tstruct cvmx_asxx_rld_comp_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_rld_comp cvmx_asxx_rld_comp_t;\n+\n+/**\n+ * cvmx_asx#_rld_data_drv\n+ *\n+ * ASX_RLD_DATA_DRV\n+ *\n+ */\n+union cvmx_asxx_rld_data_drv {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rld_data_drv_s {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 pctl : 4;\n+\t\tu64 nctl : 4;\n+\t} s;\n+\tstruct cvmx_asxx_rld_data_drv_s cn38xx;\n+\tstruct cvmx_asxx_rld_data_drv_s cn38xxp2;\n+\tstruct cvmx_asxx_rld_data_drv_s cn58xx;\n+\tstruct cvmx_asxx_rld_data_drv_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_rld_data_drv cvmx_asxx_rld_data_drv_t;\n+\n+/**\n+ * cvmx_asx#_rld_fcram_mode\n+ *\n+ * ASX_RLD_FCRAM_MODE\n+ *\n+ */\n+union cvmx_asxx_rld_fcram_mode {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rld_fcram_mode_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 mode : 1;\n+\t} s;\n+\tstruct cvmx_asxx_rld_fcram_mode_s cn38xx;\n+\tstruct cvmx_asxx_rld_fcram_mode_s cn38xxp2;\n+};\n+\n+typedef union cvmx_asxx_rld_fcram_mode cvmx_asxx_rld_fcram_mode_t;\n+\n+/**\n+ * cvmx_asx#_rld_nctl_strong\n+ *\n+ * ASX_RLD_NCTL_STRONG\n+ *\n+ */\n+union cvmx_asxx_rld_nctl_strong {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rld_nctl_strong_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 nctl : 5;\n+\t} s;\n+\tstruct cvmx_asxx_rld_nctl_strong_s cn38xx;\n+\tstruct cvmx_asxx_rld_nctl_strong_s cn38xxp2;\n+\tstruct cvmx_asxx_rld_nctl_strong_s cn58xx;\n+\tstruct cvmx_asxx_rld_nctl_strong_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_strong_t;\n+\n+/**\n+ * cvmx_asx#_rld_nctl_weak\n+ *\n+ * ASX_RLD_NCTL_WEAK\n+ *\n+ */\n+union cvmx_asxx_rld_nctl_weak {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rld_nctl_weak_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 nctl : 5;\n+\t} s;\n+\tstruct cvmx_asxx_rld_nctl_weak_s cn38xx;\n+\tstruct cvmx_asxx_rld_nctl_weak_s cn38xxp2;\n+\tstruct cvmx_asxx_rld_nctl_weak_s cn58xx;\n+\tstruct cvmx_asxx_rld_nctl_weak_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_nctl_weak_t;\n+\n+/**\n+ * cvmx_asx#_rld_pctl_strong\n+ *\n+ * ASX_RLD_PCTL_STRONG\n+ *\n+ */\n+union cvmx_asxx_rld_pctl_strong {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rld_pctl_strong_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 pctl : 5;\n+\t} s;\n+\tstruct cvmx_asxx_rld_pctl_strong_s cn38xx;\n+\tstruct cvmx_asxx_rld_pctl_strong_s cn38xxp2;\n+\tstruct cvmx_asxx_rld_pctl_strong_s cn58xx;\n+\tstruct cvmx_asxx_rld_pctl_strong_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_rld_pctl_strong cvmx_asxx_rld_pctl_strong_t;\n+\n+/**\n+ * cvmx_asx#_rld_pctl_weak\n+ *\n+ * ASX_RLD_PCTL_WEAK\n+ *\n+ */\n+union cvmx_asxx_rld_pctl_weak {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rld_pctl_weak_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 pctl : 5;\n+\t} s;\n+\tstruct cvmx_asxx_rld_pctl_weak_s cn38xx;\n+\tstruct cvmx_asxx_rld_pctl_weak_s cn38xxp2;\n+\tstruct cvmx_asxx_rld_pctl_weak_s cn58xx;\n+\tstruct cvmx_asxx_rld_pctl_weak_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_pctl_weak_t;\n+\n+/**\n+ * cvmx_asx#_rld_setting\n+ *\n+ * ASX_RLD_SETTING\n+ *\n+ */\n+union cvmx_asxx_rld_setting {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rld_setting_s {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 dfaset : 5;\n+\t\tu64 dfalag : 1;\n+\t\tu64 dfalead : 1;\n+\t\tu64 dfalock : 1;\n+\t\tu64 setting : 5;\n+\t} s;\n+\tstruct cvmx_asxx_rld_setting_cn38xx {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 setting : 5;\n+\t} cn38xx;\n+\tstruct cvmx_asxx_rld_setting_cn38xx cn38xxp2;\n+\tstruct cvmx_asxx_rld_setting_s cn58xx;\n+\tstruct cvmx_asxx_rld_setting_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_rld_setting cvmx_asxx_rld_setting_t;\n+\n+/**\n+ * cvmx_asx#_rx_clk_set#\n+ *\n+ * ASX_RX_CLK_SET = RGMII Clock delay setting\n+ *\n+ *\n+ * Notes:\n+ * Setting to place on the open-loop RXC (RGMII receive clk)\n+ * delay line, which can delay the received clock. This\n+ * can be used if the board and/or transmitting device\n+ * has not otherwise delayed the clock.\n+ *\n+ * A value of SETTING=0 disables the delay line. The delay\n+ * line should be disabled unless the transmitter or board\n+ * does not delay the clock.\n+ *\n+ * Note that this delay line provides only a coarse control\n+ * over the delay. Generally, it can only reliably provide\n+ * a delay in the range 1.25-2.5ns, which may not be adequate\n+ * for some system applications.\n+ *\n+ * The open loop delay line selects\n+ * from among a series of tap positions. Each incremental\n+ * tap position adds a delay of 50ps to 135ps per tap, depending\n+ * on the chip, its temperature, and the voltage.\n+ * To achieve from 1.25-2.5ns of delay on the received\n+ * clock, a fixed value of SETTING=24 may work.\n+ * For more precision, we recommend the following settings\n+ * based on the chip voltage:\n+ *\n+ * VDD SETTING\n+ * -----------------------------\n+ * 1.0 18\n+ * 1.05 19\n+ * 1.1 21\n+ * 1.15 22\n+ * 1.2 23\n+ * 1.25 24\n+ * 1.3 25\n+ */\n+union cvmx_asxx_rx_clk_setx {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rx_clk_setx_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 setting : 5;\n+\t} s;\n+\tstruct cvmx_asxx_rx_clk_setx_s cn30xx;\n+\tstruct cvmx_asxx_rx_clk_setx_s cn31xx;\n+\tstruct cvmx_asxx_rx_clk_setx_s cn38xx;\n+\tstruct cvmx_asxx_rx_clk_setx_s cn38xxp2;\n+\tstruct cvmx_asxx_rx_clk_setx_s cn50xx;\n+\tstruct cvmx_asxx_rx_clk_setx_s cn58xx;\n+\tstruct cvmx_asxx_rx_clk_setx_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_rx_clk_setx cvmx_asxx_rx_clk_setx_t;\n+\n+/**\n+ * cvmx_asx#_rx_prt_en\n+ *\n+ * ASX_RX_PRT_EN = RGMII Port Enable\n+ *\n+ */\n+union cvmx_asxx_rx_prt_en {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rx_prt_en_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 prt_en : 4;\n+\t} s;\n+\tstruct cvmx_asxx_rx_prt_en_cn30xx {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 prt_en : 3;\n+\t} cn30xx;\n+\tstruct cvmx_asxx_rx_prt_en_cn30xx cn31xx;\n+\tstruct cvmx_asxx_rx_prt_en_s cn38xx;\n+\tstruct cvmx_asxx_rx_prt_en_s cn38xxp2;\n+\tstruct cvmx_asxx_rx_prt_en_cn30xx cn50xx;\n+\tstruct cvmx_asxx_rx_prt_en_s cn58xx;\n+\tstruct cvmx_asxx_rx_prt_en_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_rx_prt_en cvmx_asxx_rx_prt_en_t;\n+\n+/**\n+ * cvmx_asx#_rx_wol\n+ *\n+ * ASX_RX_WOL = RGMII RX Wake on LAN status register\n+ *\n+ */\n+union cvmx_asxx_rx_wol {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rx_wol_s {\n+\t\tu64 reserved_2_63 : 62;\n+\t\tu64 status : 1;\n+\t\tu64 enable : 1;\n+\t} s;\n+\tstruct cvmx_asxx_rx_wol_s cn38xx;\n+\tstruct cvmx_asxx_rx_wol_s cn38xxp2;\n+};\n+\n+typedef union cvmx_asxx_rx_wol cvmx_asxx_rx_wol_t;\n+\n+/**\n+ * cvmx_asx#_rx_wol_msk\n+ *\n+ * ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask\n+ *\n+ */\n+union cvmx_asxx_rx_wol_msk {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rx_wol_msk_s {\n+\t\tu64 msk : 64;\n+\t} s;\n+\tstruct cvmx_asxx_rx_wol_msk_s cn38xx;\n+\tstruct cvmx_asxx_rx_wol_msk_s cn38xxp2;\n+};\n+\n+typedef union cvmx_asxx_rx_wol_msk cvmx_asxx_rx_wol_msk_t;\n+\n+/**\n+ * cvmx_asx#_rx_wol_powok\n+ *\n+ * ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK\n+ *\n+ */\n+union cvmx_asxx_rx_wol_powok {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rx_wol_powok_s {\n+\t\tu64 reserved_1_63 : 63;\n+\t\tu64 powerok : 1;\n+\t} s;\n+\tstruct cvmx_asxx_rx_wol_powok_s cn38xx;\n+\tstruct cvmx_asxx_rx_wol_powok_s cn38xxp2;\n+};\n+\n+typedef union cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_powok_t;\n+\n+/**\n+ * cvmx_asx#_rx_wol_sig\n+ *\n+ * ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature\n+ *\n+ */\n+union cvmx_asxx_rx_wol_sig {\n+\tu64 u64;\n+\tstruct cvmx_asxx_rx_wol_sig_s {\n+\t\tu64 reserved_32_63 : 32;\n+\t\tu64 sig : 32;\n+\t} s;\n+\tstruct cvmx_asxx_rx_wol_sig_s cn38xx;\n+\tstruct cvmx_asxx_rx_wol_sig_s cn38xxp2;\n+};\n+\n+typedef union cvmx_asxx_rx_wol_sig cvmx_asxx_rx_wol_sig_t;\n+\n+/**\n+ * cvmx_asx#_tx_clk_set#\n+ *\n+ * ASX_TX_CLK_SET = RGMII Clock delay setting\n+ *\n+ *\n+ * Notes:\n+ * Setting to place on the open-loop TXC (RGMII transmit clk)\n+ * delay line, which can delay the transmited clock. This\n+ * can be used if the board and/or transmitting device\n+ * has not otherwise delayed the clock.\n+ *\n+ * A value of SETTING=0 disables the delay line. The delay\n+ * line should be disabled unless the transmitter or board\n+ * does not delay the clock.\n+ *\n+ * Note that this delay line provides only a coarse control\n+ * over the delay. Generally, it can only reliably provide\n+ * a delay in the range 1.25-2.5ns, which may not be adequate\n+ * for some system applications.\n+ *\n+ * The open loop delay line selects\n+ * from among a series of tap positions. Each incremental\n+ * tap position adds a delay of 50ps to 135ps per tap, depending\n+ * on the chip, its temperature, and the voltage.\n+ * To achieve from 1.25-2.5ns of delay on the received\n+ * clock, a fixed value of SETTING=24 may work.\n+ * For more precision, we recommend the following settings\n+ * based on the chip voltage:\n+ *\n+ * VDD SETTING\n+ * -----------------------------\n+ * 1.0 18\n+ * 1.05 19\n+ * 1.1 21\n+ * 1.15 22\n+ * 1.2 23\n+ * 1.25 24\n+ * 1.3 25\n+ */\n+union cvmx_asxx_tx_clk_setx {\n+\tu64 u64;\n+\tstruct cvmx_asxx_tx_clk_setx_s {\n+\t\tu64 reserved_5_63 : 59;\n+\t\tu64 setting : 5;\n+\t} s;\n+\tstruct cvmx_asxx_tx_clk_setx_s cn30xx;\n+\tstruct cvmx_asxx_tx_clk_setx_s cn31xx;\n+\tstruct cvmx_asxx_tx_clk_setx_s cn38xx;\n+\tstruct cvmx_asxx_tx_clk_setx_s cn38xxp2;\n+\tstruct cvmx_asxx_tx_clk_setx_s cn50xx;\n+\tstruct cvmx_asxx_tx_clk_setx_s cn58xx;\n+\tstruct cvmx_asxx_tx_clk_setx_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_tx_clk_setx cvmx_asxx_tx_clk_setx_t;\n+\n+/**\n+ * cvmx_asx#_tx_comp_byp\n+ *\n+ * ASX_TX_COMP_BYP = RGMII Clock delay setting\n+ *\n+ */\n+union cvmx_asxx_tx_comp_byp {\n+\tu64 u64;\n+\tstruct cvmx_asxx_tx_comp_byp_s {\n+\t\tu64 reserved_0_63 : 64;\n+\t} s;\n+\tstruct cvmx_asxx_tx_comp_byp_cn30xx {\n+\t\tu64 reserved_9_63 : 55;\n+\t\tu64 bypass : 1;\n+\t\tu64 pctl : 4;\n+\t\tu64 nctl : 4;\n+\t} cn30xx;\n+\tstruct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;\n+\tstruct cvmx_asxx_tx_comp_byp_cn38xx {\n+\t\tu64 reserved_8_63 : 56;\n+\t\tu64 pctl : 4;\n+\t\tu64 nctl : 4;\n+\t} cn38xx;\n+\tstruct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;\n+\tstruct cvmx_asxx_tx_comp_byp_cn50xx {\n+\t\tu64 reserved_17_63 : 47;\n+\t\tu64 bypass : 1;\n+\t\tu64 reserved_13_15 : 3;\n+\t\tu64 pctl : 5;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 nctl : 5;\n+\t} cn50xx;\n+\tstruct cvmx_asxx_tx_comp_byp_cn58xx {\n+\t\tu64 reserved_13_63 : 51;\n+\t\tu64 pctl : 5;\n+\t\tu64 reserved_5_7 : 3;\n+\t\tu64 nctl : 5;\n+\t} cn58xx;\n+\tstruct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_tx_comp_byp cvmx_asxx_tx_comp_byp_t;\n+\n+/**\n+ * cvmx_asx#_tx_hi_water#\n+ *\n+ * ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark\n+ *\n+ */\n+union cvmx_asxx_tx_hi_waterx {\n+\tu64 u64;\n+\tstruct cvmx_asxx_tx_hi_waterx_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 mark : 4;\n+\t} s;\n+\tstruct cvmx_asxx_tx_hi_waterx_cn30xx {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 mark : 3;\n+\t} cn30xx;\n+\tstruct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;\n+\tstruct cvmx_asxx_tx_hi_waterx_s cn38xx;\n+\tstruct cvmx_asxx_tx_hi_waterx_s cn38xxp2;\n+\tstruct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;\n+\tstruct cvmx_asxx_tx_hi_waterx_s cn58xx;\n+\tstruct cvmx_asxx_tx_hi_waterx_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_hi_waterx_t;\n+\n+/**\n+ * cvmx_asx#_tx_prt_en\n+ *\n+ * ASX_TX_PRT_EN = RGMII Port Enable\n+ *\n+ */\n+union cvmx_asxx_tx_prt_en {\n+\tu64 u64;\n+\tstruct cvmx_asxx_tx_prt_en_s {\n+\t\tu64 reserved_4_63 : 60;\n+\t\tu64 prt_en : 4;\n+\t} s;\n+\tstruct cvmx_asxx_tx_prt_en_cn30xx {\n+\t\tu64 reserved_3_63 : 61;\n+\t\tu64 prt_en : 3;\n+\t} cn30xx;\n+\tstruct cvmx_asxx_tx_prt_en_cn30xx cn31xx;\n+\tstruct cvmx_asxx_tx_prt_en_s cn38xx;\n+\tstruct cvmx_asxx_tx_prt_en_s cn38xxp2;\n+\tstruct cvmx_asxx_tx_prt_en_cn30xx cn50xx;\n+\tstruct cvmx_asxx_tx_prt_en_s cn58xx;\n+\tstruct cvmx_asxx_tx_prt_en_s cn58xxp1;\n+};\n+\n+typedef union cvmx_asxx_tx_prt_en cvmx_asxx_tx_prt_en_t;\n+\n+#endif\n", "prefixes": [ "v1", "04/50" ] }