Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1407821/?format=api
{ "id": 1407821, "url": "http://patchwork.ozlabs.org/api/patches/1407821/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/20201129125407.1391557-2-idosch@idosch.org/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201129125407.1391557-2-idosch@idosch.org>", "list_archive_url": null, "date": "2020-11-29T12:53:59", "name": "[net-next,1/9] mlxsw: reg: Add Switch Port VLAN Classification Register", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "3f2be952f6e12dfc0220d7140f6de40effa2998d", "submitter": { "id": 69679, "url": "http://patchwork.ozlabs.org/api/people/69679/?format=api", "name": "Ido Schimmel", "email": "idosch@idosch.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/20201129125407.1391557-2-idosch@idosch.org/mbox/", "series": [ { "id": 217375, "url": "http://patchwork.ozlabs.org/api/series/217375/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=217375", "date": "2020-11-29T12:54:00", "name": "mlxsw: Add support for 802.1ad bridging", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/217375/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1407821/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1407821/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming-netdev@ozlabs.org", "Delivered-To": "patchwork-incoming-netdev@ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=23.128.96.18; helo=vger.kernel.org;\n envelope-from=netdev-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=idosch.org", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=messagingengine.com header.i=@messagingengine.com\n header.a=rsa-sha256 header.s=fm1 header.b=reCrLwLl;\n\tdkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [23.128.96.18])\n\tby ozlabs.org (Postfix) with ESMTP id 4CkSzJ4chqz9sT6\n\tfor <patchwork-incoming-netdev@ozlabs.org>;\n Sun, 29 Nov 2020 23:56:12 +1100 (AEDT)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n id S2387421AbgK2Mzt (ORCPT\n <rfc822;patchwork-incoming-netdev@ozlabs.org>);\n Sun, 29 Nov 2020 07:55:49 -0500", "from new1-smtp.messagingengine.com ([66.111.4.221]:37053 \"EHLO\n new1-smtp.messagingengine.com\" rhost-flags-OK-OK-OK-OK)\n by vger.kernel.org with ESMTP id S2387408AbgK2Mzs (ORCPT\n <rfc822;netdev@vger.kernel.org>); Sun, 29 Nov 2020 07:55:48 -0500", "from compute3.internal (compute3.nyi.internal [10.202.2.43])\n by mailnew.nyi.internal (Postfix) with ESMTP id 7AD4D580681;\n Sun, 29 Nov 2020 07:54:42 -0500 (EST)", "from mailfrontend2 ([10.202.2.163])\n by compute3.internal (MEProxy); Sun, 29 Nov 2020 07:54:42 -0500", "from shredder.lan (igld-84-229-154-147.inter.net.il\n [84.229.154.147])\n by mail.messagingengine.com (Postfix) with ESMTPA id 5CF633064AB5;\n Sun, 29 Nov 2020 07:54:40 -0500 (EST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=\n messagingengine.com; h=cc:content-transfer-encoding:date:from\n :in-reply-to:message-id:mime-version:references:subject:to\n :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=\n fm1; bh=wefPYKeg9f3jB6pW76coXo3/Je1bg6qX0vrK5Wyoam8=; b=reCrLwLl\n /ChUMyeT2JLcvuZ+ao9tC/XaUiKZGJvPz/UMJ8Q2X+llhUzjlMLJTLn17h48JG8s\n g5/6Yty9mxD18m7b8hjGjcnDfjiLdualbel+sISn1NbyuzJ41LMRgs6TES47FQAz\n QiO6f1/KH0OgVaL63tRR+d6mYkVNSyV8IN+Wj1UeeUWPPDtVrXGW2Ums1c7Yh2on\n M6yrI4xre579PK59BtEpN44ySIfLklzEYiMdIfdnSFZW6LD2VSG0KA1DArM5Xax2\n 9Z4o6x27IG0YUa6Qo3ZVXWIN37q6xosgDtJzw4DfC9YtZO60xcRADRHonXcZQv4g\n dRvmYifTMfj0yQ==", "X-ME-Sender": "<xms:EprDX1iEgweppZCvGt_Qm4DO0e-2BhXkUIPlwRZhyeLkZQ2DPeSsHw>\n <xme:EprDX6CF_PTwDLqKPkGZThAVDLzX4Fy9G3vJPQD0OlCzVtvJ7Tk1Fe_3LXLg-WH0J\n mpbjJn-FhAH6B0>", "X-ME-Proxy-Cause": "\n gggruggvucftvghtrhhoucdtuddrgedujedrudehkedggeeiucetufdoteggodetrfdotf\n fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen\n uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre\n dtredttdenucfhrhhomhepkfguohcuufgthhhimhhmvghluceoihguohhstghhsehiugho\n shgthhdrohhrgheqnecuggftrfgrthhtvghrnhepudetieevffffveelkeeljeffkefhke\n ehgfdtffethfelvdejgffghefgveejkefhnecukfhppeekgedrvddvledrudehgedrudeg\n jeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehiug\n hoshgthhesihguohhstghhrdhorhhg", "X-ME-Proxy": "<xmx:EprDX1H9chazrgrk2uu6QmxmCtDMv7kqbvlWdmItYMCNENLo2Y0IZQ>\n <xmx:EprDX6QNHOh2Ztio0pPDMDCFUmVlgQANXIUCEaXcXwBy0L22Ke6UxA>\n <xmx:EprDXyzrpg9jROzyWlBtqlGv4XOk2mkZZ54C4kGpkJNF4crHFUv3sw>\n <xmx:EprDX2ffn_Ilex_DR74MFPeKlJ6tsuvDxvCj1tEP9QROJ5Y4zN7cBQ>", "From": "Ido Schimmel <idosch@idosch.org>", "To": "netdev@vger.kernel.org, bridge@lists.linux-foundation.org", "Cc": "davem@davemloft.net, kuba@kernel.org, jiri@nvidia.com,\n ivecera@redhat.com, roopa@nvidia.com, nikolay@nvidia.com,\n amcohen@nvidia.com, danieller@nvidia.com, petrm@nvidia.com,\n mlxsw@nvidia.com, Ido Schimmel <idosch@nvidia.com>", "Subject": "[PATCH net-next 1/9] mlxsw: reg: Add Switch Port VLAN Classification\n Register", "Date": "Sun, 29 Nov 2020 14:53:59 +0200", "Message-Id": "<20201129125407.1391557-2-idosch@idosch.org>", "X-Mailer": "git-send-email 2.28.0", "In-Reply-To": "<20201129125407.1391557-1-idosch@idosch.org>", "References": "<20201129125407.1391557-1-idosch@idosch.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "From: Amit Cohen <amcohen@nvidia.com>\n\nSPVC configures the port to identify packets as untagged / single tagged /\ndouble tagged packets based on the packet EtherTypes.\n\nIt will be used to classify 802.1q packets as untagged and 802.1ad packets\nas tagged when received by ports member in a 802.1ad bridge.\n\nSigned-off-by: Amit Cohen <amcohen@nvidia.com>\nReviewed-by: Petr Machata <petrm@nvidia.com>\nSigned-off-by: Ido Schimmel <idosch@nvidia.com>\n---\n drivers/net/ethernet/mellanox/mlxsw/reg.h | 99 +++++++++++++++++++++++\n 1 file changed, 99 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h\nindex fcf9095b3f55..5248532c3999 100644\n--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h\n+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h\n@@ -1857,6 +1857,104 @@ static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,\n \t}\n }\n \n+/* SPVC - Switch Port VLAN Classification Register\n+ * -----------------------------------------------\n+ * Configures the port to identify packets as untagged / single tagged /\n+ * double packets based on the packet EtherTypes.\n+ * Ethertype IDs are configured by SVER.\n+ */\n+#define MLXSW_REG_SPVC_ID 0x2026\n+#define MLXSW_REG_SPVC_LEN 0x0C\n+\n+MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN);\n+\n+/* reg_spvc_local_port\n+ * Local port.\n+ * Access: Index\n+ *\n+ * Note: applies both to Rx port and Tx port, so if a packet traverses\n+ * through Rx port i and a Tx port j then port i and port j must have the\n+ * same configuration.\n+ */\n+MLXSW_ITEM32(reg, spvc, local_port, 0x00, 16, 8);\n+\n+/* reg_spvc_inner_et2\n+ * Vlan Tag1 EtherType2 enable.\n+ * Packet is initially classified as double VLAN Tag if in addition to\n+ * being classified with a tag0 VLAN Tag its tag1 EtherType value is\n+ * equal to ether_type2.\n+ * 0: disable (default)\n+ * 1: enable\n+ * Access: RW\n+ */\n+MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1);\n+\n+/* reg_spvc_et2\n+ * Vlan Tag0 EtherType2 enable.\n+ * Packet is initially classified as VLAN Tag if its tag0 EtherType is\n+ * equal to ether_type2.\n+ * 0: disable (default)\n+ * 1: enable\n+ * Access: RW\n+ */\n+MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1);\n+\n+/* reg_spvc_inner_et1\n+ * Vlan Tag1 EtherType1 enable.\n+ * Packet is initially classified as double VLAN Tag if in addition to\n+ * being classified with a tag0 VLAN Tag its tag1 EtherType value is\n+ * equal to ether_type1.\n+ * 0: disable\n+ * 1: enable (default)\n+ * Access: RW\n+ */\n+MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1);\n+\n+/* reg_spvc_et1\n+ * Vlan Tag0 EtherType1 enable.\n+ * Packet is initially classified as VLAN Tag if its tag0 EtherType is\n+ * equal to ether_type1.\n+ * 0: disable\n+ * 1: enable (default)\n+ * Access: RW\n+ */\n+MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1);\n+\n+/* reg_inner_et0\n+ * Vlan Tag1 EtherType0 enable.\n+ * Packet is initially classified as double VLAN Tag if in addition to\n+ * being classified with a tag0 VLAN Tag its tag1 EtherType value is\n+ * equal to ether_type0.\n+ * 0: disable\n+ * 1: enable (default)\n+ * Access: RW\n+ */\n+MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1);\n+\n+/* reg_et0\n+ * Vlan Tag0 EtherType0 enable.\n+ * Packet is initially classified as VLAN Tag if its tag0 EtherType is\n+ * equal to ether_type0.\n+ * 0: disable\n+ * 1: enable (default)\n+ * Access: RW\n+ */\n+MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1);\n+\n+static inline void mlxsw_reg_spvc_pack(char *payload, u8 local_port, bool et1,\n+\t\t\t\t bool et0)\n+{\n+\tMLXSW_REG_ZERO(spvc, payload);\n+\tmlxsw_reg_spvc_local_port_set(payload, local_port);\n+\t/* Enable inner_et1 and inner_et0 to enable identification of double\n+\t * tagged packets.\n+\t */\n+\tmlxsw_reg_spvc_inner_et1_set(payload, 1);\n+\tmlxsw_reg_spvc_inner_et0_set(payload, 1);\n+\tmlxsw_reg_spvc_et1_set(payload, et1);\n+\tmlxsw_reg_spvc_et0_set(payload, et0);\n+}\n+\n /* CWTP - Congetion WRED ECN TClass Profile\n * ----------------------------------------\n * Configures the profiles for queues of egress port and traffic class\n@@ -11212,6 +11310,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {\n \tMLXSW_REG(svpe),\n \tMLXSW_REG(sfmr),\n \tMLXSW_REG(spvmlr),\n+\tMLXSW_REG(spvc),\n \tMLXSW_REG(cwtp),\n \tMLXSW_REG(cwtpm),\n \tMLXSW_REG(pgcr),\n", "prefixes": [ "net-next", "1/9" ] }