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GET /api/patches/1378397/?format=api
{ "id": 1378397, "url": "http://patchwork.ozlabs.org/api/patches/1378397/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201008051250.25784-10-faiz_abbas@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201008051250.25784-10-faiz_abbas@ti.com>", "list_archive_url": null, "date": "2020-10-08T05:12:42", "name": "[09/17] mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modes", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "3529fabe94c313f2579eea95daaacb6cde41c3a5", "submitter": { "id": 72140, "url": "http://patchwork.ozlabs.org/api/people/72140/?format=api", "name": "Faiz Abbas", "email": "faiz_abbas@ti.com" }, "delegate": { "id": 19261, "url": "http://patchwork.ozlabs.org/api/users/19261/?format=api", "username": "lokeshvutla", "first_name": "Lokesh", "last_name": "Vutla", "email": "lokeshvutla@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201008051250.25784-10-faiz_abbas@ti.com/mbox/", "series": [ { "id": 206622, "url": "http://patchwork.ozlabs.org/api/series/206622/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=206622", "date": "2020-10-08T05:12:33", "name": "Add support for MMC higher speed modes for TI's am65x, j721e and j7200 platforms", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/206622/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1378397/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1378397/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=pass (p=quarantine dis=none) header.from=ti.com", "ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256\n header.s=ti-com-17Q1 header.b=wSxFqqaK;\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=ti.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ti.com header.i=@ti.com header.b=\"wSxFqqaK\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=ti.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=faiz_abbas@ti.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4C6KC61d91z9sRk\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 8 Oct 2020 16:14:58 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id C9757823D9;\n\tThu, 8 Oct 2020 07:13:39 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 30D5C823C9; Thu, 8 Oct 2020 07:13:38 +0200 (CEST)", "from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 3E361823ED\n for <u-boot@lists.denx.de>; Thu, 8 Oct 2020 07:13:35 +0200 (CEST)", "from fllv0035.itg.ti.com ([10.64.41.0])\n by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0985DY6X003161;\n Thu, 8 Oct 2020 00:13:34 -0500", "from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30])\n by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0985DYsr049327\n (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL);\n Thu, 8 Oct 2020 00:13:34 -0500", "from DLEE102.ent.ti.com (157.170.170.32) by DLEE100.ent.ti.com\n (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 8 Oct\n 2020 00:13:33 -0500", "from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com\n (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via\n Frontend Transport; Thu, 8 Oct 2020 00:13:33 -0500", "from a0230074-Latitude-E7470.ent.ti.com (ileax41-snat.itg.ti.com\n [10.172.224.153])\n by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0985Cpxl022642;\n Thu, 8 Oct 2020 00:13:30 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED\n autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com;\n s=ti-com-17Q1; t=1602134014;\n bh=WfoItfRNdEUHZiFR/+uaPXwkobvCP/u/3FUEXgPANcw=;\n h=From:To:CC:Subject:Date:In-Reply-To:References;\n b=wSxFqqaK4O085ajSC2v/Dq0qsYn7lu9PcFq3jX2/grEkJBirW3GMULhHLPyeGxwni\n c782/IXPZuf82+rV9IH1mpM6c5w+63ak0tXcd6+COLkmJk+mNOqX2g2Kr1uHlfj0wV\n sryk1A+Q47TtOjN70vsO75z7Bi5rqyGnk1aLJ8cQ=", "From": "Faiz Abbas <faiz_abbas@ti.com>", "To": "<u-boot@lists.denx.de>, <peng.fan@nxp.com>, <lokeshvutla@ti.com>", "CC": "<faiz_abbas@ti.com>", "Subject": "[PATCH 09/17] mmc: am654_sdhci: Fix HISPD bit configuration in some\n lower speed modes", "Date": "Thu, 8 Oct 2020 10:42:42 +0530", "Message-ID": "<20201008051250.25784-10-faiz_abbas@ti.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20201008051250.25784-1-faiz_abbas@ti.com>", "References": "<20201008051250.25784-1-faiz_abbas@ti.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "According to the AM654x Data Manual[1], the setup timing in lower speed\nmodes can only be met if the controller uses a falling edge data launch.\n\nTo ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be\ncleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25\nspeed modes.\n\nUse the sdhci writeb callback to implement this condition.\n\n[1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1\n\nSigned-off-by: Faiz Abbas <faiz_abbas@ti.com>\n---\n drivers/mmc/Kconfig | 1 +\n drivers/mmc/am654_sdhci.c | 25 +++++++++++++++++++++++--\n 2 files changed, 24 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig\nindex 0c252e34c7..525445949d 100644\n--- a/drivers/mmc/Kconfig\n+++ b/drivers/mmc/Kconfig\n@@ -521,6 +521,7 @@ config MMC_SDHCI_AM654\n \tdepends on MMC_SDHCI\n \tdepends on DM_MMC && OF_CONTROL && BLK\n \tdepends on REGMAP\n+\tselect MMC_SDHCI_IO_ACCESSORS\n \thelp\n \t Support for Secure Digital Host Controller Interface (SDHCI)\n \t controllers present on TI's AM654 SOCs.\ndiff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c\nindex 79b4331c3c..410517398a 100644\n--- a/drivers/mmc/am654_sdhci.c\n+++ b/drivers/mmc/am654_sdhci.c\n@@ -369,6 +369,26 @@ static int am654_sdhci_deferred_probe(struct sdhci_host *host)\n \treturn sdhci_probe(dev);\n }\n \n+static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg)\n+{\n+\tif (reg == SDHCI_HOST_CONTROL) {\n+\t\tswitch (host->mmc->selected_mode) {\n+\t\t/*\n+\t\t * According to the data manual, HISPD bit\n+\t\t * should not be set in these speed modes.\n+\t\t */\n+\t\tcase SD_HS:\n+\t\tcase MMC_HS:\n+\t\tcase UHS_SDR12:\n+\t\tcase UHS_SDR25:\n+\t\t\tval &= ~SDHCI_CTRL_HISPD;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\twriteb(val, host->ioaddr + reg);\n+}\n #ifdef MMC_SUPPORTS_TUNING\n #define ITAP_MAX\t32\n static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)\n@@ -414,6 +434,7 @@ const struct sdhci_ops am654_sdhci_ops = {\n \t.deferred_probe\t\t= am654_sdhci_deferred_probe,\n \t.set_ios_post\t\t= &am654_sdhci_set_ios_post,\n \t.set_control_reg\t= &am654_sdhci_set_control_reg,\n+\t.write_b\t\t= am654_sdhci_write_b,\n };\n \n const struct am654_driver_data am654_drv_data = {\n@@ -455,6 +476,7 @@ const struct sdhci_ops j721e_4bit_sdhci_ops = {\n #endif\n \t.deferred_probe\t\t= am654_sdhci_deferred_probe,\n \t.set_ios_post\t\t= &j721e_4bit_sdhci_set_ios_post,\n+\t.write_b\t\t= am654_sdhci_write_b,\n };\n \n const struct am654_driver_data j721e_4bit_drv_data = {\n@@ -532,6 +554,7 @@ static int am654_sdhci_probe(struct udevice *dev)\n \thost->max_clk = clock;\n \thost->mmc = &plat->mmc;\n \thost->mmc->dev = dev;\n+\thost->ops = drv_data->ops;\n \tret = sdhci_setup_cfg(cfg, host, cfg->f_max,\n \t\t\t AM654_SDHCI_MIN_FREQ);\n \tif (ret)\n@@ -541,8 +564,6 @@ static int am654_sdhci_probe(struct udevice *dev)\n \tif (ret)\n \t\treturn ret;\n \n-\thost->ops = drv_data->ops;\n-\n \t/* Update ops based on SoC revision */\n \tsoc = soc_device_match(am654_sdhci_soc_attr);\n \tif (soc && soc->data) {\n", "prefixes": [ "09/17" ] }