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GET /api/patches/1378394/?format=api
{ "id": 1378394, "url": "http://patchwork.ozlabs.org/api/patches/1378394/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20201008051250.25784-7-faiz_abbas@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20201008051250.25784-7-faiz_abbas@ti.com>", "list_archive_url": null, "date": "2020-10-08T05:12:39", "name": "[06/17] mmc: am654_sdhci: Add support for input tap delay", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "c9116dd046060db18f2ddb9292b45334e79bbf77", "submitter": { "id": 72140, "url": "http://patchwork.ozlabs.org/api/people/72140/?format=api", "name": "Faiz Abbas", "email": "faiz_abbas@ti.com" }, "delegate": { "id": 19261, "url": "http://patchwork.ozlabs.org/api/users/19261/?format=api", "username": "lokeshvutla", "first_name": "Lokesh", "last_name": "Vutla", "email": "lokeshvutla@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20201008051250.25784-7-faiz_abbas@ti.com/mbox/", "series": [ { "id": 206622, "url": "http://patchwork.ozlabs.org/api/series/206622/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=206622", "date": "2020-10-08T05:12:33", "name": "Add support for MMC higher speed modes for TI's am65x, j721e and j7200 platforms", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/206622/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1378394/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1378394/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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Thu, 8 Oct\n 2020 00:13:22 -0500", "from lelv0327.itg.ti.com (10.180.67.183) by DFLE100.ent.ti.com\n (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via\n Frontend Transport; Thu, 8 Oct 2020 00:13:22 -0500", "from a0230074-Latitude-E7470.ent.ti.com (ileax41-snat.itg.ti.com\n [10.172.224.153])\n by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0985Cpxi022642;\n Thu, 8 Oct 2020 00:13:19 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED\n autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com;\n s=ti-com-17Q1; t=1602134002;\n bh=TKC1dftTvD4vbOxfsqG7SCq80DGlDhL9+9cnnjZsCfg=;\n h=From:To:CC:Subject:Date:In-Reply-To:References;\n b=we3Uoi3H2mb4JDgMoKMqv28UH82MhynHEKUuoJ5+qvOyAdwm9Ab3cGsNxO2Hkt6AD\n STPNBM7BDS0hBSUmrR5sLoRg+BiHT+TJ8+9KGSJP6wxO1W8HgU2p/p8DRf0cR/aOLI\n JHPV4qL4EC6RQKX20qZzogkU5gjgICyPfXk1z6bs=", "From": "Faiz Abbas <faiz_abbas@ti.com>", "To": "<u-boot@lists.denx.de>, <peng.fan@nxp.com>, <lokeshvutla@ti.com>", "CC": "<faiz_abbas@ti.com>", "Subject": "[PATCH 06/17] mmc: am654_sdhci: Add support for input tap delay", "Date": "Thu, 8 Oct 2020 10:42:39 +0530", "Message-ID": "<20201008051250.25784-7-faiz_abbas@ti.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20201008051250.25784-1-faiz_abbas@ti.com>", "References": "<20201008051250.25784-1-faiz_abbas@ti.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.102.3 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "DLL need only be enabled for speed modes and clock frequencies at or\nabove 50 MHz. For speed modes that don't enable the DLL, we need to\nconfigure a static input delay value. This involves reading an optional\nitap-del-sel-* value from the device tree and configuring it for the\nappropriate speed mode.\n\nTherefore, move all dll configurations to their own functions and gate it\nwith 50 MHz speed and a minimum mode. If both these conditions are not\nsatisfied then configure delay chain modes.\n\nSigned-off-by: Faiz Abbas <faiz_abbas@ti.com>\n---\n drivers/mmc/am654_sdhci.c | 241 +++++++++++++++++++++++++-------------\n 1 file changed, 161 insertions(+), 80 deletions(-)", "diff": "diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c\nindex 71798be765..f472672152 100644\n--- a/drivers/mmc/am654_sdhci.c\n+++ b/drivers/mmc/am654_sdhci.c\n@@ -62,6 +62,16 @@\n #define CALDONE_MASK\t\tBIT(CALDONE_SHIFT)\n #define RETRIM_SHIFT\t\t17\n #define RETRIM_MASK\t\tBIT(RETRIM_SHIFT)\n+#define SELDLYTXCLK_SHIFT\t17\n+#define SELDLYTXCLK_MASK\tBIT(SELDLYTXCLK_SHIFT)\n+#define SELDLYRXCLK_SHIFT\t16\n+#define SELDLYRXCLK_MASK\tBIT(SELDLYRXCLK_SHIFT)\n+#define ITAPDLYSEL_SHIFT\t0\n+#define ITAPDLYSEL_MASK\t\tGENMASK(4, 0)\n+#define ITAPDLYENA_SHIFT\t8\n+#define ITAPDLYENA_MASK\t\tBIT(ITAPDLYENA_SHIFT)\n+#define ITAPCHGWIN_SHIFT\t9\n+#define ITAPCHGWIN_MASK\t\tBIT(ITAPCHGWIN_SHIFT)\n \n #define DRIVER_STRENGTH_50_OHM\t0x0\n #define DRIVER_STRENGTH_33_OHM\t0x1\n@@ -70,6 +80,7 @@\n #define DRIVER_STRENGTH_40_OHM\t0x4\n \n #define AM654_SDHCI_MIN_FREQ\t400000\n+#define CLOCK_TOO_SLOW_HZ\t50000000\n \n struct am654_sdhci_plat {\n \tstruct mmc_config cfg;\n@@ -77,6 +88,7 @@ struct am654_sdhci_plat {\n \tstruct regmap *base;\n \tbool non_removable;\n \tu32 otap_del_sel[MMC_MODES_END];\n+\tu32 itap_del_sel[MMC_MODES_END];\n \tu32 trm_icp;\n \tu32 drv_strength;\n \tu32 strb_sel;\n@@ -89,22 +101,45 @@ struct am654_sdhci_plat {\n };\n \n struct timing_data {\n-\tconst char *binding;\n+\tconst char *otap_binding;\n+\tconst char *itap_binding;\n \tu32 capability;\n };\n \n static const struct timing_data td[] = {\n-\t[MMC_LEGACY] = {\"ti,otap-del-sel-legacy\", 0},\n-\t[MMC_HS] = {\"ti,otap-del-sel-mmc-hs\", MMC_CAP(MMC_HS)},\n-\t[SD_HS] = {\"ti,otap-del-sel-sd-hs\", MMC_CAP(SD_HS)},\n-\t[UHS_SDR12] = {\"ti,otap-del-sel-sdr12\", MMC_CAP(UHS_SDR12)},\n-\t[UHS_SDR25] = {\"ti,otap-del-sel-sdr25\", MMC_CAP(UHS_SDR25)},\n-\t[UHS_SDR50] = {\"ti,otap-del-sel-sdr50\", MMC_CAP(UHS_SDR50)},\n-\t[UHS_SDR104] = {\"ti,otap-del-sel-sdr104\", MMC_CAP(UHS_SDR104)},\n-\t[UHS_DDR50] = {\"ti,otap-del-sel-ddr50\", MMC_CAP(UHS_DDR50)},\n-\t[MMC_DDR_52] = {\"ti,otap-del-sel-ddr52\", MMC_CAP(MMC_DDR_52)},\n-\t[MMC_HS_200] = {\"ti,otap-del-sel-hs200\", MMC_CAP(MMC_HS_200)},\n-\t[MMC_HS_400] = {\"ti,otap-del-sel-hs400\", MMC_CAP(MMC_HS_400)},\n+\t[MMC_LEGACY]\t= {\"ti,otap-del-sel-legacy\",\n+\t\t\t \"ti,itap-del-sel-legacy\",\n+\t\t\t 0},\n+\t[MMC_HS]\t= {\"ti,otap-del-sel-mmc-hs\",\n+\t\t\t \"ti,itap-del-sel-mms-hs\",\n+\t\t\t MMC_CAP(MMC_HS)},\n+\t[SD_HS]\t\t= {\"ti,otap-del-sel-sd-hs\",\n+\t\t\t \"ti,itap-del-sel-sd-hs\",\n+\t\t\t MMC_CAP(SD_HS)},\n+\t[UHS_SDR12]\t= {\"ti,otap-del-sel-sdr12\",\n+\t\t\t \"ti,itap-del-sel-sdr12\",\n+\t\t\t MMC_CAP(UHS_SDR12)},\n+\t[UHS_SDR25]\t= {\"ti,otap-del-sel-sdr25\",\n+\t\t\t \"ti,itap-del-sel-sdr25\",\n+\t\t\t MMC_CAP(UHS_SDR25)},\n+\t[UHS_SDR50]\t= {\"ti,otap-del-sel-sdr50\",\n+\t\t\t NULL,\n+\t\t\t MMC_CAP(UHS_SDR50)},\n+\t[UHS_SDR104]\t= {\"ti,otap-del-sel-sdr104\",\n+\t\t\t NULL,\n+\t\t\t MMC_CAP(UHS_SDR104)},\n+\t[UHS_DDR50]\t= {\"ti,otap-del-sel-ddr50\",\n+\t\t\t NULL,\n+\t\t\t MMC_CAP(UHS_DDR50)},\n+\t[MMC_DDR_52]\t= {\"ti,otap-del-sel-ddr52\",\n+\t\t\t \"ti,itap-del-sel-ddr52\",\n+\t\t\t MMC_CAP(MMC_DDR_52)},\n+\t[MMC_HS_200]\t= {\"ti,otap-del-sel-hs200\",\n+\t\t\t NULL,\n+\t\t\t MMC_CAP(MMC_HS_200)},\n+\t[MMC_HS_400]\t= {\"ti,otap-del-sel-hs400\",\n+\t\t\t NULL,\n+\t\t\t MMC_CAP(MMC_HS_400)},\n };\n \n struct am654_driver_data {\n@@ -127,12 +162,99 @@ static void am654_sdhci_set_control_reg(struct sdhci_host *host)\n \tsdhci_set_uhs_timing(host);\n }\n \n+static int am654_sdhci_setup_dll(struct am654_sdhci_plat *plat,\n+\t\t\t\t unsigned int speed)\n+{\n+\tint sel50, sel100, freqsel;\n+\tu32 mask, val;\n+\tint ret;\n+\n+\t/* Disable delay chain mode */\n+\tregmap_update_bits(plat->base, PHY_CTRL5,\n+\t\t\t SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);\n+\n+\tif (plat->flags & FREQSEL_2_BIT) {\n+\t\tswitch (speed) {\n+\t\tcase 200000000:\n+\t\t\tsel50 = 0;\n+\t\t\tsel100 = 0;\n+\t\t\tbreak;\n+\t\tcase 100000000:\n+\t\t\tsel50 = 0;\n+\t\t\tsel100 = 1;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tsel50 = 1;\n+\t\t\tsel100 = 0;\n+\t\t}\n+\n+\t\t/* Configure PHY DLL frequency */\n+\t\tmask = SEL50_MASK | SEL100_MASK;\n+\t\tval = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);\n+\t\tregmap_update_bits(plat->base, PHY_CTRL5, mask, val);\n+\t} else {\n+\t\tswitch (speed) {\n+\t\tcase 200000000:\n+\t\t\tfreqsel = 0x0;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tfreqsel = 0x4;\n+\t\t}\n+\t\tregmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,\n+\t\t\t\t freqsel << FREQSEL_SHIFT);\n+\t}\n+\n+\t/* Configure DLL TRIM */\n+\tmask = DLL_TRIM_ICP_MASK;\n+\tval = plat->trm_icp << DLL_TRIM_ICP_SHIFT;\n+\n+\t/* Configure DLL driver strength */\n+\tmask |= DR_TY_MASK;\n+\tval |= plat->drv_strength << DR_TY_SHIFT;\n+\tregmap_update_bits(plat->base, PHY_CTRL1, mask, val);\n+\n+\t/* Enable DLL */\n+\tregmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,\n+\t\t\t 0x1 << ENDLL_SHIFT);\n+\t/*\n+\t * Poll for DLL ready. Use a one second timeout.\n+\t * Works in all experiments done so far\n+\t */\n+\tret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,\n+\t\t\t\t val & DLLRDY_MASK, 1000, 1000000);\n+\n+\treturn ret;\n+}\n+\n+static void am654_sdhci_write_itapdly(struct am654_sdhci_plat *plat,\n+\t\t\t\t u32 itapdly)\n+{\n+\t/* Set ITAPCHGWIN before writing to ITAPDLY */\n+\tregmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK,\n+\t\t\t 1 << ITAPCHGWIN_SHIFT);\n+\tregmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYSEL_MASK,\n+\t\t\t itapdly << ITAPDLYSEL_SHIFT);\n+\tregmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);\n+}\n+\n+static void am654_sdhci_setup_delay_chain(struct am654_sdhci_plat *plat,\n+\t\t\t\t\t int mode)\n+{\n+\tu32 mask, val;\n+\n+\tval = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;\n+\tmask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;\n+\tregmap_update_bits(plat->base, PHY_CTRL5, mask, val);\n+\n+\tam654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode]);\n+}\n+\n static int am654_sdhci_set_ios_post(struct sdhci_host *host)\n {\n \tstruct udevice *dev = host->mmc->dev;\n \tstruct am654_sdhci_plat *plat = dev_get_platdata(dev);\n \tunsigned int speed = host->mmc->clock;\n-\tint sel50, sel100, freqsel;\n+\tint mode = host->mmc->selected_mode;\n \tu32 otap_del_sel;\n \tu32 mask, val;\n \tint ret;\n@@ -148,75 +270,29 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host)\n \tsdhci_set_clock(host->mmc, speed);\n \n \t/* switch phy back on */\n-\tif (speed > AM654_SDHCI_MIN_FREQ) {\n-\t\totap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];\n-\t\tmask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;\n-\t\tval = (1 << OTAPDLYENA_SHIFT) |\n-\t\t (otap_del_sel << OTAPDLYSEL_SHIFT);\n-\n-\t\t/* Write to STRBSEL for HS400 speed mode */\n-\t\tif (host->mmc->selected_mode == MMC_HS_400) {\n-\t\t\tif (plat->flags & STRBSEL_4_BIT)\n-\t\t\t\tmask |= STRBSEL_4BIT_MASK;\n-\t\t\telse\n-\t\t\t\tmask |= STRBSEL_8BIT_MASK;\n-\n-\t\t\tval |= plat->strb_sel << STRBSEL_SHIFT;\n-\t\t}\n+\totap_del_sel = plat->otap_del_sel[mode];\n+\tmask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;\n+\tval = (1 << OTAPDLYENA_SHIFT) |\n+\t (otap_del_sel << OTAPDLYSEL_SHIFT);\n \n-\t\tregmap_update_bits(plat->base, PHY_CTRL4, mask, val);\n-\n-\t\tif (plat->flags & FREQSEL_2_BIT) {\n-\t\t\tswitch (speed) {\n-\t\t\tcase 200000000:\n-\t\t\t\tsel50 = 0;\n-\t\t\t\tsel100 = 0;\n-\t\t\t\tbreak;\n-\t\t\tcase 100000000:\n-\t\t\t\tsel50 = 0;\n-\t\t\t\tsel100 = 1;\n-\t\t\t\tbreak;\n-\t\t\tdefault:\n-\t\t\t\tsel50 = 1;\n-\t\t\t\tsel100 = 0;\n-\t\t\t}\n-\n-\t\t\t/* Configure PHY DLL frequency */\n-\t\t\tmask = SEL50_MASK | SEL100_MASK;\n-\t\t\tval = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);\n-\t\t\tregmap_update_bits(plat->base, PHY_CTRL5, mask, val);\n-\t\t} else {\n-\t\t\tswitch (speed) {\n-\t\t\tcase 200000000:\n-\t\t\t\tfreqsel = 0x0;\n-\t\t\t\tbreak;\n-\t\t\tdefault:\n-\t\t\t\tfreqsel = 0x4;\n-\t\t\t}\n-\t\t\tregmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,\n-\t\t\t\t\t freqsel << FREQSEL_SHIFT);\n-\t\t}\n+\t/* Write to STRBSEL for HS400 speed mode */\n+\tif (host->mmc->selected_mode == MMC_HS_400) {\n+\t\tif (plat->flags & STRBSEL_4_BIT)\n+\t\t\tmask |= STRBSEL_4BIT_MASK;\n+\t\telse\n+\t\t\tmask |= STRBSEL_8BIT_MASK;\n \n-\t\t/* Configure DLL TRIM */\n-\t\tmask = DLL_TRIM_ICP_MASK;\n-\t\tval = plat->trm_icp << DLL_TRIM_ICP_SHIFT;\n-\n-\t\t/* Configure DLL driver strength */\n-\t\tmask |= DR_TY_MASK;\n-\t\tval |= plat->drv_strength << DR_TY_SHIFT;\n-\t\tregmap_update_bits(plat->base, PHY_CTRL1, mask, val);\n-\n-\t\t/* Enable DLL */\n-\t\tregmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,\n-\t\t\t\t 0x1 << ENDLL_SHIFT);\n-\t\t/*\n-\t\t * Poll for DLL ready. Use a one second timeout.\n-\t\t * Works in all experiments done so far\n-\t\t */\n-\t\tret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,\n-\t\t\t\t\t val & DLLRDY_MASK, 1000, 1000000);\n+\t\tval |= plat->strb_sel << STRBSEL_SHIFT;\n+\t}\n+\n+\tregmap_update_bits(plat->base, PHY_CTRL4, mask, val);\n+\n+\tif (mode > UHS_SDR25 && speed >= CLOCK_TOO_SLOW_HZ) {\n+\t\tret = am654_sdhci_setup_dll(plat, speed);\n \t\tif (ret)\n \t\t\treturn ret;\n+\t} else {\n+\t\tam654_sdhci_setup_delay_chain(plat, mode);\n \t}\n \n \treturn 0;\n@@ -354,15 +430,20 @@ static int sdhci_am654_get_otap_delay(struct udevice *dev,\n \t * value is not found\n \t */\n \tfor (i = MMC_HS; i <= MMC_HS_400; i++) {\n-\t\tret = dev_read_u32(dev, td[i].binding, &plat->otap_del_sel[i]);\n+\t\tret = dev_read_u32(dev, td[i].otap_binding,\n+\t\t\t\t &plat->otap_del_sel[i]);\n \t\tif (ret) {\n-\t\t\tdev_dbg(dev, \"Couldn't find %s\\n\", td[i].binding);\n+\t\t\tdev_dbg(dev, \"Couldn't find %s\\n\", td[i].otap_binding);\n \t\t\t/*\n \t\t\t * Remove the corresponding capability\n \t\t\t * if an otap-del-sel value is not found\n \t\t\t */\n \t\t\tcfg->host_caps &= ~td[i].capability;\n \t\t}\n+\n+\t\tif (td[i].itap_binding)\n+\t\t\tdev_read_u32(dev, td[i].itap_binding,\n+\t\t\t\t &plat->itap_del_sel[i]);\n \t}\n \n \treturn 0;\n", "prefixes": [ "06/17" ] }