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GET /api/patches/1372981/?format=api
{ "id": 1372981, "url": "http://patchwork.ozlabs.org/api/patches/1372981/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/1601345449-14676-1-git-send-email-willy.liu@realtek.com/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1601345449-14676-1-git-send-email-willy.liu@realtek.com>", "list_archive_url": null, "date": "2020-09-29T02:10:49", "name": "[net,v4] net: phy: realtek: fix rtl8211e rx/tx delay config", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "7304f25203c89c9c9fc753adbcc4e5599b7c9c99", "submitter": { "id": 80123, "url": "http://patchwork.ozlabs.org/api/people/80123/?format=api", "name": "Willy Liu", "email": "willy.liu@realtek.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/1601345449-14676-1-git-send-email-willy.liu@realtek.com/mbox/", "series": [ { "id": 204719, "url": "http://patchwork.ozlabs.org/api/series/204719/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=204719", "date": "2020-09-29T02:10:49", "name": "[net,v4] net: phy: realtek: fix rtl8211e rx/tx delay config", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/204719/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1372981/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1372981/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming-netdev@ozlabs.org", "Delivered-To": "patchwork-incoming-netdev@ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=23.128.96.18; helo=vger.kernel.org;\n envelope-from=netdev-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=none (p=none dis=none) header.from=realtek.com" ], "Received": [ "from vger.kernel.org (vger.kernel.org [23.128.96.18])\n\tby ozlabs.org (Postfix) with ESMTP id 4C0jYv4mw5z9sSG\n\tfor <patchwork-incoming-netdev@ozlabs.org>;\n Tue, 29 Sep 2020 12:11:47 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n id S1727338AbgI2CLm (ORCPT\n <rfc822;patchwork-incoming-netdev@ozlabs.org>);\n Mon, 28 Sep 2020 22:11:42 -0400", "from rtits2.realtek.com ([211.75.126.72]:51392 \"EHLO\n rtits2.realtek.com.tw\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n with ESMTP id S1726379AbgI2CLm (ORCPT\n <rfc822;netdev@vger.kernel.org>); Mon, 28 Sep 2020 22:11:42 -0400", "from mail.realtek.com (rtexmb04.realtek.com.tw[172.21.6.97])\n by rtits2.realtek.com.tw (8.15.2/2.66/5.86) with ESMTPS id\n 08T2B4Cr8011723\n (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128\n verify=NOT);\n Tue, 29 Sep 2020 10:11:04 +0800", "from localhost.localdomain (172.21.179.130) by\n RTEXMB04.realtek.com.tw (172.21.6.97) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.1.2044.4; Tue, 29 Sep 2020 10:11:04 +0800" ], "Authenticated-By": "", "X-SpamFilter-By": "ArmorX SpamTrap 5.69 with qID 08T2B4Cr8011723,\n This message is accepted by code: ctloc85258", "From": "Willy Liu <willy.liu@realtek.com>", "To": "<andrew@lunn.ch>", "CC": "<hkallweit1@gmail.com>, <linux@armlinux.org.uk>,\n <davem@davemloft.net>, <kuba@kernel.org>,\n <fancer.lancer@gmail.com>, <netdev@vger.kernel.org>,\n <linux-kernel@vger.kernel.org>, <kevans@FreeBSD.org>,\n <ryankao@realtek.com>, Willy Liu <willy.liu@realtek.com>", "Subject": "[PATCH net v4] net: phy: realtek: fix rtl8211e rx/tx delay config", "Date": "Tue, 29 Sep 2020 10:10:49 +0800", "Message-ID": "<1601345449-14676-1-git-send-email-willy.liu@realtek.com>", "X-Mailer": "git-send-email 1.9.1", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.21.179.130]", "X-ClientProxiedBy": "RTEXMB01.realtek.com.tw (172.21.6.94) To\n RTEXMB04.realtek.com.tw (172.21.6.97)", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "There are two chip pins named TXDLY and RXDLY which actually adds the 2ns\ndelays to TXC and RXC for TXD/RXD latching. These two pins can config via\n4.7k-ohm resistor to 3.3V hw setting, but also config via software setting\n(extension page 0xa4 register 0x1c bit13 12 and 11).\n\nThe configuration register definitions from table 13 official PHY datasheet:\nPHYAD[2:0] = PHY Address\nAN[1:0] = Auto-Negotiation\nMode = Interface Mode Select\nRX Delay = RX Delay\nTX Delay = TX Delay\nSELRGV = RGMII/GMII Selection\n\nThis table describes how to config these hw pins via external pull-high or pull-\nlow resistor.\n\nIt is a misunderstanding that mapping it as register bits below:\n8:6 = PHY Address\n5:4 = Auto-Negotiation\n3 = Interface Mode Select\n2 = RX Delay\n1 = TX Delay\n0 = SELRGV\nSo I removed these descriptions above and add related settings as below:\n14 = reserved\n13 = force Tx RX Delay controlled by bit12 bit11\n12 = Tx Delay\n11 = Rx Delay\n10:0 = Test && debug settings reserved by realtek\n\nTest && debug settings are not recommend to modify by default.\n\nFixes: f81dadbcf7fd (\"net: phy: realtek: Add rtl8211e rx/tx delays config\")\nSigned-off-by: Willy Liu <willy.liu@realtek.com>\n---\n drivers/net/phy/realtek.c | 31 ++++++++++++++++---------------\n 1 file changed, 16 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c\nindex 95dbe5e..0f09609 100644\n--- a/drivers/net/phy/realtek.c\n+++ b/drivers/net/phy/realtek.c\n@@ -1,6 +1,5 @@\n // SPDX-License-Identifier: GPL-2.0+\n-/*\n- * drivers/net/phy/realtek.c\n+/* drivers/net/phy/realtek.c\n *\n * Driver for Realtek PHYs\n *\n@@ -32,9 +31,9 @@\n #define RTL8211F_TX_DELAY\t\t\tBIT(8)\n #define RTL8211F_RX_DELAY\t\t\tBIT(3)\n \n-#define RTL8211E_TX_DELAY\t\t\tBIT(1)\n-#define RTL8211E_RX_DELAY\t\t\tBIT(2)\n-#define RTL8211E_MODE_MII_GMII\t\t\tBIT(3)\n+#define RTL8211E_CTRL_DELAY\t\t\tBIT(13)\n+#define RTL8211E_TX_DELAY\t\t\tBIT(12)\n+#define RTL8211E_RX_DELAY\t\t\tBIT(11)\n \n #define RTL8201F_ISR\t\t\t\t0x1e\n #define RTL8201F_IER\t\t\t\t0x13\n@@ -246,16 +245,16 @@ static int rtl8211e_config_init(struct phy_device *phydev)\n \t/* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */\n \tswitch (phydev->interface) {\n \tcase PHY_INTERFACE_MODE_RGMII:\n-\t\tval = 0;\n+\t\tval = RTL8211E_CTRL_DELAY | 0;\n \t\tbreak;\n \tcase PHY_INTERFACE_MODE_RGMII_ID:\n-\t\tval = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;\n+\t\tval = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;\n \t\tbreak;\n \tcase PHY_INTERFACE_MODE_RGMII_RXID:\n-\t\tval = RTL8211E_RX_DELAY;\n+\t\tval = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;\n \t\tbreak;\n \tcase PHY_INTERFACE_MODE_RGMII_TXID:\n-\t\tval = RTL8211E_TX_DELAY;\n+\t\tval = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;\n \t\tbreak;\n \tdefault: /* the rest of the modes imply leaving delays as is. */\n \t\treturn 0;\n@@ -263,11 +262,12 @@ static int rtl8211e_config_init(struct phy_device *phydev)\n \n \t/* According to a sample driver there is a 0x1c config register on the\n \t * 0xa4 extension page (0x7) layout. It can be used to disable/enable\n-\t * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. It can\n-\t * also be used to customize the whole configuration register:\n-\t * 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select,\n-\t * 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet\n-\t * for details).\n+\t * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.\n+\t * The configuration register definition:\n+\t * 14 = reserved\n+\t * 13 = Force Tx RX Delay controlled by bit12 bit11,\n+\t * 12 = RX Delay, 11 = TX Delay\n+\t * 10:0 = Test && debug settings reserved by realtek\n \t */\n \toldpage = phy_select_page(phydev, 0x7);\n \tif (oldpage < 0)\n@@ -277,7 +277,8 @@ static int rtl8211e_config_init(struct phy_device *phydev)\n \tif (ret)\n \t\tgoto err_restore_page;\n \n-\tret = __phy_modify(phydev, 0x1c, RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,\n+\tret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY\n+\t\t\t | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,\n \t\t\t val);\n \n err_restore_page:\n", "prefixes": [ "net", "v4" ] }