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GET /api/patches/1326514/?format=api
{ "id": 1326514, "url": "http://patchwork.ozlabs.org/api/patches/1326514/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200710052340.737567-16-oohall@gmail.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20200710052340.737567-16-oohall@gmail.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20200710052340.737567-16-oohall@gmail.com/", "date": "2020-07-10T05:23:40", "name": "[15/15] powerpc/powernv/sriov: Make single PE mode a per-BAR setting", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "28e539a5254030d0738aee32b88962cc947e87bc", "submitter": { "id": 68108, "url": "http://patchwork.ozlabs.org/api/people/68108/?format=api", "name": "Oliver O'Halloran", "email": "oohall@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200710052340.737567-16-oohall@gmail.com/mbox/", "series": [ { "id": 188782, "url": "http://patchwork.ozlabs.org/api/series/188782/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=188782", "date": "2020-07-10T05:23:26", "name": "[01/15] powernv/pci: Add pci_bus_to_pnvhb() helper", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/188782/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1326514/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1326514/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4B32Sh4crlz9s1x\n\tfor <patchwork-incoming@ozlabs.org>; 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a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=LTkdFSYks9dc0G797VzG05/ZL9Ctkr0EVzOGJ7m6rts=;\n b=NRD1CgKgIq+tGdNRXCMPt9e7BkEpnfUeP0FYR8tGzQ17ymul+8O9640pstGwyQeSzI\n frpHGuzQc2MH7PDtbnBu2se4LhtbLHbbi9ocZ7yk5poGICjkfq16x0vHnxMxypOkpZ8b\n c0TLLTlyzci7p4wrotk0PkdB7zeKFyphWXhtgnosTBJyPG7v9bwS9IVCmGzZr8k8t/Ai\n MsFYJ6hzEK5AZZj/aoEbVfx8JbxoVvU4bAuBNPNgVVPR6Vs3c5VYIYWxeL7D1uBB8Mdt\n QyN7js8/qvFXEAEAYM34HxMdrfoLcugZ3ChKluF48L11swCz2gSGKjA6k7xe4Mp20Esk\n Tt6w==", "X-Gm-Message-State": "AOAM531ZQcY1q7QinIdDuHMAzERFLnVkwKj1l4QIHnLR+u5msjpGbQIf\n j63MbH99L7Q2tcZaMazTY1VPSoAgdXk=", "X-Google-Smtp-Source": "\n ABdhPJx4RdXKxuG3+gExkyfnes6L6uC8JB6KbIAwAJPEPv8YAyluzUC4wUx/Uc6alyyLGxXZt/AUDw==", "X-Received": "by 2002:a1c:cc0c:: with SMTP id h12mr3541943wmb.140.1594358670766;\n Thu, 09 Jul 2020 22:24:30 -0700 (PDT)", "From": "Oliver O'Halloran <oohall@gmail.com>", "To": "linuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH 15/15] powerpc/powernv/sriov: Make single PE mode a per-BAR\n setting", "Date": "Fri, 10 Jul 2020 15:23:40 +1000", "Message-Id": "<20200710052340.737567-16-oohall@gmail.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20200710052340.737567-1-oohall@gmail.com>", "References": "<20200710052340.737567-1-oohall@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List <linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Oliver O'Halloran <oohall@gmail.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n <linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Using single PE BARs to map an SR-IOV BAR is really a choice about what\nstrategy to use when mapping a BAR. It doesn't make much sense for this to\nbe a global setting since a device might have one large BAR which needs to\nbe mapped with single PE windows and another smaller BAR that can be mapped\nwith a regular segmented window. Make the segmented vs single decision a\nper-BAR setting and clean up the logic that decides which mode to use.\n\nSigned-off-by: Oliver O'Halloran <oohall@gmail.com>\n---\n arch/powerpc/platforms/powernv/pci-sriov.c | 131 +++++++++++----------\n arch/powerpc/platforms/powernv/pci.h | 10 +-\n 2 files changed, 75 insertions(+), 66 deletions(-)", "diff": "diff --git a/arch/powerpc/platforms/powernv/pci-sriov.c b/arch/powerpc/platforms/powernv/pci-sriov.c\nindex 8de03636888a..87377d95d648 100644\n--- a/arch/powerpc/platforms/powernv/pci-sriov.c\n+++ b/arch/powerpc/platforms/powernv/pci-sriov.c\n@@ -146,10 +146,9 @@\n static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)\n {\n \tstruct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);\n-\tconst resource_size_t gate = phb->ioda.m64_segsize >> 2;\n \tstruct resource *res;\n \tint i;\n-\tresource_size_t size, total_vf_bar_sz;\n+\tresource_size_t vf_bar_sz;\n \tstruct pnv_iov_data *iov;\n \tint mul, total_vfs;\n \n@@ -158,9 +157,9 @@ static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)\n \t\tgoto disable_iov;\n \tpdev->dev.archdata.iov_data = iov;\n \n+\t/* FIXME: totalvfs > phb->ioda.total_pe_num is going to be a problem */\n \ttotal_vfs = pci_sriov_get_totalvfs(pdev);\n \tmul = phb->ioda.total_pe_num;\n-\ttotal_vf_bar_sz = 0;\n \n \tfor (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {\n \t\tres = &pdev->resource[i + PCI_IOV_RESOURCES];\n@@ -173,50 +172,51 @@ static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)\n \t\t\tgoto disable_iov;\n \t\t}\n \n-\t\ttotal_vf_bar_sz += pci_iov_resource_size(pdev,\n-\t\t\t\ti + PCI_IOV_RESOURCES);\n+\t\tvf_bar_sz = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);\n \n \t\t/*\n-\t\t * If bigger than quarter of M64 segment size, just round up\n-\t\t * power of two.\n+\t\t * Generally, one segmented M64 BAR maps one IOV BAR. However,\n+\t\t * if a VF BAR is too large we end up wasting a lot of space.\n+\t\t * If we've got a BAR that's bigger than greater than 1/4 of the\n+\t\t * default window's segment size then switch to using single PE\n+\t\t * windows. This limits the total number of VFs we can support.\n \t\t *\n-\t\t * Generally, one M64 BAR maps one IOV BAR. To avoid conflict\n-\t\t * with other devices, IOV BAR size is expanded to be\n-\t\t * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64\n-\t\t * segment size , the expanded size would equal to half of the\n-\t\t * whole M64 space size, which will exhaust the M64 Space and\n-\t\t * limit the system flexibility. This is a design decision to\n-\t\t * set the boundary to quarter of the M64 segment size.\n+\t\t * The 1/4 limit is arbitrary and can be tweaked.\n \t\t */\n-\t\tif (total_vf_bar_sz > gate) {\n-\t\t\tmul = roundup_pow_of_two(total_vfs);\n-\t\t\tdev_info(&pdev->dev,\n-\t\t\t\t\"VF BAR Total IOV size %llx > %llx, roundup to %d VFs\\n\",\n-\t\t\t\ttotal_vf_bar_sz, gate, mul);\n-\t\t\tiov->m64_single_mode = true;\n-\t\t\tbreak;\n-\t\t}\n-\t}\n+\t\tif (vf_bar_sz > (phb->ioda.m64_segsize >> 2)) {\n+\t\t\t/*\n+\t\t\t * On PHB3, the minimum size alignment of M64 BAR in\n+\t\t\t * single mode is 32MB. If this VF BAR is smaller than\n+\t\t\t * 32MB, but still too large for a segmented window\n+\t\t\t * then we can't map it and need to disable SR-IOV for\n+\t\t\t * this device.\n+\t\t\t */\n+\t\t\tif (vf_bar_sz < SZ_32M) {\n+\t\t\t\tpci_err(pdev, \"VF BAR%d: %pR can't be mapped in single PE mode\\n\",\n+\t\t\t\t\ti, res);\n+\t\t\t\tgoto disable_iov;\n+\t\t\t}\n \n-\tfor (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {\n-\t\tres = &pdev->resource[i + PCI_IOV_RESOURCES];\n-\t\tif (!res->flags || res->parent)\n+\t\t\tiov->m64_single_mode[i] = true;\n \t\t\tcontinue;\n+\t\t}\n+\n \n-\t\tsize = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);\n \t\t/*\n-\t\t * On PHB3, the minimum size alignment of M64 BAR in single\n-\t\t * mode is 32MB.\n+\t\t * This BAR can be mapped with one segmented window, so adjust\n+\t\t * te resource size to accommodate.\n \t\t */\n-\t\tif (iov->m64_single_mode && (size < SZ_32M))\n-\t\t\tgoto disable_iov;\n+\t\tpci_dbg(pdev, \" Fixing VF BAR%d: %pR to\\n\", i, res);\n+\t\tres->end = res->start + vf_bar_sz * mul - 1;\n+\t\tpci_dbg(pdev, \" %pR\\n\", res);\n \n-\t\tdev_dbg(&pdev->dev, \" Fixing VF BAR%d: %pR to\\n\", i, res);\n-\t\tres->end = res->start + size * mul - 1;\n-\t\tdev_dbg(&pdev->dev, \" %pR\\n\", res);\n-\t\tdev_info(&pdev->dev, \"VF BAR%d: %pR (expanded to %d VFs for PE alignment)\",\n+\t\tpci_info(pdev, \"VF BAR%d: %pR (expanded to %d VFs for PE alignment)\",\n \t\t\t i, res, mul);\n+\n+\t\tiov->need_shift = true;\n \t}\n+\n+\t// what should this be?\n \tiov->vfs_expanded = mul;\n \n \treturn;\n@@ -260,42 +260,42 @@ void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev)\n resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,\n \t\t\t\t\t\t int resno)\n {\n-\tstruct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);\n \tstruct pnv_iov_data *iov = pnv_iov_get(pdev);\n \tresource_size_t align;\n \n-\t/*\n-\t * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the\n-\t * SR-IOV. While from hardware perspective, the range mapped by M64\n-\t * BAR should be size aligned.\n-\t *\n-\t * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra\n-\t * powernv-specific hardware restriction is gone. But if just use the\n-\t * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with\n-\t * in one segment of M64 #15, which introduces the PE conflict between\n-\t * PF and VF. Based on this, the minimum alignment of an IOV BAR is\n-\t * m64_segsize.\n-\t *\n-\t * This function returns the total IOV BAR size if M64 BAR is in\n-\t * Shared PE mode or just VF BAR size if not.\n-\t * If the M64 BAR is in Single PE mode, return the VF BAR size or\n-\t * M64 segment size if IOV BAR size is less.\n-\t */\n-\talign = pci_iov_resource_size(pdev, resno);\n+\tint bar_no = resno - PCI_IOV_RESOURCES;\n \n \t/*\n \t * iov can be null if we have an SR-IOV device with IOV BAR that can't\n \t * be placed in the m64 space (i.e. The BAR is 32bit or non-prefetch).\n-\t * In that case we don't allow VFs to be enabled so just return the\n-\t * default alignment.\n+\t * In that case we don't allow VFs to be enabled since one of their\n+\t * BARs would not be placed in the correct PE.\n \t */\n \tif (!iov)\n \t\treturn align;\n \tif (!iov->vfs_expanded)\n \t\treturn align;\n-\tif (iov->m64_single_mode)\n-\t\treturn max(align, (resource_size_t)phb->ioda.m64_segsize);\n \n+\talign = pci_iov_resource_size(pdev, resno);\n+\n+\t/*\n+\t * If we're using single mode then we can just use the native VF BAR\n+\t * alignment. We validated that it's possible to use a single PE\n+\t * window above when we did the fixup.\n+\t */\n+\tif (iov->m64_single_mode[bar_no])\n+\t\treturn align;\n+\n+\t/*\n+\t * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the\n+\t * SR-IOV. While from hardware perspective, the range mapped by M64\n+\t * BAR should be size aligned.\n+\t *\n+\t * This function returns the total IOV BAR size if M64 BAR is in\n+\t * Shared PE mode or just VF BAR size if not.\n+\t * If the M64 BAR is in Single PE mode, return the VF BAR size or\n+\t * M64 segment size if IOV BAR size is less.\n+\t */\n \treturn iov->vfs_expanded * align;\n }\n \n@@ -453,7 +453,7 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)\n \t\t\tcontinue;\n \n \t\t/* don't need single mode? map everything in one go! */\n-\t\tif (!iov->m64_single_mode) {\n+\t\tif (!iov->m64_single_mode[i]) {\n \t\t\twin = pnv_pci_alloc_m64_bar(phb, iov);\n \t\t\tif (win < 0)\n \t\t\t\tgoto m64_failed;\n@@ -546,6 +546,8 @@ static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)\n \t\tres = &dev->resource[i + PCI_IOV_RESOURCES];\n \t\tif (!res->flags || !res->parent)\n \t\t\tcontinue;\n+\t\tif (iov->m64_single_mode[i])\n+\t\t\tcontinue;\n \n \t\t/*\n \t\t * The actual IOV BAR range is determined by the start address\n@@ -577,6 +579,8 @@ static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)\n \t\tres = &dev->resource[i + PCI_IOV_RESOURCES];\n \t\tif (!res->flags || !res->parent)\n \t\t\tcontinue;\n+\t\tif (iov->m64_single_mode[i])\n+\t\t\tcontinue;\n \n \t\tsize = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);\n \t\tres2 = *res;\n@@ -622,8 +626,8 @@ static void pnv_pci_sriov_disable(struct pci_dev *pdev)\n \t/* Release VF PEs */\n \tpnv_ioda_release_vf_PE(pdev);\n \n-\t/* Un-shift the IOV BAR resources */\n-\tif (!iov->m64_single_mode)\n+\t/* Un-shift the IOV BARs if we need to */\n+\tif (iov->need_shift)\n \t\tpnv_pci_vf_resource_shift(pdev, -base_pe);\n \n \t/* Release M64 windows */\n@@ -741,9 +745,8 @@ static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)\n \t * the IOV BAR according to the PE# allocated to the VFs.\n \t * Otherwise, the PE# for the VF will conflict with others.\n \t */\n-\tif (!iov->m64_single_mode) {\n-\t\tret = pnv_pci_vf_resource_shift(pdev,\n-\t\t\t\t\t\tbase_pe->pe_number);\n+\tif (iov->need_shift) {\n+\t\tret = pnv_pci_vf_resource_shift(pdev, base_pe->pe_number);\n \t\tif (ret)\n \t\t\tgoto shift_failed;\n \t}\ndiff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h\nindex 13555bc549f4..a78d1feb8fb8 100644\n--- a/arch/powerpc/platforms/powernv/pci.h\n+++ b/arch/powerpc/platforms/powernv/pci.h\n@@ -236,14 +236,20 @@ struct pnv_iov_data {\n \t/* number of VFs IOV BAR expanded. FIXME: rename this to something less bad */\n \tu16 vfs_expanded;\n \n+\t/*\n+\t * indicates if we need to move our IOV BAR to account for our\n+\t * allocated PE number when enabling VFs.\n+\t */\n+\tbool need_shift;\n+\n \t/* number of VFs enabled */\n \tu16 num_vfs;\n \n \t/* pointer to the array of VF PEs. num_vfs long*/\n \tstruct pnv_ioda_pe *vf_pe_arr;\n \n-\t/* Did we map the VF BARs with single-PE IODA BARs? */\n-\tbool m64_single_mode;\n+\t/* Did we map the VF BAR with single-PE IODA BARs? */\n+\tbool m64_single_mode[PCI_SRIOV_NUM_BARS];\n \n \t/*\n \t * Bit mask used to track which m64 windows that we used to map the\n", "prefixes": [ "15/15" ] }