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GET /api/patches/1326512/?format=api
{ "id": 1326512, "url": "http://patchwork.ozlabs.org/api/patches/1326512/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200710052340.737567-14-oohall@gmail.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20200710052340.737567-14-oohall@gmail.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20200710052340.737567-14-oohall@gmail.com/", "date": "2020-07-10T05:23:38", "name": "[13/15] powerpc/powernv/sriov: Move M64 BAR allocation into a helper", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "466874794f61aa3868eb4ef86ec6afa59ded58e4", "submitter": { "id": 68108, "url": "http://patchwork.ozlabs.org/api/people/68108/?format=api", "name": "Oliver O'Halloran", "email": "oohall@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200710052340.737567-14-oohall@gmail.com/mbox/", "series": [ { "id": 188782, "url": "http://patchwork.ozlabs.org/api/series/188782/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=188782", "date": "2020-07-10T05:23:26", "name": "[01/15] powernv/pci: Add pci_bus_to_pnvhb() helper", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/188782/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1326512/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1326512/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4B32N64Qndz9s1x\n\tfor <patchwork-incoming@ozlabs.org>; Fri, 10 Jul 2020 15:56:06 +1000 (AEST)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4B32N63gBczDr6t\n\tfor <patchwork-incoming@ozlabs.org>; Fri, 10 Jul 2020 15:56:06 +1000 (AEST)", "from mail-wr1-x441.google.com (mail-wr1-x441.google.com\n [IPv6:2a00:1450:4864:20::441])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by lists.ozlabs.org (Postfix) with ESMTPS id 4B31gc6rqszDrG2\n for <linuxppc-dev@lists.ozlabs.org>; Fri, 10 Jul 2020 15:24:28 +1000 (AEST)", "by mail-wr1-x441.google.com with SMTP id z2so4575754wrp.2\n for <linuxppc-dev@lists.ozlabs.org>; Thu, 09 Jul 2020 22:24:28 -0700 (PDT)", "from 192-168-1-18.tpgi.com.au ([220.240.245.68])\n by smtp.gmail.com with ESMTPSA id 92sm9090941wrr.96.2020.07.09.22.24.24\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 09 Jul 2020 22:24:25 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20161025 header.b=kE6fw/2R;\n\tdkim-atps=neutral", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n smtp.mailfrom=gmail.com (client-ip=2a00:1450:4864:20::441;\n helo=mail-wr1-x441.google.com; envelope-from=oohall@gmail.com;\n receiver=<UNKNOWN>)", "lists.ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "lists.ozlabs.org; dkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20161025 header.b=kE6fw/2R; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=XUxLjLbDTYPDEi7E9qhfkUQ6YJD3u2Zjb67u2EA9IBc=;\n b=kE6fw/2RwwSg/v1dbkBpfE5n6B3vLNrOYwHjJMH8ylEIQnw2v1lR8u9ZrMm7et07hE\n KlNgXChltwD+oJplM0Ood9ozQPm8tnpFkEUgyViWVlUjQx+jT7t/RMD5h8EWIPilScQh\n nTWkOtMqD8GOTnklyghAP6EmElQJK3TYe7M4BNkodKfiTLB315vDrH3XAlCZm+FkYp4b\n R2W57705OzTpbZ4DzBHuViq6gOSEA0eQgfcbKGxXLCRiWGM+J9FAECT2fN56/ieeyRX4\n ZeQsy7+BFs8BwEcLEL6lUiGoWi/atU5lhBepEzmWnXhAj0lj7rbGjUsxSrkLabWS9rLN\n O4PA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=XUxLjLbDTYPDEi7E9qhfkUQ6YJD3u2Zjb67u2EA9IBc=;\n b=o0FN6TUAUJAF/PBjVyevP0ecIKQmgiqN5mbb+3utw5Yq/85CbJmTpdpUMKwDRwOppJ\n +iTUyu0Hv4sreSSbZpfuPVORzZc+nr8ZRl2rWlll/GlcTQ57/Dpu28L62YKpMSmfaBek\n a6PakGftdvIYrTIjCP7SDYIGIG1ns6Cr2sLg6yHGPhHdvHsEFIsK85jHGFKG0NTFYOH8\n /gNYF7NIQT1ODroDs4BRI7Y2seiyAZZFufyPD4qSGSjWbTsPPDKtdEbtNHb4DK4nzZWn\n m0C0p0QKu0gOvDktLdk+1AvKn/Z6I/WAgR3/fUeMpSqdynVhGDhzutIMHa82cF4F8X4u\n ctZA==", "X-Gm-Message-State": "AOAM5327N2p53ULIOk26x+1FhVBP9NqjOFRmLBrGy9bw5RPV26oUfx1S\n 0Swgbfr3FCeclcsTjctxYQ3wuUu7R6c=", "X-Google-Smtp-Source": "\n ABdhPJzEK3tKpjrNJfrUKkGMflNhBGQVQ6fLcw4ORQo8CENOszQSIqGClEIXBh+YEIVGEtGsTs3nmg==", "X-Received": "by 2002:adf:efcc:: with SMTP id\n i12mr65354547wrp.349.1594358666020;\n Thu, 09 Jul 2020 22:24:26 -0700 (PDT)", "From": "Oliver O'Halloran <oohall@gmail.com>", "To": "linuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH 13/15] powerpc/powernv/sriov: Move M64 BAR allocation into a\n helper", "Date": "Fri, 10 Jul 2020 15:23:38 +1000", "Message-Id": "<20200710052340.737567-14-oohall@gmail.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20200710052340.737567-1-oohall@gmail.com>", "References": "<20200710052340.737567-1-oohall@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List <linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Oliver O'Halloran <oohall@gmail.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n <linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "I want to refactor the loop this code is currently inside of. Hoist it on\nout.\n\nSigned-off-by: Oliver O'Halloran <oohall@gmail.com>\n---\n arch/powerpc/platforms/powernv/pci-sriov.c | 31 ++++++++++++++--------\n 1 file changed, 20 insertions(+), 11 deletions(-)", "diff": "diff --git a/arch/powerpc/platforms/powernv/pci-sriov.c b/arch/powerpc/platforms/powernv/pci-sriov.c\nindex d5699cd2ab7a..2f967aa4fbf5 100644\n--- a/arch/powerpc/platforms/powernv/pci-sriov.c\n+++ b/arch/powerpc/platforms/powernv/pci-sriov.c\n@@ -416,6 +416,23 @@ static int64_t pnv_ioda_map_m64_single(struct pnv_phb *phb,\n \treturn rc;\n }\n \n+static int pnv_pci_alloc_m64_bar(struct pnv_phb *phb, struct pnv_iov_data *iov)\n+{\n+\tint win;\n+\n+\tdo {\n+\t\twin = find_next_zero_bit(&phb->ioda.m64_bar_alloc,\n+\t\t\t\tphb->ioda.m64_bar_idx + 1, 0);\n+\n+\t\tif (win >= phb->ioda.m64_bar_idx + 1)\n+\t\t\treturn -1;\n+\t} while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));\n+\n+\tset_bit(win, iov->used_m64_bar_mask);\n+\n+\treturn win;\n+}\n+\n static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)\n {\n \tstruct pnv_iov_data *iov;\n@@ -443,17 +460,9 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)\n \t\t\tcontinue;\n \n \t\tfor (j = 0; j < m64_bars; j++) {\n-\n-\t\t\t/* allocate a window ID for this BAR */\n-\t\t\tdo {\n-\t\t\t\twin = find_next_zero_bit(&phb->ioda.m64_bar_alloc,\n-\t\t\t\t\t\tphb->ioda.m64_bar_idx + 1, 0);\n-\n-\t\t\t\tif (win >= phb->ioda.m64_bar_idx + 1)\n-\t\t\t\t\tgoto m64_failed;\n-\t\t\t} while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));\n-\t\t\tset_bit(win, iov->used_m64_bar_mask);\n-\n+\t\t\twin = pnv_pci_alloc_m64_bar(phb, iov);\n+\t\t\tif (win < 0)\n+\t\t\t\tgoto m64_failed;\n \n \t\t\tif (iov->m64_single_mode) {\n \t\t\t\tint pe_num = iov->vf_pe_arr[j].pe_number;\n", "prefixes": [ "13/15" ] }