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GET /api/patches/1326511/?format=api
{ "id": 1326511, "url": "http://patchwork.ozlabs.org/api/patches/1326511/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200710052340.737567-13-oohall@gmail.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20200710052340.737567-13-oohall@gmail.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20200710052340.737567-13-oohall@gmail.com/", "date": "2020-07-10T05:23:37", "name": "[12/15] powerpc/powernv/sriov: De-indent setup and teardown", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "f4667d8710385aa250a394618103fab4439c2b19", "submitter": { "id": 68108, "url": "http://patchwork.ozlabs.org/api/people/68108/?format=api", "name": "Oliver O'Halloran", "email": "oohall@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200710052340.737567-13-oohall@gmail.com/mbox/", "series": [ { "id": 188782, "url": "http://patchwork.ozlabs.org/api/series/188782/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=188782", "date": "2020-07-10T05:23:26", "name": "[01/15] powernv/pci: Add pci_bus_to_pnvhb() helper", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/188782/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1326511/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1326511/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4B32L21Xg7z9sRf\n\tfor <patchwork-incoming@ozlabs.org>; Fri, 10 Jul 2020 15:54:18 +1000 (AEST)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4B32L16XmFzDrNM\n\tfor <patchwork-incoming@ozlabs.org>; Fri, 10 Jul 2020 15:54:17 +1000 (AEST)", "from mail-wm1-x341.google.com (mail-wm1-x341.google.com\n [IPv6:2a00:1450:4864:20::341])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by lists.ozlabs.org (Postfix) with ESMTPS id 4B31gZ5BNJzDrHb\n for <linuxppc-dev@lists.ozlabs.org>; Fri, 10 Jul 2020 15:24:26 +1000 (AEST)", "by mail-wm1-x341.google.com with SMTP id o8so4536098wmh.4\n for <linuxppc-dev@lists.ozlabs.org>; Thu, 09 Jul 2020 22:24:26 -0700 (PDT)", "from 192-168-1-18.tpgi.com.au ([220.240.245.68])\n by smtp.gmail.com with ESMTPSA id 92sm9090941wrr.96.2020.07.09.22.24.21\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 09 Jul 2020 22:24:23 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20161025 header.b=Hs+7s5b4;\n\tdkim-atps=neutral", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n smtp.mailfrom=gmail.com (client-ip=2a00:1450:4864:20::341;\n helo=mail-wm1-x341.google.com; envelope-from=oohall@gmail.com;\n receiver=<UNKNOWN>)", "lists.ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "lists.ozlabs.org; dkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20161025 header.b=Hs+7s5b4; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=buWzk/vVB/cujnN2jdBWDrbcMZbWLenLCz2srtZ5Lbc=;\n b=Hs+7s5b44wRfLzfD08uBz7vSuqydC7EcgvNk+wnoj/KWjp3BYs34h/cF7q9HLKnXu0\n s8mP7YQQE7ZeDBsA2rrFkK3lHT7nE17He2vBfONoz+3FaKHyyDS3ZVIysFQ++viunn95\n 1DlaJITO9wcwDwV/Bo0SF1lapCozznEeoFJKCAqo5q5/Gkucjzyo0UeiLGe9IqVNaFkC\n VKhDh4iOF9REjn9DwFJky8z+ffQavQdLQyVmqSl8k31Zl700163R6ipwRkqwBSXDw/wn\n Fdc9QRU4uTmi3sL62o9nzzZGWn4EmZ2DsQ/83n3IYJ+c0TbsomeXsiewje3YfQHCbv6f\n aPuQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=buWzk/vVB/cujnN2jdBWDrbcMZbWLenLCz2srtZ5Lbc=;\n b=ja8rlAMdTHkanEIp0tNp3KTVygQGQvGqZlDlv3dXb3NuDnKudSKzsFg4x3XZ3SX+an\n mwEmZw4WD+xfFIw178Kda6B93WYdlUxAzpX0UOJgd5MPWXHAi8clAAw0j0gDuGsKeyoX\n n5JCNDgLRGBrjN5JmN3DJScdMGY9TmdOcHTdzKcv5lZML8ZKwIYuPe99PfFHLgxUx3M+\n pGnla6V2uRkc6b76mNBKW00s88TP1kfQpayJpwORRohIY9b9sEJotFNAnMQcYoufLynZ\n vhvxdhoHORkojQo4+HvNgel0TScwHPAmCpuKBl5y3JS38fxKdY8iBb0aW+ai8yDu6PEu\n Bk4Q==", "X-Gm-Message-State": "AOAM533pk6x4la3pS9DDw9J7iRJqDkr68xICdZNSzyEOZfZMxE6wYSIj\n ou7GY3i4N1QHUjnCG9zEGd6Awnn9JJE=", "X-Google-Smtp-Source": "\n ABdhPJy7FwouiE7P4bGs/jPme6Gz2RPzA1xCu8fKBDFrbtGXnImBEeYJ2YyPMEmDaODA4T/RwdvpYQ==", "X-Received": "by 2002:a1c:3954:: with SMTP id g81mr3266969wma.73.1594358663720;\n Thu, 09 Jul 2020 22:24:23 -0700 (PDT)", "From": "Oliver O'Halloran <oohall@gmail.com>", "To": "linuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH 12/15] powerpc/powernv/sriov: De-indent setup and teardown", "Date": "Fri, 10 Jul 2020 15:23:37 +1000", "Message-Id": "<20200710052340.737567-13-oohall@gmail.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20200710052340.737567-1-oohall@gmail.com>", "References": "<20200710052340.737567-1-oohall@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List <linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Oliver O'Halloran <oohall@gmail.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n <linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Remove the IODA2 PHB checks. We already assume IODA2 in several places so\nthere's not much point in wrapping most of the setup and teardown process\nin an if block.\n\nSigned-off-by: Oliver O'Halloran <oohall@gmail.com>\n---\n arch/powerpc/platforms/powernv/pci-sriov.c | 86 ++++++++++++----------\n 1 file changed, 49 insertions(+), 37 deletions(-)", "diff": "diff --git a/arch/powerpc/platforms/powernv/pci-sriov.c b/arch/powerpc/platforms/powernv/pci-sriov.c\nindex 08f88187d65a..d5699cd2ab7a 100644\n--- a/arch/powerpc/platforms/powernv/pci-sriov.c\n+++ b/arch/powerpc/platforms/powernv/pci-sriov.c\n@@ -610,16 +610,18 @@ static void pnv_pci_sriov_disable(struct pci_dev *pdev)\n \tnum_vfs = iov->num_vfs;\n \tbase_pe = iov->vf_pe_arr[0].pe_number;\n \n+\tif (WARN_ON(!iov))\n+\t\treturn;\n+\n \t/* Release VF PEs */\n \tpnv_ioda_release_vf_PE(pdev);\n \n-\tif (phb->type == PNV_PHB_IODA2) {\n-\t\tif (!iov->m64_single_mode)\n-\t\t\tpnv_pci_vf_resource_shift(pdev, -base_pe);\n+\t/* Un-shift the IOV BAR resources */\n+\tif (!iov->m64_single_mode)\n+\t\tpnv_pci_vf_resource_shift(pdev, -base_pe);\n \n-\t\t/* Release M64 windows */\n-\t\tpnv_pci_vf_release_m64(pdev, num_vfs);\n-\t}\n+\t/* Release M64 windows */\n+\tpnv_pci_vf_release_m64(pdev, num_vfs);\n }\n \n static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)\n@@ -693,41 +695,51 @@ static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)\n \tphb = pci_bus_to_pnvhb(pdev->bus);\n \tiov = pnv_iov_get(pdev);\n \n-\tif (phb->type == PNV_PHB_IODA2) {\n-\t\tif (!iov->vfs_expanded) {\n-\t\t\tdev_info(&pdev->dev, \"don't support this SRIOV device\"\n-\t\t\t\t\" with non 64bit-prefetchable IOV BAR\\n\");\n-\t\t\treturn -ENOSPC;\n-\t\t}\n+\t/*\n+\t * There's a calls to IODA2 PE setup code littered throughout. We could\n+\t * probably fix that, but we'd still have problems due to the\n+\t * restriction inherent on IODA1 PHBs.\n+\t *\n+\t * NB: We class IODA3 as IODA2 since they're very similar.\n+\t */\n+\tif (phb->type != PNV_PHB_IODA2) {\n+\t\tpci_err(pdev, \"SR-IOV is not supported on this PHB\\n\");\n+\t\treturn -ENXIO;\n+\t}\n \n-\t\t/* allocate a contigious block of PEs for our VFs */\n-\t\tbase_pe = pnv_ioda_alloc_pe(phb, num_vfs);\n-\t\tif (!base_pe) {\n-\t\t\tpci_err(pdev, \"Unable to allocate PEs for %d VFs\\n\", num_vfs);\n-\t\t\treturn -EBUSY;\n-\t\t}\n+\tif (!iov->vfs_expanded) {\n+\t\tdev_info(&pdev->dev, \"don't support this SRIOV device\"\n+\t\t\t\" with non 64bit-prefetchable IOV BAR\\n\");\n+\t\treturn -ENOSPC;\n+\t}\n \n-\t\tiov->vf_pe_arr = base_pe;\n-\t\tiov->num_vfs = num_vfs;\n+\t/* allocate a contigious block of PEs for our VFs */\n+\tbase_pe = pnv_ioda_alloc_pe(phb, num_vfs);\n+\tif (!base_pe) {\n+\t\tpci_err(pdev, \"Unable to allocate PEs for %d VFs\\n\", num_vfs);\n+\t\treturn -EBUSY;\n+\t}\n \n-\t\t/* Assign M64 window accordingly */\n-\t\tret = pnv_pci_vf_assign_m64(pdev, num_vfs);\n-\t\tif (ret) {\n-\t\t\tdev_info(&pdev->dev, \"Not enough M64 window resources\\n\");\n-\t\t\tgoto m64_failed;\n-\t\t}\n+\tiov->vf_pe_arr = base_pe;\n+\tiov->num_vfs = num_vfs;\n \n-\t\t/*\n-\t\t * When using one M64 BAR to map one IOV BAR, we need to shift\n-\t\t * the IOV BAR according to the PE# allocated to the VFs.\n-\t\t * Otherwise, the PE# for the VF will conflict with others.\n-\t\t */\n-\t\tif (!iov->m64_single_mode) {\n-\t\t\tret = pnv_pci_vf_resource_shift(pdev,\n-\t\t\t\t\t\t\tbase_pe->pe_number);\n-\t\t\tif (ret)\n-\t\t\t\tgoto shift_failed;\n-\t\t}\n+\t/* Assign M64 window accordingly */\n+\tret = pnv_pci_vf_assign_m64(pdev, num_vfs);\n+\tif (ret) {\n+\t\tdev_info(&pdev->dev, \"Not enough M64 window resources\\n\");\n+\t\tgoto m64_failed;\n+\t}\n+\n+\t/*\n+\t * When using one M64 BAR to map one IOV BAR, we need to shift\n+\t * the IOV BAR according to the PE# allocated to the VFs.\n+\t * Otherwise, the PE# for the VF will conflict with others.\n+\t */\n+\tif (!iov->m64_single_mode) {\n+\t\tret = pnv_pci_vf_resource_shift(pdev,\n+\t\t\t\t\t\tbase_pe->pe_number);\n+\t\tif (ret)\n+\t\t\tgoto shift_failed;\n \t}\n \n \t/* Setup VF PEs */\n", "prefixes": [ "12/15" ] }