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GET /api/patches/1326510/?format=api
{ "id": 1326510, "url": "http://patchwork.ozlabs.org/api/patches/1326510/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200710052340.737567-12-oohall@gmail.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20200710052340.737567-12-oohall@gmail.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20200710052340.737567-12-oohall@gmail.com/", "date": "2020-07-10T05:23:36", "name": "[11/15] powerpc/powernv/sriov: Drop iov->pe_num_map[]", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "62f26075d1afd929dcb50be6e2c58811ade75b8d", "submitter": { "id": 68108, "url": "http://patchwork.ozlabs.org/api/people/68108/?format=api", "name": "Oliver O'Halloran", "email": "oohall@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200710052340.737567-12-oohall@gmail.com/mbox/", "series": [ { "id": 188782, "url": "http://patchwork.ozlabs.org/api/series/188782/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=188782", "date": "2020-07-10T05:23:26", "name": "[01/15] powernv/pci: Add pci_bus_to_pnvhb() helper", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/188782/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1326510/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1326510/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4B32Hq1dpbz9s1x\n\tfor <patchwork-incoming@ozlabs.org>; Fri, 10 Jul 2020 15:52:23 +1000 (AEST)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4B32Hq06P9zDqSS\n\tfor <patchwork-incoming@ozlabs.org>; Fri, 10 Jul 2020 15:52:23 +1000 (AEST)", "from mail-wm1-x341.google.com (mail-wm1-x341.google.com\n [IPv6:2a00:1450:4864:20::341])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by lists.ozlabs.org (Postfix) with ESMTPS id 4B31gX31qMzDrJC\n for <linuxppc-dev@lists.ozlabs.org>; Fri, 10 Jul 2020 15:24:24 +1000 (AEST)", "by mail-wm1-x341.google.com with SMTP id a6so7665967wmm.0\n for <linuxppc-dev@lists.ozlabs.org>; Thu, 09 Jul 2020 22:24:24 -0700 (PDT)", "from 192-168-1-18.tpgi.com.au ([220.240.245.68])\n by smtp.gmail.com with ESMTPSA id 92sm9090941wrr.96.2020.07.09.22.24.19\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 09 Jul 2020 22:24:21 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20161025 header.b=oSfngKiD;\n\tdkim-atps=neutral", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n smtp.mailfrom=gmail.com (client-ip=2a00:1450:4864:20::341;\n helo=mail-wm1-x341.google.com; envelope-from=oohall@gmail.com;\n receiver=<UNKNOWN>)", "lists.ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "lists.ozlabs.org; dkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20161025 header.b=oSfngKiD; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=TBp/iCn0n7Y1l7vt8/uMkbtGvCDuCAapXCRyx2TQ8Cs=;\n b=oSfngKiDcKvwlkWCLvK0q3GIyo+tCITRdGcNP2sC31BnZGd4YQvS4PesDuzlWWodqX\n aFFHd4eViULTLwUgzlh/VQRYlcyFdAOYvnjg9b/+EHERQmxWbqjKS5hIpcgFRhuivLxq\n HG7RkeUcqSMH0zXSUX+R2nHKTAKaG2HELaL1SBx16e9s1ZStmk9QBRhQpjKrI3TmGEaG\n 0/Ko7G1CtWgXbaao2dsF6JTVbDeSbrvNQYWq1mcDUqu5ry1lwl7duNynniah6A++/O86\n PqQUkXINRXvM/3g6uxIdSO9950qKbGH36/hJDaV61ec8XIteneaZzvuoCYMo8QXOz9QD\n 2Xnw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=TBp/iCn0n7Y1l7vt8/uMkbtGvCDuCAapXCRyx2TQ8Cs=;\n b=E6gzlGwlcU+ibGefzRHFeWoX0ZlYe4RcNINeVw8wprYbiU4gToTwM4xHteP0CF0nTq\n 6NSZsf2raM8V3o7ZU0HUqhDItk/NllRI3MM5dHedNhPrq8kIWHGeOqw2IADNiUkdK3cD\n tYS/SoJzrcF2x/yEuXFnckV1V8q5ExBxbh79MYY1VfUgYQrWpvT5kE8p8cj7eAQpbkNs\n QXb8/Gup+8u6nurtQVIVZI/jx1jXpH19PUbeWtUyZQ3RsNbhreuDDbGmkX5JapG1bEtV\n XLgff9YSG8a/DKj+SbjoNUKjY+YsflqqgQ+lHT0ezDQShtOXDo0HenEqsUWVJ79xsc/R\n dsOw==", "X-Gm-Message-State": "AOAM530vX7ZYF6hRyUhGGGEVLtkiOyt6EgaIgZX6jNVbvPKspL5B6lh1\n WDSTQ8YcoCCtqPcEICi1+lLQOV+Dmdk=", "X-Google-Smtp-Source": "\n ABdhPJyWe7w6uicFmWZ2XkeyKKIcBOwOdiaC7+HAcJZHip6P1vFEpA5NlU6hIb6FpiaBoWJFO71n0g==", "X-Received": "by 2002:a1c:cc12:: with SMTP id h18mr3565383wmb.56.1594358661450;\n Thu, 09 Jul 2020 22:24:21 -0700 (PDT)", "From": "Oliver O'Halloran <oohall@gmail.com>", "To": "linuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH 11/15] powerpc/powernv/sriov: Drop iov->pe_num_map[]", "Date": "Fri, 10 Jul 2020 15:23:36 +1000", "Message-Id": "<20200710052340.737567-12-oohall@gmail.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20200710052340.737567-1-oohall@gmail.com>", "References": "<20200710052340.737567-1-oohall@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List <linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Oliver O'Halloran <oohall@gmail.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n <linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Currently the iov->pe_num_map[] does one of two things depending on\nwhether single PE mode is being used or not. When it is, this contains an\narray which maps a vf_index to the corresponding PE number. When single PE\nmode is not being used this contains a scalar which is the base PE for the\nset of enabled VFs (for for VFn is base + n).\n\nThe array was necessary because when calling pnv_ioda_alloc_pe() there is\nno guarantee that the allocated PEs would be contigious. We can now\nallocate contigious blocks of PEs so this is no longer an issue. This\nallows us to drop the if (single_mode) {} .. else {} block scattered\nthrough the SR-IOV code which is a nice clean up.\n\nSigned-off-by: Oliver O'Halloran <oohall@gmail.com>\n---\n arch/powerpc/platforms/powernv/pci-sriov.c | 109 +++++----------------\n arch/powerpc/platforms/powernv/pci.h | 4 +-\n 2 files changed, 25 insertions(+), 88 deletions(-)", "diff": "diff --git a/arch/powerpc/platforms/powernv/pci-sriov.c b/arch/powerpc/platforms/powernv/pci-sriov.c\nindex d53a85ccb538..08f88187d65a 100644\n--- a/arch/powerpc/platforms/powernv/pci-sriov.c\n+++ b/arch/powerpc/platforms/powernv/pci-sriov.c\n@@ -456,11 +456,13 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)\n \n \n \t\t\tif (iov->m64_single_mode) {\n+\t\t\t\tint pe_num = iov->vf_pe_arr[j].pe_number;\n+\n \t\t\t\tsize = pci_iov_resource_size(pdev,\n \t\t\t\t\t\t\tPCI_IOV_RESOURCES + i);\n \t\t\t\tstart = res->start + size * j;\n \t\t\t\trc = pnv_ioda_map_m64_single(phb, win,\n-\t\t\t\t\t\t\t iov->pe_num_map[j],\n+\t\t\t\t\t\t\t pe_num,\n \t\t\t\t\t\t\t start,\n \t\t\t\t\t\t\t size);\n \t\t\t} else {\n@@ -599,38 +601,24 @@ static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)\n \n static void pnv_pci_sriov_disable(struct pci_dev *pdev)\n {\n+\tu16 num_vfs, base_pe;\n \tstruct pnv_phb *phb;\n-\tstruct pnv_ioda_pe *pe;\n \tstruct pnv_iov_data *iov;\n-\tu16 num_vfs, i;\n \n \tphb = pci_bus_to_pnvhb(pdev->bus);\n \tiov = pnv_iov_get(pdev);\n \tnum_vfs = iov->num_vfs;\n+\tbase_pe = iov->vf_pe_arr[0].pe_number;\n \n \t/* Release VF PEs */\n \tpnv_ioda_release_vf_PE(pdev);\n \n \tif (phb->type == PNV_PHB_IODA2) {\n \t\tif (!iov->m64_single_mode)\n-\t\t\tpnv_pci_vf_resource_shift(pdev, -*iov->pe_num_map);\n+\t\t\tpnv_pci_vf_resource_shift(pdev, -base_pe);\n \n \t\t/* Release M64 windows */\n \t\tpnv_pci_vf_release_m64(pdev, num_vfs);\n-\n-\t\t/* Release PE numbers */\n-\t\tif (iov->m64_single_mode) {\n-\t\t\tfor (i = 0; i < num_vfs; i++) {\n-\t\t\t\tif (iov->pe_num_map[i] == IODA_INVALID_PE)\n-\t\t\t\t\tcontinue;\n-\n-\t\t\t\tpe = &phb->ioda.pe_array[iov->pe_num_map[i]];\n-\t\t\t\tpnv_ioda_free_pe(pe);\n-\t\t\t}\n-\t\t} else\n-\t\t\tbitmap_clear(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs);\n-\t\t/* Releasing pe_num_map */\n-\t\tkfree(iov->pe_num_map);\n \t}\n }\n \n@@ -656,13 +644,7 @@ static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)\n \t\tint vf_bus = pci_iov_virtfn_bus(pdev, vf_index);\n \t\tstruct pci_dn *vf_pdn;\n \n-\t\tif (iov->m64_single_mode)\n-\t\t\tpe_num = iov->pe_num_map[vf_index];\n-\t\telse\n-\t\t\tpe_num = *iov->pe_num_map + vf_index;\n-\n-\t\tpe = &phb->ioda.pe_array[pe_num];\n-\t\tpe->pe_number = pe_num;\n+\t\tpe = &iov->vf_pe_arr[vf_index];\n \t\tpe->phb = phb;\n \t\tpe->flags = PNV_IODA_PE_VF;\n \t\tpe->pbus = NULL;\n@@ -670,6 +652,7 @@ static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)\n \t\tpe->mve_number = -1;\n \t\tpe->rid = (vf_bus << 8) | vf_devfn;\n \n+\t\tpe_num = pe->pe_number;\n \t\tpe_info(pe, \"VF %04d:%02d:%02d.%d associated with PE#%x\\n\",\n \t\t\tpci_domain_nr(pdev->bus), pdev->bus->number,\n \t\t\tPCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num);\n@@ -701,9 +684,9 @@ static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)\n \n static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)\n {\n+\tstruct pnv_ioda_pe *base_pe;\n \tstruct pnv_iov_data *iov;\n \tstruct pnv_phb *phb;\n-\tstruct pnv_ioda_pe *pe;\n \tint ret;\n \tu16 i;\n \n@@ -717,55 +700,14 @@ static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)\n \t\t\treturn -ENOSPC;\n \t\t}\n \n-\t\t/*\n-\t\t * When M64 BARs functions in Single PE mode, the number of VFs\n-\t\t * could be enabled must be less than the number of M64 BARs.\n-\t\t */\n-\t\tif (iov->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {\n-\t\t\tdev_info(&pdev->dev, \"Not enough M64 BAR for VFs\\n\");\n+\t\t/* allocate a contigious block of PEs for our VFs */\n+\t\tbase_pe = pnv_ioda_alloc_pe(phb, num_vfs);\n+\t\tif (!base_pe) {\n+\t\t\tpci_err(pdev, \"Unable to allocate PEs for %d VFs\\n\", num_vfs);\n \t\t\treturn -EBUSY;\n \t\t}\n \n-\t\t/* Allocating pe_num_map */\n-\t\tif (iov->m64_single_mode)\n-\t\t\tiov->pe_num_map = kmalloc_array(num_vfs,\n-\t\t\t\t\t\t\tsizeof(*iov->pe_num_map),\n-\t\t\t\t\t\t\tGFP_KERNEL);\n-\t\telse\n-\t\t\tiov->pe_num_map = kmalloc(sizeof(*iov->pe_num_map), GFP_KERNEL);\n-\n-\t\tif (!iov->pe_num_map)\n-\t\t\treturn -ENOMEM;\n-\n-\t\tif (iov->m64_single_mode)\n-\t\t\tfor (i = 0; i < num_vfs; i++)\n-\t\t\t\tiov->pe_num_map[i] = IODA_INVALID_PE;\n-\n-\t\t/* Calculate available PE for required VFs */\n-\t\tif (iov->m64_single_mode) {\n-\t\t\tfor (i = 0; i < num_vfs; i++) {\n-\t\t\t\tpe = pnv_ioda_alloc_pe(phb);\n-\t\t\t\tif (!pe) {\n-\t\t\t\t\tret = -EBUSY;\n-\t\t\t\t\tgoto m64_failed;\n-\t\t\t\t}\n-\n-\t\t\t\tiov->pe_num_map[i] = pe->pe_number;\n-\t\t\t}\n-\t\t} else {\n-\t\t\tmutex_lock(&phb->ioda.pe_alloc_mutex);\n-\t\t\t*iov->pe_num_map = bitmap_find_next_zero_area(\n-\t\t\t\tphb->ioda.pe_alloc, phb->ioda.total_pe_num,\n-\t\t\t\t0, num_vfs, 0);\n-\t\t\tif (*iov->pe_num_map >= phb->ioda.total_pe_num) {\n-\t\t\t\tmutex_unlock(&phb->ioda.pe_alloc_mutex);\n-\t\t\t\tdev_info(&pdev->dev, \"Failed to enable VF%d\\n\", num_vfs);\n-\t\t\t\tkfree(iov->pe_num_map);\n-\t\t\t\treturn -EBUSY;\n-\t\t\t}\n-\t\t\tbitmap_set(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs);\n-\t\t\tmutex_unlock(&phb->ioda.pe_alloc_mutex);\n-\t\t}\n+\t\tiov->vf_pe_arr = base_pe;\n \t\tiov->num_vfs = num_vfs;\n \n \t\t/* Assign M64 window accordingly */\n@@ -781,9 +723,10 @@ static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)\n \t\t * Otherwise, the PE# for the VF will conflict with others.\n \t\t */\n \t\tif (!iov->m64_single_mode) {\n-\t\t\tret = pnv_pci_vf_resource_shift(pdev, *iov->pe_num_map);\n+\t\t\tret = pnv_pci_vf_resource_shift(pdev,\n+\t\t\t\t\t\t\tbase_pe->pe_number);\n \t\t\tif (ret)\n-\t\t\t\tgoto m64_failed;\n+\t\t\t\tgoto shift_failed;\n \t\t}\n \t}\n \n@@ -792,20 +735,12 @@ static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)\n \n \treturn 0;\n \n-m64_failed:\n-\tif (iov->m64_single_mode) {\n-\t\tfor (i = 0; i < num_vfs; i++) {\n-\t\t\tif (iov->pe_num_map[i] == IODA_INVALID_PE)\n-\t\t\t\tcontinue;\n-\n-\t\t\tpe = &phb->ioda.pe_array[iov->pe_num_map[i]];\n-\t\t\tpnv_ioda_free_pe(pe);\n-\t\t}\n-\t} else\n-\t\tbitmap_clear(phb->ioda.pe_alloc, *iov->pe_num_map, num_vfs);\n+shift_failed:\n+\tpnv_pci_vf_release_m64(pdev, num_vfs);\n \n-\t/* Releasing pe_num_map */\n-\tkfree(iov->pe_num_map);\n+m64_failed:\n+\tfor (i = 0; i < num_vfs; i++)\n+\t\tpnv_ioda_free_pe(&iov->vf_pe_arr[i]);\n \n \treturn ret;\n }\ndiff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h\nindex b4c9bdba7217..13555bc549f4 100644\n--- a/arch/powerpc/platforms/powernv/pci.h\n+++ b/arch/powerpc/platforms/powernv/pci.h\n@@ -238,7 +238,9 @@ struct pnv_iov_data {\n \n \t/* number of VFs enabled */\n \tu16 num_vfs;\n-\tunsigned int *pe_num_map;\t/* PE# for the first VF PE or array */\n+\n+\t/* pointer to the array of VF PEs. num_vfs long*/\n+\tstruct pnv_ioda_pe *vf_pe_arr;\n \n \t/* Did we map the VF BARs with single-PE IODA BARs? */\n \tbool m64_single_mode;\n", "prefixes": [ "11/15" ] }