Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1326507/?format=api
{ "id": 1326507, "url": "http://patchwork.ozlabs.org/api/patches/1326507/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200710052340.737567-10-oohall@gmail.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20200710052340.737567-10-oohall@gmail.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20200710052340.737567-10-oohall@gmail.com/", "date": "2020-07-10T05:23:34", "name": "[09/15] powerpc/powernv/sriov: Factor out M64 BAR setup", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "bbccb484aa5c94b0760674e3d68c5282e726602e", "submitter": { "id": 68108, "url": "http://patchwork.ozlabs.org/api/people/68108/?format=api", "name": "Oliver O'Halloran", "email": "oohall@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200710052340.737567-10-oohall@gmail.com/mbox/", "series": [ { "id": 188782, "url": "http://patchwork.ozlabs.org/api/series/188782/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=188782", "date": "2020-07-10T05:23:26", "name": "[01/15] powernv/pci: Add pci_bus_to_pnvhb() helper", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/188782/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1326507/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1326507/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4B32CR5zRTz9s1x\n\tfor <patchwork-incoming@ozlabs.org>; Fri, 10 Jul 2020 15:48:35 +1000 (AEST)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4B32CR5BLXzDqDQ\n\tfor <patchwork-incoming@ozlabs.org>; Fri, 10 Jul 2020 15:48:35 +1000 (AEST)", "from mail-wm1-x341.google.com (mail-wm1-x341.google.com\n [IPv6:2a00:1450:4864:20::341])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by lists.ozlabs.org (Postfix) with ESMTPS id 4B31gS0pYmzDrHY\n for <linuxppc-dev@lists.ozlabs.org>; Fri, 10 Jul 2020 15:24:20 +1000 (AEST)", "by mail-wm1-x341.google.com with SMTP id 17so4391380wmo.1\n for <linuxppc-dev@lists.ozlabs.org>; Thu, 09 Jul 2020 22:24:19 -0700 (PDT)", "from 192-168-1-18.tpgi.com.au ([220.240.245.68])\n by smtp.gmail.com with ESMTPSA id 92sm9090941wrr.96.2020.07.09.22.24.14\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 09 Jul 2020 22:24:16 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20161025 header.b=PYWE5N61;\n\tdkim-atps=neutral", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n smtp.mailfrom=gmail.com (client-ip=2a00:1450:4864:20::341;\n helo=mail-wm1-x341.google.com; envelope-from=oohall@gmail.com;\n receiver=<UNKNOWN>)", "lists.ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "lists.ozlabs.org; dkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20161025 header.b=PYWE5N61; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=um5RPZtI5ikMHm5O4kgSxfjKpNY5pRZlVyV91IeyDE8=;\n b=PYWE5N61LwAHEpwyfbeGO7JeXsUhIWJ9u/GTFbtJneN5M0svfN1a+pA+Cq+hEJuwWc\n T7CHNf45l61KTJQUIDwVsKQaXRKWikLJl0DFcVzjcK0jyUHCxyRCDUB7aDjq7wqDYCkx\n 8widfTFOjt35scQTjNeSY/s9VzE5Nzim6I0QKbiV4O0yAr2v26MrOuzHo7K93kAkpObH\n 4qwlA1ooSk9wo6xmCiHaiU5/AEVxqgJV/nP1zV97oR8WEGSUg4sI0dghr8jlfg3R+fHL\n 55fJcrAWhCFkWlvI1yoFkqkgMlHqi2qTslkjaB73WGtvc9jTkYSlWpKssbukTLqdUVjB\n 4EUg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=um5RPZtI5ikMHm5O4kgSxfjKpNY5pRZlVyV91IeyDE8=;\n b=ubPoCklCha911LfGVD53+mXdoegIASq4dLkLL4nJa9mqiRrZ2oggNj506QhLur0BBC\n FneB6uPAA5+P1Vg/iNxjNqAPr7TL7r9GPB8EHzqmLvTBhbQvbnjcEJWOOFPEkCxiN73m\n ECbX7AzBVLWI6MVjSrPSEchVzE6OMJNGijn2qA14fHynG0UNEFVchyCBy7gSPXUvVe2Y\n 7ceERTt3BtjE12+PzrJZlQ1AhFICDMd+b6/s6F81RRc6ebTjMkJHwnv+7BG6+RG4Q2Dp\n EKgt/DpKNLiAX46GOvBdhbZ5F0ZrxOf+juNZAUVj96R3dejtKYxbcqDbowtMlU739UgZ\n i7Mw==", "X-Gm-Message-State": "AOAM530TrmNUBan9W6tizHw6Ofqz6mNU1JLRtXU7JmPXYvwTML19nyUH\n wlilwhbcgE0zp8xik/eeswdrO1lmZGI=", "X-Google-Smtp-Source": "\n ABdhPJzrhcgv3L2aYTbKWZdNm3RCsaZBkYN8+Z1oMHns5JQdJCpA5XUZa2HeHoKk8SuzbCwofh484w==", "X-Received": "by 2002:a1c:4143:: with SMTP id o64mr3296712wma.11.1594358656872;\n Thu, 09 Jul 2020 22:24:16 -0700 (PDT)", "From": "Oliver O'Halloran <oohall@gmail.com>", "To": "linuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH 09/15] powerpc/powernv/sriov: Factor out M64 BAR setup", "Date": "Fri, 10 Jul 2020 15:23:34 +1000", "Message-Id": "<20200710052340.737567-10-oohall@gmail.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20200710052340.737567-1-oohall@gmail.com>", "References": "<20200710052340.737567-1-oohall@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List <linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Oliver O'Halloran <oohall@gmail.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n <linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "The sequence required to use the single PE BAR mode is kinda janky and\nrequires a little explanation. The API was designed with P7-IOC style\nwindows where the setup process is something like:\n\n1. Configure the window start / end address\n2. Enable the window\n3. Map the segments of each window to the PE\n\nFor Single PE BARs the process is:\n\n1. Set the PE for segment zero on a disabled window\n2. Set the range\n3. Enable the window\n\nMove the OPAL calls into their own helper functions where the quirks can be\ncontained.\n\nSigned-off-by: Oliver O'Halloran <oohall@gmail.com>\n---\n arch/powerpc/platforms/powernv/pci-sriov.c | 132 ++++++++++++++++-----\n 1 file changed, 103 insertions(+), 29 deletions(-)", "diff": "diff --git a/arch/powerpc/platforms/powernv/pci-sriov.c b/arch/powerpc/platforms/powernv/pci-sriov.c\nindex e4c65cb49757..d53a85ccb538 100644\n--- a/arch/powerpc/platforms/powernv/pci-sriov.c\n+++ b/arch/powerpc/platforms/powernv/pci-sriov.c\n@@ -320,6 +320,102 @@ static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)\n \treturn 0;\n }\n \n+\n+/*\n+ * PHB3 and beyond support \"accordion\" windows. The window's address range\n+ * is subdivided into phb->ioda.total_pe_num segments and there's a 1-1\n+ * mapping between PEs and segments.\n+ *\n+ * They're called that because as the window size changes the segment sizes\n+ * change with it. Sort of like an accordion, sort of.\n+ */\n+static int64_t pnv_ioda_map_m64_accordion(struct pnv_phb *phb,\n+\t\t\t\t\t int window_id,\n+\t\t\t\t\t resource_size_t start,\n+\t\t\t\t\t resource_size_t size)\n+{\n+\tint64_t rc;\n+\n+\trc = opal_pci_set_phb_mem_window(phb->opal_id,\n+\t\t\t\t\t OPAL_M64_WINDOW_TYPE,\n+\t\t\t\t\t window_id,\n+\t\t\t\t\t start,\n+\t\t\t\t\t 0, /* unused */\n+\t\t\t\t\t size);\n+\tif (rc)\n+\t\tgoto out;\n+\n+\trc = opal_pci_phb_mmio_enable(phb->opal_id,\n+\t\t\t\t OPAL_M64_WINDOW_TYPE,\n+\t\t\t\t window_id,\n+\t\t\t\t OPAL_ENABLE_M64_SPLIT);\n+out:\n+\tif (rc)\n+\t\tpr_err(\"Failed to map M64 window #%d: %lld\\n\", window_id, rc);\n+\n+\treturn rc;\n+}\n+\n+static int64_t pnv_ioda_map_m64_single(struct pnv_phb *phb,\n+\t\t\t\t int pe_num,\n+\t\t\t\t int window_id,\n+\t\t\t\t resource_size_t start,\n+\t\t\t\t resource_size_t size)\n+{\n+\tint64_t rc;\n+\n+\t/*\n+\t * The API for setting up m64 mmio windows seems to have been designed\n+\t * with P7-IOC in mind. For that chip each M64 BAR (window) had a fixed\n+\t * split of 8 equally sized segments each of which could individually\n+\t * assigned to a PE.\n+\t *\n+\t * The problem with this is that the API doesn't have any way to\n+\t * communicate the number of segments we want on a BAR. This wasn't\n+\t * a problem for p7-ioc since you didn't have a choice, but the\n+\t * single PE windows added in PHB3 don't map cleanly to this API.\n+\t *\n+\t * As a result we've got this slightly awkward process where we\n+\t * call opal_pci_map_pe_mmio_window() to put the single in single\n+\t * PE mode, and set the PE for the window before setting the address\n+\t * bounds. We need to do it this way because the single PE windows\n+\t * for PHB3 have different alignment requirements on PHB3.\n+\t */\n+\trc = opal_pci_map_pe_mmio_window(phb->opal_id,\n+\t\t\t\t\t pe_num,\n+\t\t\t\t\t OPAL_M64_WINDOW_TYPE,\n+\t\t\t\t\t window_id,\n+\t\t\t\t\t 0);\n+\tif (rc)\n+\t\tgoto out;\n+\n+\t/*\n+\t * NB: In single PE mode the window needs to be aligned to 32MB\n+\t */\n+\trc = opal_pci_set_phb_mem_window(phb->opal_id,\n+\t\t\t\t\t OPAL_M64_WINDOW_TYPE,\n+\t\t\t\t\t window_id,\n+\t\t\t\t\t start,\n+\t\t\t\t\t 0, /* ignored by FW, m64 is 1-1 */\n+\t\t\t\t\t size);\n+\tif (rc)\n+\t\tgoto out;\n+\n+\t/*\n+\t * Now actually enable it. We specified the BAR should be in \"non-split\"\n+\t * mode so FW will validate that the BAR is in single PE mode.\n+\t */\n+\trc = opal_pci_phb_mmio_enable(phb->opal_id,\n+\t\t\t\t OPAL_M64_WINDOW_TYPE,\n+\t\t\t\t window_id,\n+\t\t\t\t OPAL_ENABLE_M64_NON_SPLIT);\n+out:\n+\tif (rc)\n+\t\tpr_err(\"Error mapping single PE BAR\\n\");\n+\n+\treturn rc;\n+}\n+\n static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)\n {\n \tstruct pnv_iov_data *iov;\n@@ -330,7 +426,6 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)\n \tint64_t rc;\n \tint total_vfs;\n \tresource_size_t size, start;\n-\tint pe_num;\n \tint m64_bars;\n \n \tphb = pci_bus_to_pnvhb(pdev->bus);\n@@ -359,49 +454,28 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)\n \t\t\t} while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));\n \t\t\tset_bit(win, iov->used_m64_bar_mask);\n \n+\n \t\t\tif (iov->m64_single_mode) {\n \t\t\t\tsize = pci_iov_resource_size(pdev,\n \t\t\t\t\t\t\tPCI_IOV_RESOURCES + i);\n \t\t\t\tstart = res->start + size * j;\n+\t\t\t\trc = pnv_ioda_map_m64_single(phb, win,\n+\t\t\t\t\t\t\t iov->pe_num_map[j],\n+\t\t\t\t\t\t\t start,\n+\t\t\t\t\t\t\t size);\n \t\t\t} else {\n \t\t\t\tsize = resource_size(res);\n \t\t\t\tstart = res->start;\n-\t\t\t}\n \n-\t\t\t/* Map the M64 here */\n-\t\t\tif (iov->m64_single_mode) {\n-\t\t\t\tpe_num = iov->pe_num_map[j];\n-\t\t\t\trc = opal_pci_map_pe_mmio_window(phb->opal_id,\n-\t\t\t\t\t\tpe_num, OPAL_M64_WINDOW_TYPE,\n-\t\t\t\t\t\twin, 0);\n+\t\t\t\trc = pnv_ioda_map_m64_accordion(phb, win, start,\n+\t\t\t\t\t\t\t\tsize);\n \t\t\t}\n \n-\t\t\trc = opal_pci_set_phb_mem_window(phb->opal_id,\n-\t\t\t\t\t\t OPAL_M64_WINDOW_TYPE,\n-\t\t\t\t\t\t win,\n-\t\t\t\t\t\t start,\n-\t\t\t\t\t\t 0, /* unused */\n-\t\t\t\t\t\t size);\n-\n-\n \t\t\tif (rc != OPAL_SUCCESS) {\n \t\t\t\tdev_err(&pdev->dev, \"Failed to map M64 window #%d: %lld\\n\",\n \t\t\t\t\twin, rc);\n \t\t\t\tgoto m64_failed;\n \t\t\t}\n-\n-\t\t\tif (iov->m64_single_mode)\n-\t\t\t\trc = opal_pci_phb_mmio_enable(phb->opal_id,\n-\t\t\t\t OPAL_M64_WINDOW_TYPE, win, 2);\n-\t\t\telse\n-\t\t\t\trc = opal_pci_phb_mmio_enable(phb->opal_id,\n-\t\t\t\t OPAL_M64_WINDOW_TYPE, win, 1);\n-\n-\t\t\tif (rc != OPAL_SUCCESS) {\n-\t\t\t\tdev_err(&pdev->dev, \"Failed to enable M64 window #%d: %llx\\n\",\n-\t\t\t\t\twin, rc);\n-\t\t\t\tgoto m64_failed;\n-\t\t\t}\n \t\t}\n \t}\n \treturn 0;\n", "prefixes": [ "09/15" ] }