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GET /api/patches/1326501/?format=api
{ "id": 1326501, "url": "http://patchwork.ozlabs.org/api/patches/1326501/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200710052340.737567-4-oohall@gmail.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20200710052340.737567-4-oohall@gmail.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20200710052340.737567-4-oohall@gmail.com/", "date": "2020-07-10T05:23:28", "name": "[03/15] powerpc/powernv/pci: Add explicit tracking of the DMA setup state", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "c3d2f6da8c534d8573d908a70cc424c327cebe45", "submitter": { "id": 68108, "url": "http://patchwork.ozlabs.org/api/people/68108/?format=api", "name": "Oliver O'Halloran", "email": "oohall@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20200710052340.737567-4-oohall@gmail.com/mbox/", "series": [ { "id": 188782, "url": "http://patchwork.ozlabs.org/api/series/188782/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=188782", "date": "2020-07-10T05:23:26", "name": "[01/15] powernv/pci: Add pci_bus_to_pnvhb() helper", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/188782/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1326501/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1326501/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4B31yX2gGmz9s1x\n\tfor <patchwork-incoming@ozlabs.org>; Fri, 10 Jul 2020 15:37:24 +1000 (AEST)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4B31yW6RYPzDqS2\n\tfor <patchwork-incoming@ozlabs.org>; Fri, 10 Jul 2020 15:37:23 +1000 (AEST)", "from mail-wm1-x343.google.com (mail-wm1-x343.google.com\n [IPv6:2a00:1450:4864:20::343])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by lists.ozlabs.org (Postfix) with ESMTPS id 4B31gB0cndzDrH8\n for <linuxppc-dev@lists.ozlabs.org>; Fri, 10 Jul 2020 15:24:05 +1000 (AEST)", "by mail-wm1-x343.google.com with SMTP id l17so4560573wmj.0\n for <linuxppc-dev@lists.ozlabs.org>; Thu, 09 Jul 2020 22:24:05 -0700 (PDT)", "from 192-168-1-18.tpgi.com.au ([220.240.245.68])\n by smtp.gmail.com with ESMTPSA id 92sm9090941wrr.96.2020.07.09.22.23.59\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 09 Jul 2020 22:24:01 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n dmarc=fail (p=none dis=none) header.from=gmail.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20161025 header.b=X5AF++IA;\n\tdkim-atps=neutral", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n smtp.mailfrom=gmail.com (client-ip=2a00:1450:4864:20::343;\n helo=mail-wm1-x343.google.com; envelope-from=oohall@gmail.com;\n receiver=<UNKNOWN>)", "lists.ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "lists.ozlabs.org; dkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20161025 header.b=X5AF++IA; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=UxmXR/WLSBm2vMKnRUFb+GXjgplAREAPNZTS1mltnW0=;\n b=X5AF++IADmf/FVLgRdEYN5Kv0EobeAGKMvu6mYW2btCgM8Q2tqPGJLsRRUVCp/9bmo\n s277tdv5k9s4rrlfkfLWDi7pnnfImquc8EmWJ1fhAlGR813MfNIY0Q57Nbt12rgKPdz6\n kF/VEU7Aal6ZDoWUUfzMoYhKeTELwIfXi2tSWSmFZTo/UHblAUzYubdfUEfnGf1PgkGt\n waM4vo+GIIkmjevpVt19jLDyMeShww/QBLDqNn9f6HYT7v8aBBN3K2YpV5VSEgsBCRpX\n IZy9Vpi9cVG44NK1ADYozr/RoehvYdd3oxaHkrK7WRBnb19gJ5yEMrxcUPk38kdaChMe\n fx1g==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=UxmXR/WLSBm2vMKnRUFb+GXjgplAREAPNZTS1mltnW0=;\n b=BQ6DgXMJoh+AEFqqnm+b2vlDDHiDFzPHCvbtpwDBXaEUO+bAEGEuN44R6LSXSEW5fu\n I6Q7E4karlAnASKgc055E+EdtSunaW21cHu3HDpiknW+jpOa2X+JcDM+Tads+Bw6RLEf\n aGimqvMAyhHbSVEb2ZQLIku6szccjaoDKB/I9CeO5dEY9w5QdoNS5caVarQ8UjMO/7E4\n d4DiJWcMvFVgFyZArbPeFhIoolMOQSpyXvechlmJHrcXeCCvZtLUHtMMzmK8eTcABzsM\n 0JAYrSAAL3eDF0oLRz0hdtmOYvFfhCUjUc8yLgcTlaHxm7BAhqkGWzz8OWZ7uO4j6yWu\n 3Pyw==", "X-Gm-Message-State": "AOAM532OAv5716awi3sUMTTUSUBsRDcYEPBwpeXjF14u4EfVCTFVrh8B\n 24CmxXWVvc0LJyM0wu/HoPBSO79Ttc8=", "X-Google-Smtp-Source": "\n ABdhPJybmnVGaxVmuSKYGO5nN1yTJXSRqHXlGijH1z59NyaCp1poypZhwInMooFf1LtCegwXcxINag==", "X-Received": "by 2002:a05:600c:2187:: with SMTP id\n e7mr3246288wme.171.1594358641939;\n Thu, 09 Jul 2020 22:24:01 -0700 (PDT)", "From": "Oliver O'Halloran <oohall@gmail.com>", "To": "linuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH 03/15] powerpc/powernv/pci: Add explicit tracking of the DMA\n setup state", "Date": "Fri, 10 Jul 2020 15:23:28 +1000", "Message-Id": "<20200710052340.737567-4-oohall@gmail.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20200710052340.737567-1-oohall@gmail.com>", "References": "<20200710052340.737567-1-oohall@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List <linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Alexey Kardashevskiy <aik@ozlabs.ru>, Oliver O'Halloran <oohall@gmail.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n <linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "There's an optimisation in the PE setup which skips performing DMA\nsetup for a PE if we only have bridges in a PE. The assumption being\nthat only \"real\" devices will DMA to system memory, which is probably\nfair. However, if we start off with only bridge devices in a PE then\nadd a non-bridge device the new device won't be able to use DMA because\nwe never configured it.\n\nFix this (admittedly pretty weird) edge case by tracking whether we've done\nthe DMA setup for the PE or not. If a non-bridge device is added to the PE\n(via rescan or hotplug, or whatever) we can set up DMA on demand.\n\nThis also means the only remaining user of the old \"DMA Weight\" code is\nthe IODA1 DMA setup code that it was originally added for, which is good.\n\nCc: Alexey Kardashevskiy <aik@ozlabs.ru>\nSigned-off-by: Oliver O'Halloran <oohall@gmail.com>\n---\nAlexey, do we need to have the IOMMU API stuff set/clear this flag?\n---\n arch/powerpc/platforms/powernv/pci-ioda.c | 48 ++++++++++++++---------\n arch/powerpc/platforms/powernv/pci.h | 7 ++++\n 2 files changed, 36 insertions(+), 19 deletions(-)", "diff": "diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c\nindex bfb40607aa0e..bb9c1cc60c33 100644\n--- a/arch/powerpc/platforms/powernv/pci-ioda.c\n+++ b/arch/powerpc/platforms/powernv/pci-ioda.c\n@@ -141,6 +141,7 @@ static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)\n \n \tphb->ioda.pe_array[pe_no].phb = phb;\n \tphb->ioda.pe_array[pe_no].pe_number = pe_no;\n+\tphb->ioda.pe_array[pe_no].dma_setup_done = false;\n \n \t/*\n \t * Clear the PE frozen state as it might be put into frozen state\n@@ -1685,6 +1686,12 @@ static int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)\n }\n #endif /* CONFIG_PCI_IOV */\n \n+static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,\n+\t\t\t\t struct pnv_ioda_pe *pe);\n+\n+static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,\n+\t\t\t\t struct pnv_ioda_pe *pe);\n+\n static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev)\n {\n \tstruct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);\n@@ -1713,6 +1720,24 @@ static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev)\n \t\tpci_info(pdev, \"Added to existing PE#%x\\n\", pe->pe_number);\n \t}\n \n+\t/*\n+\t * We assume that bridges *probably* don't need to do any DMA so we can\n+\t * skip allocating a TCE table, etc unless we get a non-bridge device.\n+\t */\n+\tif (!pe->dma_setup_done && !pci_is_bridge(pdev)) {\n+\t\tswitch (phb->type) {\n+\t\tcase PNV_PHB_IODA1:\n+\t\t\tpnv_pci_ioda1_setup_dma_pe(phb, pe);\n+\t\t\tbreak;\n+\t\tcase PNV_PHB_IODA2:\n+\t\t\tpnv_pci_ioda2_setup_dma_pe(phb, pe);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tpr_warn(\"%s: No DMA for PHB#%x (type %d)\\n\",\n+\t\t\t\t__func__, phb->hose->global_number, phb->type);\n+\t\t}\n+\t}\n+\n \tif (pdn)\n \t\tpdn->pe_number = pe->pe_number;\n \tpe->device_count++;\n@@ -2222,6 +2247,7 @@ static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,\n \tpe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;\n \tiommu_init_table(tbl, phb->hose->node, 0, 0);\n \n+\tpe->dma_setup_done = true;\n \treturn;\n fail:\n \t/* XXX Failure: Try to fallback to 64-bit only ? */\n@@ -2536,9 +2562,6 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,\n {\n \tint64_t rc;\n \n-\tif (!pnv_pci_ioda_pe_dma_weight(pe))\n-\t\treturn;\n-\n \t/* TVE #1 is selected by PCI address bit 59 */\n \tpe->tce_bypass_base = 1ull << 59;\n \n@@ -2563,6 +2586,7 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,\n \tiommu_register_group(&pe->table_group, phb->hose->global_number,\n \t\t\t pe->pe_number);\n #endif\n+\tpe->dma_setup_done = true;\n }\n \n int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)\n@@ -3136,7 +3160,6 @@ static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,\n \n static void pnv_pci_configure_bus(struct pci_bus *bus)\n {\n-\tstruct pnv_phb *phb = pci_bus_to_pnvhb(bus);\n \tstruct pci_dev *bridge = bus->self;\n \tstruct pnv_ioda_pe *pe;\n \tbool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);\n@@ -3160,17 +3183,6 @@ static void pnv_pci_configure_bus(struct pci_bus *bus)\n \t\treturn;\n \n \tpnv_ioda_setup_pe_seg(pe);\n-\tswitch (phb->type) {\n-\tcase PNV_PHB_IODA1:\n-\t\tpnv_pci_ioda1_setup_dma_pe(phb, pe);\n-\t\tbreak;\n-\tcase PNV_PHB_IODA2:\n-\t\tpnv_pci_ioda2_setup_dma_pe(phb, pe);\n-\t\tbreak;\n-\tdefault:\n-\t\tpr_warn(\"%s: No DMA for PHB#%x (type %d)\\n\",\n-\t\t\t__func__, phb->hose->global_number, phb->type);\n-\t}\n }\n \n static resource_size_t pnv_pci_default_alignment(void)\n@@ -3289,11 +3301,10 @@ static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,\n \n static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)\n {\n-\tunsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);\n \tstruct iommu_table *tbl = pe->table_group.tables[0];\n \tint64_t rc;\n \n-\tif (!weight)\n+\tif (!pe->dma_setup_done)\n \t\treturn;\n \n \trc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);\n@@ -3313,10 +3324,9 @@ static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)\n static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)\n {\n \tstruct iommu_table *tbl = pe->table_group.tables[0];\n-\tunsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);\n \tint64_t rc;\n \n-\tif (!weight)\n+\tif (pe->dma_setup_done)\n \t\treturn;\n \n \trc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);\ndiff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h\nindex 0727dec9a0d1..6aa6aefb637d 100644\n--- a/arch/powerpc/platforms/powernv/pci.h\n+++ b/arch/powerpc/platforms/powernv/pci.h\n@@ -87,6 +87,13 @@ struct pnv_ioda_pe {\n \tbool\t\t\ttce_bypass_enabled;\n \tuint64_t\t\ttce_bypass_base;\n \n+\t/*\n+\t * Used to track whether we've done DMA setup for this PE or not. We\n+\t * want to defer allocating TCE tables, etc until we've added a\n+\t * non-bridge device to the PE.\n+\t */\n+\tbool\t\t\tdma_setup_done;\n+\n \t/* MSIs. MVE index is identical for for 32 and 64 bit MSI\n \t * and -1 if not supported. (It's actually identical to the\n \t * PE number)\n", "prefixes": [ "03/15" ] }