Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1302234/?format=api
{ "id": 1302234, "url": "http://patchwork.ozlabs.org/api/patches/1302234/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200602075047.19085-1-sasha.neftin@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20200602075047.19085-1-sasha.neftin@intel.com>", "list_archive_url": null, "date": "2020-06-02T07:50:47", "name": "[v1,1/1] igc: Add initial LTR support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "f78db6e211785159af78f1e87d8c02e72cfb316d", "submitter": { "id": 69860, "url": "http://patchwork.ozlabs.org/api/people/69860/?format=api", "name": "Sasha Neftin", "email": "sasha.neftin@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200602075047.19085-1-sasha.neftin@intel.com/mbox/", "series": [ { "id": 180753, "url": "http://patchwork.ozlabs.org/api/series/180753/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=180753", "date": "2020-06-02T07:50:47", "name": "[v1,1/1] igc: Add initial LTR support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/180753/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1302234/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1302234/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.133; helo=hemlock.osuosl.org;\n envelope-from=intel-wired-lan-bounces@osuosl.org; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 49bkk71vXcz9sSg\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 2 Jun 2020 17:50:54 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 5EEFE8818B;\n\tTue, 2 Jun 2020 07:50:53 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id xPzQb8-9SP0N; Tue, 2 Jun 2020 07:50:52 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 9F90186D88;\n\tTue, 2 Jun 2020 07:50:52 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n by ash.osuosl.org (Postfix) with ESMTP id 23F3D1BF31B\n for <intel-wired-lan@lists.osuosl.org>; Tue, 2 Jun 2020 07:50:52 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n by hemlock.osuosl.org (Postfix) with ESMTP id 1F79386D88\n for <intel-wired-lan@lists.osuosl.org>; Tue, 2 Jun 2020 07:50:52 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n with ESMTP id N8TqzkgVSFw1 for <intel-wired-lan@lists.osuosl.org>;\n Tue, 2 Jun 2020 07:50:49 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by hemlock.osuosl.org (Postfix) with ESMTPS id 3F709865CD\n for <intel-wired-lan@lists.osuosl.org>; Tue, 2 Jun 2020 07:50:49 +0000 (UTC)", "from orsmga004.jf.intel.com ([10.7.209.38])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Jun 2020 00:50:48 -0700", "from ccdlinuxdev09.iil.intel.com ([143.185.160.241])\n by orsmga004.jf.intel.com with ESMTP; 02 Jun 2020 00:50:47 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "IronPort-SDR": [ "\n xpPcATWHrrVOY026+76gJ6fUnJT3lTdL8Xv8bmfuMk5b/yV01slY+fMaALbHkk6gdFdInb54PY\n 7l+KMdL7NVUw==", "\n k3CPlvhjBtqTXhUWlNfBrB0RxjpJql4Vt4dVFPE1HpfafBIvsiFvnWyPVvAhWH+KWEO3js3Bz5\n d4fMFfI7OfVA==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.73,463,1583222400\"; d=\"scan'208\";a=\"416096703\"", "From": "Sasha Neftin <sasha.neftin@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Tue, 2 Jun 2020 10:50:47 +0300", "Message-Id": "<20200602075047.19085-1-sasha.neftin@intel.com>", "X-Mailer": "git-send-email 2.11.0", "Subject": "[Intel-wired-lan] [PATCH v1 1/1] igc: Add initial LTR support", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "The LTR message on the PCIe inform the requested latency\non which the PCIe must become active to the downstream\nPCIe port of the system.\nThis patch provide reccommended LTR parameters by i225\nspecification.\n\nSigned-off-by: Sasha Neftin <sasha.neftin@intel.com>\n---\n drivers/net/ethernet/intel/igc/igc_defines.h | 27 ++++++++\n drivers/net/ethernet/intel/igc/igc_i225.c | 100 +++++++++++++++++++++++++++\n drivers/net/ethernet/intel/igc/igc_i225.h | 1 +\n drivers/net/ethernet/intel/igc/igc_mac.c | 5 ++\n drivers/net/ethernet/intel/igc/igc_regs.h | 6 ++\n 5 files changed, 139 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h\nindex a7baadc49d84..81df6de2b206 100644\n--- a/drivers/net/ethernet/intel/igc/igc_defines.h\n+++ b/drivers/net/ethernet/intel/igc/igc_defines.h\n@@ -522,4 +522,31 @@\n #define IGC_EEER_LPI_FC\t\t\t0x00040000 /* EEER Ena on Flow Cntrl */\n #define IGC_EEE_SU_LPI_CLK_STP\t\t0x00800000 /* EEE LPI Clock Stop */\n \n+/* LTR defines */\n+#define IGC_LTRC_EEEMS_EN\t\t0x00000020 /* Enable EEE LTR max send */\n+#define IGC_RXPBS_SIZE_I225_MASK\t0x0000003F /* Rx packet buffer size */\n+#define IGC_TW_SYSTEM_1000_MASK\t\t0x000000FF\n+/* Minimum time for 100BASE-T where no data will be transmit following move out\n+ * of EEE LPI Tx state\n+ */\n+#define IGC_TW_SYSTEM_100_MASK\t\t0x0000FF00\n+#define IGC_TW_SYSTEM_100_SHIFT\t\t8\n+#define IGC_DMACR_DMAC_EN\t\t0x80000000 /* Enable DMA Coalescing */\n+#define IGC_DMACR_DMACTHR_MASK\t\t0x00FF0000\n+#define IGC_DMACR_DMACTHR_SHIFT\t\t16\n+/* Reg val to set scale to 1024 nsec */\n+#define IGC_LTRMINV_SCALE_1024\t\t2\n+/* Reg val to set scale to 32768 nsec */\n+#define IGC_LTRMINV_SCALE_32768\t\t3\n+/* Reg val to set scale to 1024 nsec */\n+#define IGC_LTRMAXV_SCALE_1024\t\t2\n+/* Reg val to set scale to 32768 nsec */\n+#define IGC_LTRMAXV_SCALE_32768\t\t3\n+#define IGC_LTRMINV_LTRV_MASK\t\t0x000003FF /* LTR minimum value */\n+#define IGC_LTRMAXV_LTRV_MASK\t\t0x000003FF /* LTR maximum value */\n+#define IGC_LTRMINV_LSNP_REQ\t\t0x00008000 /* LTR Snoop Requirement */\n+#define IGC_LTRMINV_SCALE_SHIFT\t\t10\n+#define IGC_LTRMAXV_LSNP_REQ\t\t0x00008000 /* LTR Snoop Requirement */\n+#define IGC_LTRMAXV_SCALE_SHIFT\t\t10\n+\n #endif /* _IGC_DEFINES_H_ */\ndiff --git a/drivers/net/ethernet/intel/igc/igc_i225.c b/drivers/net/ethernet/intel/igc/igc_i225.c\nindex c67bfbe92074..aed1be83c252 100644\n--- a/drivers/net/ethernet/intel/igc/igc_i225.c\n+++ b/drivers/net/ethernet/intel/igc/igc_i225.c\n@@ -544,3 +544,103 @@ s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,\n \n \treturn IGC_SUCCESS;\n }\n+\n+/* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds.\n+ * @hw: pointer to the HW structure\n+ * @link: bool indicating link status\n+ *\n+ * Set the LTR thresholds based on the link speed (Mbps), EEE, and DMAC\n+ * settings, otherwise specify that there is no LTR requirement.\n+ */\n+s32 igc_set_ltr_i225(struct igc_hw *hw, bool link)\n+{\n+\tu16 speed, duplex;\n+\tu32 tw_system, ltrc, ltrv, ltr_min, ltr_max, scale_min, scale_max;\n+\ts32 size;\n+\n+\t/* If we do not have link, LTR thresholds are zero. */\n+\tif (link) {\n+\t\thw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);\n+\n+\t\t/* Check if using copper interface with EEE enabled or if the\n+\t\t * link speed is 10 Mbps.\n+\t\t */\n+\t\tif (hw->dev_spec._base.eee_enable &&\n+\t\t speed != SPEED_10) {\n+\t\t\t/* EEE enabled, so send LTRMAX threshold. */\n+\t\t\tltrc = rd32(IGC_LTRC) |\n+\t\t\t\tIGC_LTRC_EEEMS_EN;\n+\t\t\twr32(IGC_LTRC, ltrc);\n+\n+\t\t\t/* Calculate tw_system (nsec). */\n+\t\t\tif (speed == SPEED_100) {\n+\t\t\t\ttw_system = ((rd32(IGC_EEE_SU) &\n+\t\t\t\t\t IGC_TW_SYSTEM_100_MASK) >>\n+\t\t\t\t\t IGC_TW_SYSTEM_100_SHIFT) * 500;\n+\t\t\t} else {\n+\t\t\t\ttw_system = (rd32(IGC_EEE_SU) &\n+\t\t\t\t\t IGC_TW_SYSTEM_1000_MASK) * 500;\n+\t\t\t\t}\n+\t\t} else {\n+\t\t\ttw_system = 0;\n+\t\t\t}\n+\n+\t\t/* Get the Rx packet buffer size. */\n+\t\tsize = rd32(IGC_RXPBS) &\n+\t\t\tIGC_RXPBS_SIZE_I225_MASK;\n+\n+\t\t/* Calculations vary based on DMAC settings. */\n+\t\tif (rd32(IGC_DMACR) & IGC_DMACR_DMAC_EN) {\n+\t\t\tsize -= (rd32(IGC_DMACR) &\n+\t\t\t\t IGC_DMACR_DMACTHR_MASK) >>\n+\t\t\t\t IGC_DMACR_DMACTHR_SHIFT;\n+\t\t\t/* Convert size to bits. */\n+\t\t\tsize *= 1024 * 8;\n+\t\t} else {\n+\t\t\t/* Convert size to bytes, subtract the MTU, and then\n+\t\t\t * convert the size to bits.\n+\t\t\t */\n+\t\t\tsize *= 1024;\n+\t\t\tsize *= 8;\n+\t\t}\n+\n+\t\tif (size < 0) {\n+\t\t\thw_dbg(\"Invalid effective Rx buffer size %d\\n\",\n+\t\t\t size);\n+\t\t\treturn -IGC_ERR_CONFIG;\n+\t\t}\n+\n+\t\t/* Calculate the thresholds. Since speed is in Mbps, simplify\n+\t\t * the calculation by multiplying size/speed by 1000 for result\n+\t\t * to be in nsec before dividing by the scale in nsec. Set the\n+\t\t * scale such that the LTR threshold fits in the register.\n+\t\t */\n+\t\tltr_min = (1000 * size) / speed;\n+\t\tltr_max = ltr_min + tw_system;\n+\t\tscale_min = (ltr_min / 1024) < 1024 ? IGC_LTRMINV_SCALE_1024 :\n+\t\t\t IGC_LTRMINV_SCALE_32768;\n+\t\tscale_max = (ltr_max / 1024) < 1024 ? IGC_LTRMAXV_SCALE_1024 :\n+\t\t\t IGC_LTRMAXV_SCALE_32768;\n+\t\tltr_min /= scale_min == IGC_LTRMINV_SCALE_1024 ? 1024 : 32768;\n+\t\tltr_min -= 1;\n+\t\tltr_max /= scale_max == IGC_LTRMAXV_SCALE_1024 ? 1024 : 32768;\n+\t\tltr_max -= 1;\n+\n+\t\t/* Only write the LTR thresholds if they differ from before. */\n+\t\tltrv = rd32(IGC_LTRMINV);\n+\t\tif (ltr_min != (ltrv & IGC_LTRMINV_LTRV_MASK)) {\n+\t\t\tltrv = IGC_LTRMINV_LSNP_REQ | ltr_min |\n+\t\t\t (scale_min << IGC_LTRMINV_SCALE_SHIFT);\n+\t\t\twr32(IGC_LTRMINV, ltrv);\n+\t\t}\n+\n+\t\tltrv = rd32(IGC_LTRMAXV);\n+\t\tif (ltr_max != (ltrv & IGC_LTRMAXV_LTRV_MASK)) {\n+\t\t\tltrv = IGC_LTRMAXV_LSNP_REQ | ltr_max |\n+\t\t\t (scale_min << IGC_LTRMAXV_SCALE_SHIFT);\n+\t\t\twr32(IGC_LTRMAXV, ltrv);\n+\t\t}\n+\t}\n+\n+\treturn IGC_SUCCESS;\n+}\ndiff --git a/drivers/net/ethernet/intel/igc/igc_i225.h b/drivers/net/ethernet/intel/igc/igc_i225.h\nindex 04759e076a9e..dae47e4f16b0 100644\n--- a/drivers/net/ethernet/intel/igc/igc_i225.h\n+++ b/drivers/net/ethernet/intel/igc/igc_i225.h\n@@ -11,5 +11,6 @@ s32 igc_init_nvm_params_i225(struct igc_hw *hw);\n bool igc_get_flash_presence_i225(struct igc_hw *hw);\n s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,\n \t\t bool adv100M);\n+s32 igc_set_ltr_i225(struct igc_hw *hw, bool link);\n \n #endif\ndiff --git a/drivers/net/ethernet/intel/igc/igc_mac.c b/drivers/net/ethernet/intel/igc/igc_mac.c\nindex 410aeb01de5c..bc077f230f17 100644\n--- a/drivers/net/ethernet/intel/igc/igc_mac.c\n+++ b/drivers/net/ethernet/intel/igc/igc_mac.c\n@@ -417,6 +417,11 @@ s32 igc_check_for_copper_link(struct igc_hw *hw)\n \t\thw_dbg(\"Error configuring flow control\\n\");\n \n out:\n+\t/* Now that we are aware of our link settings, we can set the LTR\n+\t * thresholds.\n+\t */\n+\tret_val = igc_set_ltr_i225(hw, link);\n+\n \treturn ret_val;\n }\n \ndiff --git a/drivers/net/ethernet/intel/igc/igc_regs.h b/drivers/net/ethernet/intel/igc/igc_regs.h\nindex 75e040a5d46f..97f9b928509f 100644\n--- a/drivers/net/ethernet/intel/igc/igc_regs.h\n+++ b/drivers/net/ethernet/intel/igc/igc_regs.h\n@@ -253,6 +253,12 @@\n #define IGC_IPCNFG\t0x0E38 /* Internal PHY Configuration */\n #define IGC_EEE_SU\t0x0E34 /* EEE Setup */\n \n+/* LTR registers */\n+#define IGC_LTRC\t0x01A0 /* Latency Tolerance Reporting Control */\n+#define IGC_DMACR\t0x02508 /* DMA Coalescing Control Register */\n+#define IGC_LTRMINV\t0x5BB0 /* LTR Minimum Value */\n+#define IGC_LTRMAXV\t0x5BB4 /* LTR Maximum Value */\n+\n /* forward declaration */\n struct igc_hw;\n u32 igc_rd32(struct igc_hw *hw, u32 reg);\n", "prefixes": [ "v1", "1/1" ] }