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GET /api/patches/1291783/?format=api
{ "id": 1291783, "url": "http://patchwork.ozlabs.org/api/patches/1291783/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200516005121.4963-1-anthony.l.nguyen@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20200516005121.4963-1-anthony.l.nguyen@intel.com>", "list_archive_url": null, "date": "2020-05-16T00:51:07", "name": "[S45,01/15] ice: Refactor ice_ena_vf_mappings to split MSIX and queue mappings", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "0ab28346d08f3ae88353796b967e7c8524d57ca8", "submitter": { "id": 68875, "url": "http://patchwork.ozlabs.org/api/people/68875/?format=api", "name": "Tony Nguyen", "email": "anthony.l.nguyen@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200516005121.4963-1-anthony.l.nguyen@intel.com/mbox/", "series": [ { "id": 177330, "url": "http://patchwork.ozlabs.org/api/series/177330/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=177330", "date": "2020-05-16T00:51:18", "name": "[S45,01/15] ice: Refactor ice_ena_vf_mappings to split MSIX and queue mappings", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/177330/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1291783/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1291783/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n envelope-from=intel-wired-lan-bounces@osuosl.org; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 49P6H8582Hz9sTL\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 16 May 2020 10:54:12 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 1E2C687D69;\n\tSat, 16 May 2020 00:54:11 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id oF8naTiDMvMS; Sat, 16 May 2020 00:54:05 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 4D8FF85735;\n\tSat, 16 May 2020 00:54:05 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n by ash.osuosl.org (Postfix) with ESMTP id 790371BF9C8\n for <intel-wired-lan@lists.osuosl.org>; Sat, 16 May 2020 00:53:59 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n by fraxinus.osuosl.org (Postfix) with ESMTP id 75DCF87F7D\n for <intel-wired-lan@lists.osuosl.org>; Sat, 16 May 2020 00:53:59 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n with ESMTP id lX2NWhZiOzde for <intel-wired-lan@lists.osuosl.org>;\n Sat, 16 May 2020 00:53:58 +0000 (UTC)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by fraxinus.osuosl.org (Postfix) with ESMTPS id 912DB881C1\n for <intel-wired-lan@lists.osuosl.org>; Sat, 16 May 2020 00:53:56 +0000 (UTC)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 May 2020 17:53:54 -0700", "from unknown (HELO localhost.jf.intel.com) ([10.166.241.65])\n by orsmga003.jf.intel.com with ESMTP; 15 May 2020 17:53:54 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "IronPort-SDR": [ "\n yxSXpp8d/RJrdRbHWuhXB5ogOhZYh3MVi1pGhn6zwKSTjjsxQslq4CYlRmuOU2FHS6XG+n+sJ5\n fjdBD2uh5pwQ==", "\n motId3FZA6GbnaAJV+y+LuajmqQ0p/Vb4tb4k/k9CgWN7bIbarwjc+E/wTI/30OmGXcYfhYQC9\n zPMan3gbCQyg==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.73,397,1583222400\"; d=\"scan'208\";a=\"263360537\"", "From": "Tony Nguyen <anthony.l.nguyen@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Fri, 15 May 2020 17:51:07 -0700", "Message-Id": "<20200516005121.4963-1-anthony.l.nguyen@intel.com>", "X-Mailer": "git-send-email 2.20.1", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH S45 01/15] ice: Refactor\n ice_ena_vf_mappings to split MSIX and queue mappings", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Brett Creeley <brett.creeley@intel.com>\n\nCurrently ice_ena_vf_mappings() does all of the VF's MSIX and queue\nmapping in one function. This makes it hard to digest. Fix this by\ncreating a new function for enabling MSIX mappings and one for enabling\nqueue mappings.\n\nAlso, rename some variables in the functions for clarity.\n\nSigned-off-by: Brett Creeley <brett.creeley@intel.com>\n---\n .../net/ethernet/intel/ice/ice_virtchnl_pf.c | 91 ++++++++++++-------\n 1 file changed, 59 insertions(+), 32 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c b/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c\nindex b27206423537..8547eaaa7e40 100644\n--- a/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c\n+++ b/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c\n@@ -651,55 +651,70 @@ static int ice_alloc_vf_res(struct ice_vf *vf)\n }\n \n /**\n- * ice_ena_vf_mappings\n- * @vf: pointer to the VF structure\n+ * ice_ena_vf_msix_mappings - enable VF MSIX mappings in hardware\n+ * @vf: VF to enable MSIX mappings for\n *\n- * Enable VF vectors and queues allocation by writing the details into\n- * respective registers.\n+ * Some of the registers need to be indexed/configured using hardware global\n+ * device values and other registers need 0-based values, which represent PF\n+ * based values.\n */\n-static void ice_ena_vf_mappings(struct ice_vf *vf)\n+static void ice_ena_vf_msix_mappings(struct ice_vf *vf)\n {\n-\tint abs_vf_id, abs_first, abs_last;\n+\tint device_based_first_msix, device_based_last_msix;\n+\tint pf_based_first_msix, pf_based_last_msix, v;\n \tstruct ice_pf *pf = vf->pf;\n-\tstruct ice_vsi *vsi;\n-\tstruct device *dev;\n-\tint first, last, v;\n+\tint device_based_vf_id;\n \tstruct ice_hw *hw;\n \tu32 reg;\n \n-\tdev = ice_pf_to_dev(pf);\n \thw = &pf->hw;\n-\tvsi = pf->vsi[vf->lan_vsi_idx];\n-\tfirst = vf->first_vector_idx;\n-\tlast = (first + pf->num_msix_per_vf) - 1;\n-\tabs_first = first + pf->hw.func_caps.common_cap.msix_vector_first_id;\n-\tabs_last = (abs_first + pf->num_msix_per_vf) - 1;\n-\tabs_vf_id = vf->vf_id + hw->func_caps.vf_base_id;\n-\n-\t/* VF Vector allocation */\n-\treg = (((abs_first << VPINT_ALLOC_FIRST_S) & VPINT_ALLOC_FIRST_M) |\n-\t ((abs_last << VPINT_ALLOC_LAST_S) & VPINT_ALLOC_LAST_M) |\n-\t VPINT_ALLOC_VALID_M);\n+\tpf_based_first_msix = vf->first_vector_idx;\n+\tpf_based_last_msix = (pf_based_first_msix + pf->num_msix_per_vf) - 1;\n+\n+\tdevice_based_first_msix = pf_based_first_msix +\n+\t\tpf->hw.func_caps.common_cap.msix_vector_first_id;\n+\tdevice_based_last_msix =\n+\t\t(device_based_first_msix + pf->num_msix_per_vf) - 1;\n+\tdevice_based_vf_id = vf->vf_id + hw->func_caps.vf_base_id;\n+\n+\treg = (((device_based_first_msix << VPINT_ALLOC_FIRST_S) &\n+\t\tVPINT_ALLOC_FIRST_M) |\n+\t ((device_based_last_msix << VPINT_ALLOC_LAST_S) &\n+\t\tVPINT_ALLOC_LAST_M) | VPINT_ALLOC_VALID_M);\n \twr32(hw, VPINT_ALLOC(vf->vf_id), reg);\n \n-\treg = (((abs_first << VPINT_ALLOC_PCI_FIRST_S)\n+\treg = (((device_based_first_msix << VPINT_ALLOC_PCI_FIRST_S)\n \t\t & VPINT_ALLOC_PCI_FIRST_M) |\n-\t ((abs_last << VPINT_ALLOC_PCI_LAST_S) & VPINT_ALLOC_PCI_LAST_M) |\n-\t VPINT_ALLOC_PCI_VALID_M);\n+\t ((device_based_last_msix << VPINT_ALLOC_PCI_LAST_S) &\n+\t\tVPINT_ALLOC_PCI_LAST_M) | VPINT_ALLOC_PCI_VALID_M);\n \twr32(hw, VPINT_ALLOC_PCI(vf->vf_id), reg);\n+\n \t/* map the interrupts to its functions */\n-\tfor (v = first; v <= last; v++) {\n-\t\treg = (((abs_vf_id << GLINT_VECT2FUNC_VF_NUM_S) &\n+\tfor (v = pf_based_first_msix; v <= pf_based_last_msix; v++) {\n+\t\treg = (((device_based_vf_id << GLINT_VECT2FUNC_VF_NUM_S) &\n \t\t\tGLINT_VECT2FUNC_VF_NUM_M) |\n \t\t ((hw->pf_id << GLINT_VECT2FUNC_PF_NUM_S) &\n \t\t\tGLINT_VECT2FUNC_PF_NUM_M));\n \t\twr32(hw, GLINT_VECT2FUNC(v), reg);\n \t}\n \n-\t/* Map mailbox interrupt. We put an explicit 0 here to remind us that\n-\t * VF admin queue interrupts will go to VF MSI-X vector 0.\n-\t */\n-\twr32(hw, VPINT_MBX_CTL(abs_vf_id), VPINT_MBX_CTL_CAUSE_ENA_M | 0);\n+\t/* Map mailbox interrupt to VF MSI-X vector 0 */\n+\twr32(hw, VPINT_MBX_CTL(device_based_vf_id), VPINT_MBX_CTL_CAUSE_ENA_M);\n+}\n+\n+/**\n+ * ice_ena_vf_q_mappings - enable Rx/Tx queue mappings for a VF\n+ * @vf: VF to enable the mappings for\n+ * @max_txq: max Tx queues allowed on the VF's VSI\n+ * @max_rxq: max Rx queues allowed on the VF's VSI\n+ */\n+static void ice_ena_vf_q_mappings(struct ice_vf *vf, u16 max_txq, u16 max_rxq)\n+{\n+\tstruct ice_vsi *vsi = vf->pf->vsi[vf->lan_vsi_idx];\n+\tstruct device *dev = ice_pf_to_dev(vf->pf);\n+\tstruct ice_hw *hw = &vf->pf->hw;\n+\tu32 reg;\n+\n \t/* set regardless of mapping mode */\n \twr32(hw, VPLAN_TXQ_MAPENA(vf->vf_id), VPLAN_TXQ_MAPENA_TX_ENA_M);\n \n@@ -711,7 +726,7 @@ static void ice_ena_vf_mappings(struct ice_vf *vf)\n \t\t */\n \t\treg = (((vsi->txq_map[0] << VPLAN_TX_QBASE_VFFIRSTQ_S) &\n \t\t\tVPLAN_TX_QBASE_VFFIRSTQ_M) |\n-\t\t (((vsi->alloc_txq - 1) << VPLAN_TX_QBASE_VFNUMQ_S) &\n+\t\t (((max_txq - 1) << VPLAN_TX_QBASE_VFNUMQ_S) &\n \t\t\tVPLAN_TX_QBASE_VFNUMQ_M));\n \t\twr32(hw, VPLAN_TX_QBASE(vf->vf_id), reg);\n \t} else {\n@@ -729,7 +744,7 @@ static void ice_ena_vf_mappings(struct ice_vf *vf)\n \t\t */\n \t\treg = (((vsi->rxq_map[0] << VPLAN_RX_QBASE_VFFIRSTQ_S) &\n \t\t\tVPLAN_RX_QBASE_VFFIRSTQ_M) |\n-\t\t (((vsi->alloc_txq - 1) << VPLAN_RX_QBASE_VFNUMQ_S) &\n+\t\t (((max_rxq - 1) << VPLAN_RX_QBASE_VFNUMQ_S) &\n \t\t\tVPLAN_RX_QBASE_VFNUMQ_M));\n \t\twr32(hw, VPLAN_RX_QBASE(vf->vf_id), reg);\n \t} else {\n@@ -737,6 +752,18 @@ static void ice_ena_vf_mappings(struct ice_vf *vf)\n \t}\n }\n \n+/**\n+ * ice_ena_vf_mappings - enable VF MSIX and queue mapping\n+ * @vf: pointer to the VF structure\n+ */\n+static void ice_ena_vf_mappings(struct ice_vf *vf)\n+{\n+\tstruct ice_vsi *vsi = vf->pf->vsi[vf->lan_vsi_idx];\n+\n+\tice_ena_vf_msix_mappings(vf);\n+\tice_ena_vf_q_mappings(vf, vsi->alloc_txq, vsi->alloc_rxq);\n+}\n+\n /**\n * ice_determine_res\n * @pf: pointer to the PF structure\n", "prefixes": [ "S45", "01/15" ] }