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GET /api/patches/1291743/?format=api
{ "id": 1291743, "url": "http://patchwork.ozlabs.org/api/patches/1291743/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200516003644.4658-1-anthony.l.nguyen@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20200516003644.4658-1-anthony.l.nguyen@intel.com>", "list_archive_url": null, "date": "2020-05-16T00:36:30", "name": "[S43,01/15] ice: Call ice_aq_set_mac_cfg", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "63bb827cd614884a3605551e92a0559134a73cdb", "submitter": { "id": 68875, "url": "http://patchwork.ozlabs.org/api/people/68875/?format=api", "name": "Tony Nguyen", "email": "anthony.l.nguyen@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200516003644.4658-1-anthony.l.nguyen@intel.com/mbox/", "series": [ { "id": 177325, "url": "http://patchwork.ozlabs.org/api/series/177325/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=177325", "date": "2020-05-16T00:36:39", "name": "[S43,01/15] ice: Call ice_aq_set_mac_cfg", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/177325/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1291743/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1291743/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n envelope-from=intel-wired-lan-bounces@osuosl.org; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 49P5y95L9nz9sTM\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 16 May 2020 10:39:29 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 0F17F87C49;\n\tSat, 16 May 2020 00:39:28 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id OrPLWxNs8rVV; Sat, 16 May 2020 00:39:23 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id D878887740;\n\tSat, 16 May 2020 00:39:23 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n by ash.osuosl.org (Postfix) with ESMTP id B95E41BF2B9\n for <intel-wired-lan@lists.osuosl.org>; Sat, 16 May 2020 00:39:20 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n by whitealder.osuosl.org (Postfix) with ESMTP id B65FF877FA\n for <intel-wired-lan@lists.osuosl.org>; Sat, 16 May 2020 00:39:20 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n with ESMTP id r0WUct3Lkc6v for <intel-wired-lan@lists.osuosl.org>;\n Sat, 16 May 2020 00:39:19 +0000 (UTC)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by whitealder.osuosl.org (Postfix) with ESMTPS id 1CAE58771C\n for <intel-wired-lan@lists.osuosl.org>; Sat, 16 May 2020 00:39:19 +0000 (UTC)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 May 2020 17:39:18 -0700", "from unknown (HELO localhost.jf.intel.com) ([10.166.241.65])\n by FMSMGA003.fm.intel.com with ESMTP; 15 May 2020 17:39:18 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "IronPort-SDR": [ "\n iXuTeTYUYxZGm6n9TtApVFy5ar7+ZC0jEXNFtAA9m9XAUV1Vfw+ZolikmpYloHV83BTmHfYP9E\n CZvkH7lDU5QA==", "\n pF0UbtCL2PdDTzGpimqpGd5ZnCR9DYQjRDcY/y9TXxwWPu+M6dR30wNY/xJM9ZfAPJBDzwFTE2\n lmjYR8sWrt+g==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.73,397,1583222400\"; d=\"scan'208\";a=\"307560856\"", "From": "Tony Nguyen <anthony.l.nguyen@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Fri, 15 May 2020 17:36:30 -0700", "Message-Id": "<20200516003644.4658-1-anthony.l.nguyen@intel.com>", "X-Mailer": "git-send-email 2.20.1", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH S43 01/15] ice: Call ice_aq_set_mac_cfg", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n\nAs per the specification, the driver needs to call set_mac_cfg\n(opcode 0x0603) to be able to exercise jumbo frames. Call the\nfunction during initialization and the post reset rebuild flow.\n\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\nSigned-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>\n---\n .../net/ethernet/intel/ice/ice_adminq_cmd.h | 21 ++++++\n drivers/net/ethernet/intel/ice/ice_common.c | 69 +++++++++++++++++++\n drivers/net/ethernet/intel/ice/ice_common.h | 2 +\n .../net/ethernet/intel/ice/ice_hw_autogen.h | 5 ++\n drivers/net/ethernet/intel/ice/ice_main.c | 6 ++\n 5 files changed, 103 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\nindex 745f58a86a1d..1586f24f26fb 100644\n--- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n@@ -1069,6 +1069,25 @@ struct ice_aqc_set_phy_cfg_data {\n \tu8 rsvd1;\n };\n \n+/* Set MAC Config command data structure (direct 0x0603) */\n+struct ice_aqc_set_mac_cfg {\n+\t__le16 max_frame_size;\n+\tu8 params;\n+#define ICE_AQ_SET_MAC_PACE_S\t\t3\n+#define ICE_AQ_SET_MAC_PACE_M\t\t(0xF << ICE_AQ_SET_MAC_PACE_S)\n+#define ICE_AQ_SET_MAC_PACE_TYPE_M\tBIT(7)\n+#define ICE_AQ_SET_MAC_PACE_TYPE_RATE\t0\n+#define ICE_AQ_SET_MAC_PACE_TYPE_FIXED\tICE_AQ_SET_MAC_PACE_TYPE_M\n+\tu8 tx_tmr_priority;\n+\t__le16 tx_tmr_value;\n+\t__le16 fc_refresh_threshold;\n+\tu8 drop_opts;\n+#define ICE_AQ_SET_MAC_AUTO_DROP_MASK\t\tBIT(0)\n+#define ICE_AQ_SET_MAC_AUTO_DROP_NONE\t\t0\n+#define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS\tBIT(0)\n+\tu8 reserved[7];\n+};\n+\n /* Restart AN command data structure (direct 0x0605)\n * Also used for response, with only the lport_num field present.\n */\n@@ -1806,6 +1825,7 @@ struct ice_aq_desc {\n \t\tstruct ice_aqc_download_pkg download_pkg;\n \t\tstruct ice_aqc_set_mac_lb set_mac_lb;\n \t\tstruct ice_aqc_alloc_free_res_cmd sw_res_ctrl;\n+\t\tstruct ice_aqc_set_mac_cfg set_mac_cfg;\n \t\tstruct ice_aqc_set_event_mask set_event_mask;\n \t\tstruct ice_aqc_get_link_status get_link_status;\n \t\tstruct ice_aqc_event_lan_overflow lan_overflow;\n@@ -1902,6 +1922,7 @@ enum ice_adminq_opc {\n \t/* PHY commands */\n \tice_aqc_opc_get_phy_caps\t\t\t= 0x0600,\n \tice_aqc_opc_set_phy_cfg\t\t\t\t= 0x0601,\n+\tice_aqc_opc_set_mac_cfg\t\t\t\t= 0x0603,\n \tice_aqc_opc_restart_an\t\t\t\t= 0x0605,\n \tice_aqc_opc_get_link_status\t\t\t= 0x0607,\n \tice_aqc_opc_set_event_mask\t\t\t= 0x0613,\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c\nindex aa3cad00a78a..06beae93176e 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.c\n+++ b/drivers/net/ethernet/intel/ice/ice_common.c\n@@ -315,6 +315,71 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n \treturn 0;\n }\n \n+/**\n+ * ice_fill_tx_timer_and_fc_thresh\n+ * @hw: pointer to the HW struct\n+ * @cmd: pointer to MAC cfg structure\n+ *\n+ * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command\n+ * descriptor\n+ */\n+static void\n+ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,\n+\t\t\t\tstruct ice_aqc_set_mac_cfg *cmd)\n+{\n+\tu16 fc_thres_val, tx_timer_val;\n+\tu32 val;\n+\n+\t/* We read back the transmit timer and FC threshold value of\n+\t * LFC. Thus, we will use index =\n+\t * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.\n+\t *\n+\t * Also, because we are operating on transmit timer and FC\n+\t * threshold of LFC, we don't turn on any bit in tx_tmr_priority\n+\t */\n+#define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX\n+\n+\t/* Retrieve the transmit timer */\n+\tval = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));\n+\ttx_timer_val = val &\n+\t\tPRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;\n+\tcmd->tx_tmr_value = cpu_to_le16(tx_timer_val);\n+\n+\t/* Retrieve the FC threshold */\n+\tval = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));\n+\tfc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;\n+\n+\tcmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val);\n+}\n+\n+/**\n+ * ice_aq_set_mac_cfg\n+ * @hw: pointer to the HW struct\n+ * @max_frame_size: Maximum Frame Size to be supported\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Set MAC configuration (0x0603)\n+ */\n+enum ice_status\n+ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_set_mac_cfg *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.set_mac_cfg;\n+\n+\tif (max_frame_size == 0)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);\n+\n+\tcmd->max_frame_size = cpu_to_le16(max_frame_size);\n+\n+\tice_fill_tx_timer_and_fc_thresh(hw, cmd);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n+\n /**\n * ice_init_fltr_mgmt_struct - initializes filter management list and locks\n * @hw: pointer to the HW struct\n@@ -745,6 +810,10 @@ enum ice_status ice_init_hw(struct ice_hw *hw)\n \tstatus = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);\n \tdevm_kfree(ice_hw_to_dev(hw), mac_buf);\n \n+\tif (status)\n+\t\tgoto err_unroll_fltr_mgmt_struct;\n+\t/* enable jumbo frame support at MAC level */\n+\tstatus = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);\n \tif (status)\n \t\tgoto err_unroll_fltr_mgmt_struct;\n \t/* Obtain counter base index which would be used by flow director */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h\nindex db63fd6b5608..9bac3e46da33 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.h\n+++ b/drivers/net/ethernet/intel/ice/ice_common.h\n@@ -108,6 +108,8 @@ enum ice_status\n ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,\n \t\t\t struct ice_sq_cd *cd);\n enum ice_status\n+ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);\n+enum ice_status\n ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n \t\t struct ice_link_status *link, struct ice_sq_cd *cd);\n enum ice_status\ndiff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\nindex 30c28a4bcf2f..16ec9bebf4b4 100644\n--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n@@ -219,6 +219,11 @@\n #define VPLAN_TX_QBASE_VFNUMQ_M\t\t\tICE_M(0xFF, 16)\n #define VPLAN_TXQ_MAPENA(_VF)\t\t\t(0x00073800 + ((_VF) * 4))\n #define VPLAN_TXQ_MAPENA_TX_ENA_M\t\tBIT(0)\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i)\t(0x001E36E0 + ((_i) * 32))\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M ICE_M(0xFFFF, 0)\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32))\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M ICE_M(0xFFFF, 0)\n #define GL_MDCK_TX_TDPU\t\t\t\t0x00049348\n #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)\n #define GL_MDET_RX\t\t\t\t0x00294C00\ndiff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c\nindex f738e3046fb5..6af21510c694 100644\n--- a/drivers/net/ethernet/intel/ice/ice_main.c\n+++ b/drivers/net/ethernet/intel/ice/ice_main.c\n@@ -4963,6 +4963,12 @@ static void ice_rebuild(struct ice_pf *pf, enum ice_reset_req reset_type)\n \t\tgoto err_init_ctrlq;\n \t}\n \n+\tret = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);\n+\tif (ret) {\n+\t\tdev_err(dev, \"set_mac_cfg failed %s\\n\", ice_stat_str(ret));\n+\t\tgoto err_init_ctrlq;\n+\t}\n+\n \terr = ice_sched_init_port(hw->port_info);\n \tif (err)\n \t\tgoto err_sched_init_port;\n", "prefixes": [ "S43", "01/15" ] }