Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1288149/?format=api
{ "id": 1288149, "url": "http://patchwork.ozlabs.org/api/patches/1288149/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200512010146.41303-5-anthony.l.nguyen@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20200512010146.41303-5-anthony.l.nguyen@intel.com>", "list_archive_url": null, "date": "2020-05-12T01:01:44", "name": "[S42,5/7] ice: Enable flex-bytes support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "5a1970a95649a990c158029e77ae54f65777f9f9", "submitter": { "id": 68875, "url": "http://patchwork.ozlabs.org/api/people/68875/?format=api", "name": "Tony Nguyen", "email": "anthony.l.nguyen@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200512010146.41303-5-anthony.l.nguyen@intel.com/mbox/", "series": [ { "id": 176248, "url": "http://patchwork.ozlabs.org/api/series/176248/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=176248", "date": "2020-05-12T01:01:45", "name": "[S42,1/7] ice: Initialize Flow Director resources", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/176248/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1288149/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1288149/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n envelope-from=intel-wired-lan-bounces@osuosl.org; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 49Lfj15xypz9sRf\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 12 May 2020 11:04:37 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 3250886C53;\n\tTue, 12 May 2020 01:04:36 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id wn1pwZ+YA9fI; Tue, 12 May 2020 01:04:27 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 4B13E8695C;\n\tTue, 12 May 2020 01:04:24 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n by ash.osuosl.org (Postfix) with ESMTP id 54B401BF841\n for <intel-wired-lan@lists.osuosl.org>; Tue, 12 May 2020 01:04:23 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n by whitealder.osuosl.org (Postfix) with ESMTP id 50BF1867CC\n for <intel-wired-lan@lists.osuosl.org>; Tue, 12 May 2020 01:04:23 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n with ESMTP id 4GKtfC3IIJSh for <intel-wired-lan@lists.osuosl.org>;\n Tue, 12 May 2020 01:04:20 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by whitealder.osuosl.org (Postfix) with ESMTPS id B6789868C6\n for <intel-wired-lan@lists.osuosl.org>; Tue, 12 May 2020 01:04:20 +0000 (UTC)", "from orsmga004.jf.intel.com ([10.7.209.38])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 May 2020 18:04:20 -0700", "from unknown (HELO localhost.jf.intel.com) ([10.166.241.65])\n by orsmga004.jf.intel.com with ESMTP; 11 May 2020 18:04:19 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "IronPort-SDR": [ "\n pYEha3w9XX740JQ2qASIEAjG7sVNdjl78uEwJLKO/lYLy37fyfKwOyZhkj2TZnRmQaTz2llgWi\n q2sGhTvFLBuw==", "\n 6tK+YBNGiveWD2A5flwIWziZ8AmqGWwGd5fldeF46azRl+PpRdP5PNwAXZqTM6hIc95WlRFFeg\n khLZrYB8deYg==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.73,381,1583222400\"; d=\"scan'208\";a=\"409116468\"", "From": "Tony Nguyen <anthony.l.nguyen@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Mon, 11 May 2020 18:01:44 -0700", "Message-Id": "<20200512010146.41303-5-anthony.l.nguyen@intel.com>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20200512010146.41303-1-anthony.l.nguyen@intel.com>", "References": "<20200512010146.41303-1-anthony.l.nguyen@intel.com>", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH S42 5/7] ice: Enable flex-bytes support", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Henry Tieman <henry.w.tieman@intel.com>\n\nFlex-bytes allows for packet matching based on an offset and value. This\nis supported via the ethtool user-def option. It is specified by providing\nan offset followed by a 2 byte match value. Offset is measured from the\nstart of the MAC address.\n\nThe following restrictions apply to flex-bytes. The specified offset must\nbe an even number and be smaller than 0x1fe.\n\nExample usage:\n\nethtool -N eth0 flow-type tcp4 src-ip 192.168.0.55 dst-ip 172.16.0.55 \\\nsrc-port 12 dst-port 13 user-def 0x10ffff action 32\n\nSigned-off-by: Henry Tieman <henry.w.tieman@intel.com>\nSigned-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>\n---\n .../net/ethernet/intel/ice/ice_ethtool_fdir.c | 88 +++++++++-\n drivers/net/ethernet/intel/ice/ice_fdir.c | 3 +\n drivers/net/ethernet/intel/ice/ice_fdir.h | 13 ++\n drivers/net/ethernet/intel/ice/ice_flow.c | 150 ++++++++++++++++++\n drivers/net/ethernet/intel/ice/ice_flow.h | 12 ++\n .../ethernet/intel/ice/ice_protocol_type.h | 1 +\n 6 files changed, 265 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c b/drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c\nindex 5b7774aabe3c..223a883f7796 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c\n+++ b/drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c\n@@ -92,6 +92,19 @@ static enum ice_fltr_ptype ice_ethtool_flow_to_fltr(int eth)\n \t}\n }\n \n+/**\n+ * ice_is_mask_valid - check mask field set\n+ * @mask: full mask to check\n+ * @field: field for which mask should be valid\n+ *\n+ * If the mask is fully set return true. If it is not valid for field return\n+ * false.\n+ */\n+static bool ice_is_mask_valid(u64 mask, u64 field)\n+{\n+\treturn (mask & field) == field;\n+}\n+\n /**\n * ice_get_ethtool_fdir_entry - fill ethtool structure with fdir filter data\n * @hw: hardware structure that contains filter list\n@@ -335,6 +348,53 @@ void ice_fdir_release_flows(struct ice_hw *hw)\n \t\tice_fdir_erase_flow_from_hw(hw, ICE_BLK_FD, flow);\n }\n \n+/**\n+ * ice_parse_rx_flow_user_data - deconstruct user-defined data\n+ * @fsp: pointer to ethtool Rx flow specification\n+ * @data: pointer to userdef data structure for storage\n+ *\n+ * Returns 0 on success, negative error value on failure\n+ */\n+static int\n+ice_parse_rx_flow_user_data(struct ethtool_rx_flow_spec *fsp,\n+\t\t\t struct ice_rx_flow_userdef *data)\n+{\n+\tu64 value, mask;\n+\n+\tmemset(data, 0, sizeof(*data));\n+\tif (!(fsp->flow_type & FLOW_EXT))\n+\t\treturn 0;\n+\n+\tvalue = be64_to_cpu(*((__force __be64 *)fsp->h_ext.data));\n+\tmask = be64_to_cpu(*((__force __be64 *)fsp->m_ext.data));\n+\tif (!mask)\n+\t\treturn 0;\n+\n+#define ICE_USERDEF_FLEX_WORD_M\tGENMASK_ULL(15, 0)\n+#define ICE_USERDEF_FLEX_OFFS_S\t16\n+#define ICE_USERDEF_FLEX_OFFS_M\tGENMASK_ULL(31, ICE_USERDEF_FLEX_OFFS_S)\n+#define ICE_USERDEF_FLEX_FLTR_M\tGENMASK_ULL(31, 0)\n+\n+\t/* 0x1fe is the maximum value for offsets stored in the internal\n+\t * filtering tables.\n+\t */\n+#define ICE_USERDEF_FLEX_MAX_OFFS_VAL 0x1fe\n+\n+\tif (!ice_is_mask_valid(mask, ICE_USERDEF_FLEX_FLTR_M) ||\n+\t value > ICE_USERDEF_FLEX_FLTR_M)\n+\t\treturn -EINVAL;\n+\n+\tdata->flex_word = value & ICE_USERDEF_FLEX_WORD_M;\n+\tdata->flex_offset = (value & ICE_USERDEF_FLEX_OFFS_M) >>\n+\t\t\t ICE_USERDEF_FLEX_OFFS_S;\n+\tif (data->flex_offset > ICE_USERDEF_FLEX_MAX_OFFS_VAL)\n+\t\treturn -EINVAL;\n+\n+\tdata->flex_fltr = true;\n+\n+\treturn 0;\n+}\n+\n /**\n * ice_fdir_num_avail_fltr - return the number of unused flow director filters\n * @hw: pointer to hardware structure\n@@ -936,11 +996,13 @@ ice_set_fdir_ip6_usr_seg(struct ice_flow_seg_info *seg,\n * ice_cfg_fdir_xtrct_seq - Configure extraction sequence for the given filter\n * @pf: PF structure\n * @fsp: pointer to ethtool Rx flow specification\n+ * @user: user defined data from flow specification\n *\n * Returns 0 on success.\n */\n static int\n-ice_cfg_fdir_xtrct_seq(struct ice_pf *pf, struct ethtool_rx_flow_spec *fsp)\n+ice_cfg_fdir_xtrct_seq(struct ice_pf *pf, struct ethtool_rx_flow_spec *fsp,\n+\t\t struct ice_rx_flow_userdef *user)\n {\n \tstruct ice_flow_seg_info *seg, *tun_seg;\n \tstruct device *dev = ice_pf_to_dev(pf);\n@@ -1008,6 +1070,18 @@ ice_cfg_fdir_xtrct_seq(struct ice_pf *pf, struct ethtool_rx_flow_spec *fsp)\n \t/* tunnel segments are shifted up one. */\n \tmemcpy(&tun_seg[1], seg, sizeof(*seg));\n \n+\tif (user && user->flex_fltr) {\n+\t\tperfect_filter = false;\n+\t\tice_flow_add_fld_raw(seg, user->flex_offset,\n+\t\t\t\t ICE_FLTR_PRGM_FLEX_WORD_SIZE,\n+\t\t\t\t ICE_FLOW_FLD_OFF_INVAL,\n+\t\t\t\t ICE_FLOW_FLD_OFF_INVAL);\n+\t\tice_flow_add_fld_raw(&tun_seg[1], user->flex_offset,\n+\t\t\t\t ICE_FLTR_PRGM_FLEX_WORD_SIZE,\n+\t\t\t\t ICE_FLOW_FLD_OFF_INVAL,\n+\t\t\t\t ICE_FLOW_FLD_OFF_INVAL);\n+\t}\n+\n \t/* add filter for outer headers */\n \tfltr_idx = ice_ethtool_flow_to_fltr(fsp->flow_type & ~FLOW_EXT);\n \tret = ice_fdir_set_hw_fltr_rule(pf, seg, fltr_idx,\n@@ -1433,6 +1507,7 @@ ice_set_fdir_input_set(struct ice_vsi *vsi, struct ethtool_rx_flow_spec *fsp,\n */\n int ice_add_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd)\n {\n+\tstruct ice_rx_flow_userdef userdata;\n \tstruct ethtool_rx_flow_spec *fsp;\n \tstruct ice_fdir_fltr *input;\n \tstruct device *dev;\n@@ -1460,10 +1535,13 @@ int ice_add_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd)\n \n \tfsp = (struct ethtool_rx_flow_spec *)&cmd->fs;\n \n+\tif (ice_parse_rx_flow_user_data(fsp, &userdata))\n+\t\treturn -EINVAL;\n+\n \tif (fsp->flow_type & FLOW_MAC_EXT)\n \t\treturn -EINVAL;\n \n-\tret = ice_cfg_fdir_xtrct_seq(pf, fsp);\n+\tret = ice_cfg_fdir_xtrct_seq(pf, fsp, &userdata);\n \tif (ret)\n \t\treturn ret;\n \n@@ -1495,6 +1573,12 @@ int ice_add_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd)\n \t\tgoto release_lock;\n \t}\n \n+\tif (userdata.flex_fltr) {\n+\t\tinput->flex_fltr = true;\n+\t\tinput->flex_word = cpu_to_be16(userdata.flex_word);\n+\t\tinput->flex_offset = userdata.flex_offset;\n+\t}\n+\n \t/* input struct is added to the HW filter list */\n \tice_fdir_update_list_entry(pf, input, fsp->location);\n \ndiff --git a/drivers/net/ethernet/intel/ice/ice_fdir.c b/drivers/net/ethernet/intel/ice/ice_fdir.c\nindex e94277dc9cdc..548a41140c05 100644\n--- a/drivers/net/ethernet/intel/ice/ice_fdir.c\n+++ b/drivers/net/ethernet/intel/ice/ice_fdir.c\n@@ -650,6 +650,9 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,\n \t\treturn ICE_ERR_PARAM;\n \t}\n \n+\tif (input->flex_fltr)\n+\t\tice_pkt_insert_u16(loc, input->flex_offset, input->flex_word);\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/ethernet/intel/ice/ice_fdir.h b/drivers/net/ethernet/intel/ice/ice_fdir.h\nindex 1a47420d67b2..d6e47b645cdd 100644\n--- a/drivers/net/ethernet/intel/ice/ice_fdir.h\n+++ b/drivers/net/ethernet/intel/ice/ice_fdir.h\n@@ -68,6 +68,14 @@ struct ice_fd_fltr_desc_ctx {\n \tu8 fdid_mdid;\n };\n \n+#define ICE_FLTR_PRGM_FLEX_WORD_SIZE\tsizeof(__be16)\n+\n+struct ice_rx_flow_userdef {\n+\tu16 flex_word;\n+\tu16 flex_offset;\n+\tu16 flex_fltr;\n+};\n+\n struct ice_fdir_v4 {\n \t__be32 dst_ip;\n \t__be32 src_ip;\n@@ -112,6 +120,11 @@ struct ice_fdir_fltr {\n \tstruct ice_fdir_extra ext_data;\n \tstruct ice_fdir_extra ext_mask;\n \n+\t/* flex byte filter data */\n+\t__be16 flex_word;\n+\tu16 flex_offset;\n+\tu16 flex_fltr;\n+\n \t/* filter control */\n \tu16 q_index;\n \tu16 dest_vsi;\ndiff --git a/drivers/net/ethernet/intel/ice/ice_flow.c b/drivers/net/ethernet/intel/ice/ice_flow.c\nindex f4b6c3933564..d74e5290677f 100644\n--- a/drivers/net/ethernet/intel/ice/ice_flow.c\n+++ b/drivers/net/ethernet/intel/ice/ice_flow.c\n@@ -193,6 +193,40 @@ ice_flow_val_hdrs(struct ice_flow_seg_info *segs, u8 segs_cnt)\n \treturn 0;\n }\n \n+/* Sizes of fixed known protocol headers without header options */\n+#define ICE_FLOW_PROT_HDR_SZ_MAC\t14\n+#define ICE_FLOW_PROT_HDR_SZ_IPV4\t20\n+#define ICE_FLOW_PROT_HDR_SZ_IPV6\t40\n+#define ICE_FLOW_PROT_HDR_SZ_TCP\t20\n+#define ICE_FLOW_PROT_HDR_SZ_UDP\t8\n+#define ICE_FLOW_PROT_HDR_SZ_SCTP\t12\n+\n+/**\n+ * ice_flow_calc_seg_sz - calculates size of a packet segment based on headers\n+ * @params: information about the flow to be processed\n+ * @seg: index of packet segment whose header size is to be determined\n+ */\n+static u16 ice_flow_calc_seg_sz(struct ice_flow_prof_params *params, u8 seg)\n+{\n+\tu16 sz = ICE_FLOW_PROT_HDR_SZ_MAC;\n+\n+\t/* L3 headers */\n+\tif (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_IPV4)\n+\t\tsz += ICE_FLOW_PROT_HDR_SZ_IPV4;\n+\telse if (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_IPV6)\n+\t\tsz += ICE_FLOW_PROT_HDR_SZ_IPV6;\n+\n+\t/* L4 headers */\n+\tif (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_TCP)\n+\t\tsz += ICE_FLOW_PROT_HDR_SZ_TCP;\n+\telse if (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_UDP)\n+\t\tsz += ICE_FLOW_PROT_HDR_SZ_UDP;\n+\telse if (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_SCTP)\n+\t\tsz += ICE_FLOW_PROT_HDR_SZ_SCTP;\n+\n+\treturn sz;\n+}\n+\n /**\n * ice_flow_proc_seg_hdrs - process protocol headers present in pkt segments\n * @params: information about the flow to be processed\n@@ -347,6 +381,81 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,\n \treturn 0;\n }\n \n+/**\n+ * ice_flow_xtract_raws - Create extract sequence entries for raw bytes\n+ * @hw: pointer to the HW struct\n+ * @params: information about the flow to be processed\n+ * @seg: index of packet segment whose raw fields are to be be extracted\n+ */\n+static enum ice_status\n+ice_flow_xtract_raws(struct ice_hw *hw, struct ice_flow_prof_params *params,\n+\t\t u8 seg)\n+{\n+\tu16 fv_words;\n+\tu16 hdrs_sz;\n+\tu8 i;\n+\n+\tif (!params->prof->segs[seg].raws_cnt)\n+\t\treturn 0;\n+\n+\tif (params->prof->segs[seg].raws_cnt >\n+\t ARRAY_SIZE(params->prof->segs[seg].raws))\n+\t\treturn ICE_ERR_MAX_LIMIT;\n+\n+\t/* Offsets within the segment headers are not supported */\n+\thdrs_sz = ice_flow_calc_seg_sz(params, seg);\n+\tif (!hdrs_sz)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tfv_words = hw->blk[params->blk].es.fvw;\n+\n+\tfor (i = 0; i < params->prof->segs[seg].raws_cnt; i++) {\n+\t\tstruct ice_flow_seg_fld_raw *raw;\n+\t\tu16 off, cnt, j;\n+\n+\t\traw = ¶ms->prof->segs[seg].raws[i];\n+\n+\t\t/* Storing extraction information */\n+\t\traw->info.xtrct.prot_id = ICE_PROT_MAC_OF_OR_S;\n+\t\traw->info.xtrct.off = (raw->off / ICE_FLOW_FV_EXTRACT_SZ) *\n+\t\t\tICE_FLOW_FV_EXTRACT_SZ;\n+\t\traw->info.xtrct.disp = (raw->off % ICE_FLOW_FV_EXTRACT_SZ) *\n+\t\t\tBITS_PER_BYTE;\n+\t\traw->info.xtrct.idx = params->es_cnt;\n+\n+\t\t/* Determine the number of field vector entries this raw field\n+\t\t * consumes.\n+\t\t */\n+\t\tcnt = DIV_ROUND_UP(raw->info.xtrct.disp +\n+\t\t\t\t (raw->info.src.last * BITS_PER_BYTE),\n+\t\t\t\t (ICE_FLOW_FV_EXTRACT_SZ * BITS_PER_BYTE));\n+\t\toff = raw->info.xtrct.off;\n+\t\tfor (j = 0; j < cnt; j++) {\n+\t\t\tu16 idx;\n+\n+\t\t\t/* Make sure the number of extraction sequence required\n+\t\t\t * does not exceed the block's capability\n+\t\t\t */\n+\t\t\tif (params->es_cnt >= hw->blk[params->blk].es.count ||\n+\t\t\t params->es_cnt >= ICE_MAX_FV_WORDS)\n+\t\t\t\treturn ICE_ERR_MAX_LIMIT;\n+\n+\t\t\t/* some blocks require a reversed field vector layout */\n+\t\t\tif (hw->blk[params->blk].es.reverse)\n+\t\t\t\tidx = fv_words - params->es_cnt - 1;\n+\t\t\telse\n+\t\t\t\tidx = params->es_cnt;\n+\n+\t\t\tparams->es[idx].prot_id = raw->info.xtrct.prot_id;\n+\t\t\tparams->es[idx].off = off;\n+\t\t\tparams->es_cnt++;\n+\t\t\toff += ICE_FLOW_FV_EXTRACT_SZ;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n /**\n * ice_flow_create_xtrct_seq - Create an extraction sequence for given segments\n * @hw: pointer to the HW struct\n@@ -373,6 +482,11 @@ ice_flow_create_xtrct_seq(struct ice_hw *hw,\n \t\t\tif (status)\n \t\t\t\treturn status;\n \t\t}\n+\n+\t\t/* Process raw matching bytes */\n+\t\tstatus = ice_flow_xtract_raws(hw, params, i);\n+\t\tif (status)\n+\t\t\treturn status;\n \t}\n \n \treturn status;\n@@ -943,6 +1057,42 @@ ice_flow_set_fld(struct ice_flow_seg_info *seg, enum ice_flow_field fld,\n \tice_flow_set_fld_ext(seg, fld, t, val_loc, mask_loc, last_loc);\n }\n \n+/**\n+ * ice_flow_add_fld_raw - sets locations of a raw field from entry's input buf\n+ * @seg: packet segment the field being set belongs to\n+ * @off: offset of the raw field from the beginning of the segment in bytes\n+ * @len: length of the raw pattern to be matched\n+ * @val_loc: location of the value to match from entry's input buffer\n+ * @mask_loc: location of mask value from entry's input buffer\n+ *\n+ * This function specifies the offset of the raw field to be match from the\n+ * beginning of the specified packet segment, and the locations, in the form of\n+ * byte offsets from the start of the input buffer for a flow entry, from where\n+ * the value to match and the mask value to be extracted. These locations are\n+ * then stored in the flow profile. When adding flow entries to the associated\n+ * flow profile, these locations can be used to quickly extract the values to\n+ * create the content of a match entry. This function should only be used for\n+ * fixed-size data structures.\n+ */\n+void\n+ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,\n+\t\t u16 val_loc, u16 mask_loc)\n+{\n+\tif (seg->raws_cnt < ICE_FLOW_SEG_RAW_FLD_MAX) {\n+\t\tseg->raws[seg->raws_cnt].off = off;\n+\t\tseg->raws[seg->raws_cnt].info.type = ICE_FLOW_FLD_TYPE_SIZE;\n+\t\tseg->raws[seg->raws_cnt].info.src.val = val_loc;\n+\t\tseg->raws[seg->raws_cnt].info.src.mask = mask_loc;\n+\t\t/* The \"last\" field is used to store the length of the field */\n+\t\tseg->raws[seg->raws_cnt].info.src.last = len;\n+\t}\n+\n+\t/* Overflows of \"raws\" will be handled as an error condition later in\n+\t * the flow when this information is processed.\n+\t */\n+\tseg->raws_cnt++;\n+}\n+\n #define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \\\n \t(ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)\n \ndiff --git a/drivers/net/ethernet/intel/ice/ice_flow.h b/drivers/net/ethernet/intel/ice/ice_flow.h\nindex 3c784c3b5db2..3913da2116d2 100644\n--- a/drivers/net/ethernet/intel/ice/ice_flow.h\n+++ b/drivers/net/ethernet/intel/ice/ice_flow.h\n@@ -128,6 +128,7 @@ enum ice_flow_priority {\n };\n \n #define ICE_FLOW_SEG_MAX\t\t2\n+#define ICE_FLOW_SEG_RAW_FLD_MAX\t2\n #define ICE_FLOW_FV_EXTRACT_SZ\t\t2\n \n #define ICE_FLOW_SET_HDRS(seg, val)\t((seg)->hdrs |= (u32)(val))\n@@ -164,12 +165,20 @@ struct ice_flow_fld_info {\n \tstruct ice_flow_seg_xtrct xtrct;\n };\n \n+struct ice_flow_seg_fld_raw {\n+\tstruct ice_flow_fld_info info;\n+\tu16 off;\t/* Offset from the start of the segment */\n+};\n+\n struct ice_flow_seg_info {\n \tu32 hdrs;\t/* Bitmask indicating protocol headers present */\n \tu64 match;\t/* Bitmask indicating header fields to be matched */\n \tu64 range;\t/* Bitmask indicating header fields matched as ranges */\n \n \tstruct ice_flow_fld_info fields[ICE_FLOW_FIELD_IDX_MAX];\n+\n+\tu8 raws_cnt;\t/* Number of raw fields to be matched */\n+\tstruct ice_flow_seg_fld_raw raws[ICE_FLOW_SEG_RAW_FLD_MAX];\n };\n \n /* This structure describes a flow entry, and is tracked only in this file */\n@@ -228,6 +237,9 @@ ice_flow_rem_entry(struct ice_hw *hw, enum ice_block blk, u64 entry_h);\n void\n ice_flow_set_fld(struct ice_flow_seg_info *seg, enum ice_flow_field fld,\n \t\t u16 val_loc, u16 mask_loc, u16 last_loc, bool range);\n+void\n+ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,\n+\t\t u16 val_loc, u16 mask_loc);\n void ice_rem_vsi_rss_list(struct ice_hw *hw, u16 vsi_handle);\n enum ice_status ice_replay_rss_cfg(struct ice_hw *hw, u16 vsi_handle);\n enum ice_status\ndiff --git a/drivers/net/ethernet/intel/ice/ice_protocol_type.h b/drivers/net/ethernet/intel/ice/ice_protocol_type.h\nindex babe4a485fd6..7f4c1ec1eff2 100644\n--- a/drivers/net/ethernet/intel/ice/ice_protocol_type.h\n+++ b/drivers/net/ethernet/intel/ice/ice_protocol_type.h\n@@ -12,6 +12,7 @@\n */\n enum ice_prot_id {\n \tICE_PROT_ID_INVAL\t= 0,\n+\tICE_PROT_MAC_OF_OR_S\t= 1,\n \tICE_PROT_IPV4_OF_OR_S\t= 32,\n \tICE_PROT_IPV4_IL\t= 33,\n \tICE_PROT_IPV6_OF_OR_S\t= 40,\n", "prefixes": [ "S42", "5/7" ] }