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GET /api/patches/1283660/?format=api
{ "id": 1283660, "url": "http://patchwork.ozlabs.org/api/patches/1283660/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200505140638.44937-1-vitaly.lifshits@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20200505140638.44937-1-vitaly.lifshits@intel.com>", "list_archive_url": null, "date": "2020-05-05T14:06:38", "name": "[v5] igc: add support to eeprom, registers and link self-tests", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "0e20189a9fa88cdcbd4df9f27f20d7e7cb77cfc6", "submitter": { "id": 76816, "url": "http://patchwork.ozlabs.org/api/people/76816/?format=api", "name": "Lifshits, Vitaly", "email": "vitaly.lifshits@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200505140638.44937-1-vitaly.lifshits@intel.com/mbox/", "series": [ { "id": 174818, "url": "http://patchwork.ozlabs.org/api/series/174818/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=174818", "date": "2020-05-05T14:06:38", "name": "[v5] igc: add support to eeprom, registers and link self-tests", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/174818/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1283660/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1283660/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.136; helo=silver.osuosl.org;\n envelope-from=intel-wired-lan-bounces@osuosl.org; receiver=<UNKNOWN>)", "ozlabs.org;\n dmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 49GhPD4PfSz9sP7\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 6 May 2020 00:07:12 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id B9370240DF;\n\tTue, 5 May 2020 14:07:10 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 4CwthcOsYBVt; Tue, 5 May 2020 14:07:05 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id A39D4248F6;\n\tTue, 5 May 2020 14:07:05 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n by ash.osuosl.org (Postfix) with ESMTP id 3BFE61BF2A5\n for <intel-wired-lan@lists.osuosl.org>; Tue, 5 May 2020 14:07:04 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n by whitealder.osuosl.org (Postfix) with ESMTP id 37CBA87EFD\n for <intel-wired-lan@lists.osuosl.org>; Tue, 5 May 2020 14:07:04 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n with ESMTP id KIlAtAOMfk-j for <intel-wired-lan@lists.osuosl.org>;\n Tue, 5 May 2020 14:06:59 +0000 (UTC)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by whitealder.osuosl.org (Postfix) with ESMTPS id C37CA87E15\n for <intel-wired-lan@lists.osuosl.org>; Tue, 5 May 2020 14:06:59 +0000 (UTC)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 05 May 2020 07:06:45 -0700", "from ccdlinuxdev08.iil.intel.com ([143.185.160.195])\n by fmsmga001.fm.intel.com with ESMTP; 05 May 2020 07:06:43 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "IronPort-SDR": [ "\n QCE5vik2v+fQvZsTqj87QYgRiWg0k8zATj72CtzfrYRd6+MyyVvri1QRGO7rsLPdCfcw6Bmh++\n VFVXLJJDWJIQ==", "\n aHHQxUq9kY/zDacUKVF/eYNmUD6CLlDaglCBQU+bmroSu/haPh8BdE6xwZZ4UZBU1ELarI4NTk\n 1jtF1TefWblQ==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.73,355,1583222400\"; d=\"scan'208\";a=\"369424741\"", "From": "Vitaly Lifshits <vitaly.lifshits@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Tue, 5 May 2020 17:06:38 +0300", "Message-Id": "<20200505140638.44937-1-vitaly.lifshits@intel.com>", "X-Mailer": "git-send-email 2.11.0", "Subject": "[Intel-wired-lan] [PATCH v5] igc: add support to eeprom,\n registers and link self-tests", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Introduced igc_diag.c and igc_diag.h, these files have the\ndiagnostics functionality of igc driver. For the time being\nthese files are being used by ethtool self-test callbacks.\nWhich mean that eeprom, registers and link self-tests for\nethtool were implemented.\n\nSigned-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>\nReported-by: kbuild test robot <lkp@intel.com>\nReported-by: Dan Carpenter <dan.carpenter@oracle.com>\n---\nv2: Fix return 0/1 to boolean value in igc_reg_test function\nv3: Address community comments\nv4: Fix interrupt test and address community comments\nv5: Remove interrupt test in order to avoid kernel panic\n---\n drivers/net/ethernet/intel/igc/Makefile | 2 +-\n drivers/net/ethernet/intel/igc/igc.h | 4 +\n drivers/net/ethernet/intel/igc/igc_diag.c | 186 +++++++++++++++++++++++++++\n drivers/net/ethernet/intel/igc/igc_diag.h | 30 +++++\n drivers/net/ethernet/intel/igc/igc_ethtool.c | 60 +++++++++\n drivers/net/ethernet/intel/igc/igc_main.c | 4 +-\n drivers/net/ethernet/intel/igc/igc_regs.h | 2 +\n 7 files changed, 285 insertions(+), 3 deletions(-)\n create mode 100644 drivers/net/ethernet/intel/igc/igc_diag.c\n create mode 100644 drivers/net/ethernet/intel/igc/igc_diag.h", "diff": "diff --git a/drivers/net/ethernet/intel/igc/Makefile b/drivers/net/ethernet/intel/igc/Makefile\nindex 3652f211f351..1c3051db9085 100644\n--- a/drivers/net/ethernet/intel/igc/Makefile\n+++ b/drivers/net/ethernet/intel/igc/Makefile\n@@ -8,4 +8,4 @@\n obj-$(CONFIG_IGC) += igc.o\n \n igc-objs := igc_main.o igc_mac.o igc_i225.o igc_base.o igc_nvm.o igc_phy.o \\\n-igc_ethtool.o igc_ptp.o igc_dump.o igc_tsn.o\n+igc_diag.o igc_ethtool.o igc_ptp.o igc_dump.o igc_tsn.o\ndiff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h\nindex 8ddc39482a8e..661dc8875f3f 100644\n--- a/drivers/net/ethernet/intel/igc/igc.h\n+++ b/drivers/net/ethernet/intel/igc/igc.h\n@@ -198,6 +198,8 @@ struct igc_adapter {\n \tunsigned long link_check_timeout;\n \tstruct igc_info ei;\n \n+\tu32 test_icr;\n+\n \tstruct ptp_clock *ptp_clock;\n \tstruct ptp_clock_info ptp_caps;\n \tstruct work_struct ptp_tx_work;\n@@ -215,6 +217,8 @@ struct igc_adapter {\n \n void igc_up(struct igc_adapter *adapter);\n void igc_down(struct igc_adapter *adapter);\n+int igc_open(struct net_device *netdev);\n+int igc_close(struct net_device *netdev);\n int igc_setup_tx_resources(struct igc_ring *ring);\n int igc_setup_rx_resources(struct igc_ring *ring);\n void igc_free_tx_resources(struct igc_ring *ring);\ndiff --git a/drivers/net/ethernet/intel/igc/igc_diag.c b/drivers/net/ethernet/intel/igc/igc_diag.c\nnew file mode 100644\nindex 000000000000..1c4536105e56\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/igc/igc_diag.c\n@@ -0,0 +1,186 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2020 Intel Corporation */\n+\n+#include \"igc.h\"\n+#include \"igc_diag.h\"\n+\n+struct igc_reg_test reg_test[] = {\n+\t{ IGC_FCAL,\t1,\tPATTERN_TEST,\t0xFFFFFFFF,\t0xFFFFFFFF },\n+\t{ IGC_FCAH,\t1,\tPATTERN_TEST,\t0x0000FFFF,\t0xFFFFFFFF },\n+\t{ IGC_FCT,\t1,\tPATTERN_TEST,\t0x0000FFFF,\t0xFFFFFFFF },\n+\t{ IGC_RDBAH(0), 4,\tPATTERN_TEST,\t0xFFFFFFFF,\t0xFFFFFFFF },\n+\t{ IGC_RDBAL(0),\t4,\tPATTERN_TEST,\t0xFFFFFF80,\t0xFFFFFF80 },\n+\t{ IGC_RDLEN(0),\t4,\tPATTERN_TEST,\t0x000FFF80,\t0x000FFFFF },\n+\t{ IGC_RDT(0),\t4,\tPATTERN_TEST,\t0x0000FFFF,\t0x0000FFFF },\n+\t{ IGC_FCRTH,\t1,\tPATTERN_TEST,\t0x0003FFF0,\t0x0003FFF0 },\n+\t{ IGC_FCTTV,\t1,\tPATTERN_TEST,\t0x0000FFFF,\t0x0000FFFF },\n+\t{ IGC_TIPG,\t1,\tPATTERN_TEST,\t0x3FFFFFFF,\t0x3FFFFFFF },\n+\t{ IGC_TDBAH(0),\t4,\tPATTERN_TEST,\t0xFFFFFFFF,\t0xFFFFFFFF },\n+\t{ IGC_TDBAL(0),\t4,\tPATTERN_TEST,\t0xFFFFFF80,\t0xFFFFFF80 },\n+\t{ IGC_TDLEN(0),\t4,\tPATTERN_TEST,\t0x000FFF80,\t0x000FFFFF },\n+\t{ IGC_TDT(0),\t4,\tPATTERN_TEST,\t0x0000FFFF,\t0x0000FFFF },\n+\t{ IGC_RCTL,\t1,\tSET_READ_TEST,\t0xFFFFFFFF,\t0x00000000 },\n+\t{ IGC_RCTL,\t1,\tSET_READ_TEST,\t0x04CFB2FE,\t0x003FFFFB },\n+\t{ IGC_RCTL,\t1,\tSET_READ_TEST,\t0x04CFB2FE,\t0xFFFFFFFF },\n+\t{ IGC_TCTL,\t1,\tSET_READ_TEST,\t0xFFFFFFFF,\t0x00000000 },\n+\t{ IGC_RA,\t16,\tTABLE64_TEST_LO,\n+\t\t\t\t\t\t0xFFFFFFFF,\t0xFFFFFFFF },\n+\t{ IGC_RA,\t16,\tTABLE64_TEST_HI,\n+\t\t\t\t\t\t0x900FFFFF,\t0xFFFFFFFF },\n+\t{ IGC_MTA,\t128,\tTABLE32_TEST,\n+\t\t\t\t\t\t0xFFFFFFFF,\t0xFFFFFFFF },\n+\t{ 0, 0, 0, 0}\n+};\n+\n+static bool reg_pattern_test(struct igc_adapter *adapter, u64 *data, int reg,\n+\t\t\t u32 mask, u32 write)\n+{\n+\tstruct igc_hw *hw = &adapter->hw;\n+\tu32 pat, val, before;\n+\tstatic const u32 test_pattern[] = {\n+\t\t0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF\n+\t};\n+\n+\tfor (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {\n+\t\tbefore = rd32(reg);\n+\t\twr32(reg, test_pattern[pat] & write);\n+\t\tval = rd32(reg);\n+\t\tif (val != (test_pattern[pat] & write & mask)) {\n+\t\t\tnetdev_err(adapter->netdev,\n+\t\t\t\t \"pattern test reg %04X failed: got 0x%08X expected 0x%08X\",\n+\t\t\t\t reg, val, test_pattern[pat] & write & mask);\n+\t\t\t*data = reg;\n+\t\t\twr32(reg, before);\n+\t\t\treturn false;\n+\t\t}\n+\t\twr32(reg, before);\n+\t}\n+\treturn true;\n+}\n+\n+static bool reg_set_and_check(struct igc_adapter *adapter, u64 *data, int reg,\n+\t\t\t u32 mask, u32 write)\n+{\n+\tstruct igc_hw *hw = &adapter->hw;\n+\tu32 val, before;\n+\n+\tbefore = rd32(reg);\n+\twr32(reg, write & mask);\n+\tval = rd32(reg);\n+\tif ((write & mask) != (val & mask)) {\n+\t\tnetdev_err(adapter->netdev,\n+\t\t\t \"set/check reg %04X test failed: got 0x%08X expected 0x%08X\",\n+\t\t\t reg, (val & mask), (write & mask));\n+\t\t*data = reg;\n+\t\twr32(reg, before);\n+\t\treturn false;\n+\t}\n+\twr32(reg, before);\n+\treturn true;\n+}\n+\n+bool igc_reg_test(struct igc_adapter *adapter, u64 *data)\n+{\n+\tstruct igc_reg_test *test = reg_test;\n+\tstruct igc_hw *hw = &adapter->hw;\n+\tu32 value, before, after;\n+\tu32 i, toggle, b = false;\n+\n+\t/* Because the status register is such a special case,\n+\t * we handle it separately from the rest of the register\n+\t * tests. Some bits are read-only, some toggle, and some\n+\t * are writeable.\n+\t */\n+\ttoggle = 0x6800D3;\n+\tbefore = rd32(IGC_STATUS);\n+\tvalue = before & toggle;\n+\twr32(IGC_STATUS, toggle);\n+\tafter = rd32(IGC_STATUS) & toggle;\n+\tif (value != after) {\n+\t\tnetdev_err(adapter->netdev,\n+\t\t\t \"failed STATUS register test got: 0x%08X expected: 0x%08X\",\n+\t\t\t after, value);\n+\t\t*data = 1;\n+\t\treturn false;\n+\t}\n+\t/* restore previous status */\n+\twr32(IGC_STATUS, before);\n+\n+\t/* Perform the remainder of the register test, looping through\n+\t * the test table until we either fail or reach the null entry.\n+\t */\n+\twhile (test->reg) {\n+\t\tfor (i = 0; i < test->array_len; i++) {\n+\t\t\tswitch (test->test_type) {\n+\t\t\tcase PATTERN_TEST:\n+\t\t\t\tb = reg_pattern_test(adapter, data,\n+\t\t\t\t\t\t test->reg + (i * 0x40),\n+\t\t\t\t\t\t test->mask,\n+\t\t\t\t\t\t test->write);\n+\t\t\t\tbreak;\n+\t\t\tcase SET_READ_TEST:\n+\t\t\t\tb = reg_set_and_check(adapter, data,\n+\t\t\t\t\t\t test->reg + (i * 0x40),\n+\t\t\t\t\t\t test->mask,\n+\t\t\t\t\t\t test->write);\n+\t\t\t\tbreak;\n+\t\t\tcase TABLE64_TEST_LO:\n+\t\t\t\tb = reg_pattern_test(adapter, data,\n+\t\t\t\t\t\t test->reg + (i * 8),\n+\t\t\t\t\t\t test->mask,\n+\t\t\t\t\t\t test->write);\n+\t\t\t\tbreak;\n+\t\t\tcase TABLE64_TEST_HI:\n+\t\t\t\tb = reg_pattern_test(adapter, data,\n+\t\t\t\t\t\t test->reg + 4 + (i * 8),\n+\t\t\t\t\t\t test->mask,\n+\t\t\t\t\t\t test->write);\n+\t\t\t\tbreak;\n+\t\t\tcase TABLE32_TEST:\n+\t\t\t\tb = reg_pattern_test(adapter, data,\n+\t\t\t\t\t\t test->reg + (i * 4),\n+\t\t\t\t\t\t test->mask,\n+\t\t\t\t\t\t test->write);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (!b)\n+\t\t\t\treturn false;\n+\t\t}\n+\t\ttest++;\n+\t}\n+\t*data = 0;\n+\treturn true;\n+}\n+\n+bool igc_eeprom_test(struct igc_adapter *adapter, u64 *data)\n+{\n+\tstruct igc_hw *hw = &adapter->hw;\n+\n+\t*data = 0;\n+\n+\tif (hw->nvm.ops.validate(hw) != IGC_SUCCESS) {\n+\t\t*data = 1;\n+\t\treturn false;\n+\t}\n+\n+\treturn true;\n+}\n+\n+bool igc_link_test(struct igc_adapter *adapter, u64 *data)\n+{\n+\tbool link_up;\n+\n+\t*data = 0;\n+\n+\t/* add delay to give enough time for autonegotioation to finish */\n+\tif (adapter->hw.mac.autoneg)\n+\t\tssleep(5);\n+\n+\tlink_up = igc_has_link(adapter);\n+\tif (!link_up) {\n+\t\t*data = 1;\n+\t\treturn false;\n+\t}\n+\n+\treturn true;\n+}\ndiff --git a/drivers/net/ethernet/intel/igc/igc_diag.h b/drivers/net/ethernet/intel/igc/igc_diag.h\nnew file mode 100644\nindex 000000000000..600658e33bec\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/igc/igc_diag.h\n@@ -0,0 +1,30 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2020 Intel Corporation */\n+\n+bool igc_reg_test(struct igc_adapter *adapter, u64 *data);\n+bool igc_eeprom_test(struct igc_adapter *adapter, u64 *data);\n+bool igc_link_test(struct igc_adapter *adapter, u64 *data);\n+\n+struct igc_reg_test {\n+\tu16 reg;\n+\tu8 array_len;\n+\tu8 test_type;\n+\tu32 mask;\n+\tu32 write;\n+};\n+\n+/* In the hardware, registers are laid out either singly, in arrays\n+ * spaced 0x40 bytes apart, or in contiguous tables. We assume\n+ * most tests take place on arrays or single registers (handled\n+ * as a single-element array) and special-case the tables.\n+ * Table tests are always pattern tests.\n+ *\n+ * We also make provision for some required setup steps by specifying\n+ * registers to be written without any read-back testing.\n+ */\n+\n+#define PATTERN_TEST\t1\n+#define SET_READ_TEST\t2\n+#define TABLE32_TEST\t3\n+#define TABLE64_TEST_LO\t4\n+#define TABLE64_TEST_HI\t5\ndiff --git a/drivers/net/ethernet/intel/igc/igc_ethtool.c b/drivers/net/ethernet/intel/igc/igc_ethtool.c\nindex 0a8c4a7412a4..9fc250cdf88c 100644\n--- a/drivers/net/ethernet/intel/igc/igc_ethtool.c\n+++ b/drivers/net/ethernet/intel/igc/igc_ethtool.c\n@@ -6,6 +6,7 @@\n #include <linux/pm_runtime.h>\n \n #include \"igc.h\"\n+#include \"igc_diag.h\"\n \n /* forward declaration */\n struct igc_stats {\n@@ -1896,6 +1897,64 @@ static int igc_set_link_ksettings(struct net_device *netdev,\n \treturn 0;\n }\n \n+static void igc_diag_test(struct net_device *netdev,\n+\t\t\t struct ethtool_test *eth_test, u64 *data)\n+{\n+\tstruct igc_adapter *adapter = netdev_priv(netdev);\n+\tbool if_running = netif_running(netdev);\n+\n+\tif (eth_test->flags == ETH_TEST_FL_OFFLINE) {\n+\t\tnetdev_info(adapter->netdev, \"offline testing starting\");\n+\t\tset_bit(__IGC_TESTING, &adapter->state);\n+\n+\t\t/* Link test performed before hardware reset so autoneg doesn't\n+\t\t * interfere with test result\n+\t\t */\n+\t\tif (!igc_link_test(adapter, &data[TEST_LINK]))\n+\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n+\n+\t\tif (if_running)\n+\t\t\tigc_close(netdev);\n+\t\telse\n+\t\t\tigc_reset(adapter);\n+\n+\t\tnetdev_info(adapter->netdev, \"register testing starting\");\n+\t\tif (!igc_reg_test(adapter, &data[TEST_REG]))\n+\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n+\n+\t\tigc_reset(adapter);\n+\n+\t\tnetdev_info(adapter->netdev, \"eeprom testing starting\");\n+\t\tif (!igc_eeprom_test(adapter, &data[TEST_EEP]))\n+\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n+\n+\t\tigc_reset(adapter);\n+\n+\t\t/* loopback and interrupt tests\n+\t\t * will be implemented in the future\n+\t\t */\n+\t\tdata[TEST_LOOP] = 0;\n+\t\tdata[TEST_IRQ] = 0;\n+\n+\t\tclear_bit(__IGC_TESTING, &adapter->state);\n+\t\tif (if_running)\n+\t\t\tigc_open(netdev);\n+\t} else {\n+\t\tnetdev_info(adapter->netdev, \"online testing starting\");\n+\n+\t\t/* register, eeprom, intr and loopback tests not run online */\n+\t\tdata[TEST_REG] = 0;\n+\t\tdata[TEST_EEP] = 0;\n+\t\tdata[TEST_IRQ] = 0;\n+\t\tdata[TEST_LOOP] = 0;\n+\n+\t\tif (!igc_link_test(adapter, &data[TEST_LINK]))\n+\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n+\t}\n+\n+\tmsleep_interruptible(4 * 1000);\n+}\n+\n static const struct ethtool_ops igc_ethtool_ops = {\n \t.supported_coalesce_params = ETHTOOL_COALESCE_USECS,\n \t.get_drvinfo\t\t= igc_get_drvinfo,\n@@ -1933,6 +1992,7 @@ static const struct ethtool_ops igc_ethtool_ops = {\n \t.complete\t\t= igc_ethtool_complete,\n \t.get_link_ksettings\t= igc_get_link_ksettings,\n \t.set_link_ksettings\t= igc_set_link_ksettings,\n+\t.self_test\t\t= igc_diag_test,\n };\n \n void igc_set_ethtool_ops(struct net_device *netdev)\ndiff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c\nindex 3c1c41577233..7b0d04788cf0 100644\n--- a/drivers/net/ethernet/intel/igc/igc_main.c\n+++ b/drivers/net/ethernet/intel/igc/igc_main.c\n@@ -4389,7 +4389,7 @@ static int __igc_open(struct net_device *netdev, bool resuming)\n \treturn err;\n }\n \n-static int igc_open(struct net_device *netdev)\n+int igc_open(struct net_device *netdev)\n {\n \treturn __igc_open(netdev, false);\n }\n@@ -4431,7 +4431,7 @@ static int __igc_close(struct net_device *netdev, bool suspending)\n \treturn 0;\n }\n \n-static int igc_close(struct net_device *netdev)\n+int igc_close(struct net_device *netdev)\n {\n \tif (netif_device_present(netdev) || netdev->dismantle)\n \t\treturn __igc_close(netdev, false);\ndiff --git a/drivers/net/ethernet/intel/igc/igc_regs.h b/drivers/net/ethernet/intel/igc/igc_regs.h\nindex 6093cde2351c..633545977a65 100644\n--- a/drivers/net/ethernet/intel/igc/igc_regs.h\n+++ b/drivers/net/ethernet/intel/igc/igc_regs.h\n@@ -49,6 +49,7 @@\n #define IGC_FACTPS\t\t0x05B30\n \n /* Interrupt Register Description */\n+#define IGC_EICR\t\t0x01580 /* Ext. Interrupt Cause read - W0 */\n #define IGC_EICS\t\t0x01520 /* Ext. Interrupt Cause Set - W0 */\n #define IGC_EIMS\t\t0x01524 /* Ext. Interrupt Mask Set/Read - RW */\n #define IGC_EIMC\t\t0x01528 /* Ext. Interrupt Mask Clear - WO */\n@@ -119,6 +120,7 @@\n #define IGC_RLPML\t\t0x05004 /* Rx Long Packet Max Length */\n #define IGC_RFCTL\t\t0x05008 /* Receive Filter Control*/\n #define IGC_MTA\t\t\t0x05200 /* Multicast Table Array - RW Array */\n+#define IGC_RA\t\t\t0x05400 /* Receive Address - RW Array */\n #define IGC_UTA\t\t\t0x0A000 /* Unicast Table Array - RW */\n #define IGC_RAL(_n)\t\t(0x05400 + ((_n) * 0x08))\n #define IGC_RAH(_n)\t\t(0x05404 + ((_n) * 0x08))\n", "prefixes": [ "v5" ] }