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GET /api/patches/1266535/?format=api
{ "id": 1266535, "url": "http://patchwork.ozlabs.org/api/patches/1266535/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200405121604.36654-1-vitaly.lifshits@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20200405121604.36654-1-vitaly.lifshits@intel.com>", "list_archive_url": null, "date": "2020-04-05T12:16:04", "name": "[v4] igc: add support to interrupt, eeprom, registers and link self-tests", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "f3b80b021f8c80d472bc6bf78944f4529416a9ad", "submitter": { "id": 76816, "url": "http://patchwork.ozlabs.org/api/people/76816/?format=api", "name": "Lifshits, Vitaly", "email": "vitaly.lifshits@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200405121604.36654-1-vitaly.lifshits@intel.com/mbox/", "series": [ { "id": 168651, "url": "http://patchwork.ozlabs.org/api/series/168651/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=168651", "date": "2020-04-05T12:16:04", "name": "[v4] igc: add support to interrupt, eeprom, registers and link self-tests", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/168651/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1266535/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1266535/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@osuosl.org" ], "Authentication-Results": [ "ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=osuosl.org (client-ip=140.211.166.137;\n\thelo=fraxinus.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 48wCM53mWdz9sR4\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSun, 5 Apr 2020 22:16:16 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 8E86B85E9F;\n\tSun, 5 Apr 2020 12:16:14 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id riOy-_75u1Nh; Sun, 5 Apr 2020 12:16:12 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id E68DC85E8A;\n\tSun, 5 Apr 2020 12:16:12 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 97D591BF3C0\n\tfor <intel-wired-lan@osuosl.org>;\n\tSun, 5 Apr 2020 12:16:11 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 92CB820492\n\tfor <intel-wired-lan@osuosl.org>;\n\tSun, 5 Apr 2020 12:16:11 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id g8Xkx24QXitL for <intel-wired-lan@osuosl.org>;\n\tSun, 5 Apr 2020 12:16:09 +0000 (UTC)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n\tby silver.osuosl.org (Postfix) with ESMTPS id 518F620355\n\tfor <intel-wired-lan@osuosl.org>;\n\tSun, 5 Apr 2020 12:16:09 +0000 (UTC)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; \n\t05 Apr 2020 05:16:08 -0700", "from ccdlinuxdev08.iil.intel.com ([143.185.160.195])\n\tby orsmga002.jf.intel.com with ESMTP; 05 Apr 2020 05:16:06 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "IronPort-SDR": [ "3LboZAaoUOeyry7EuavNN7tIgwwJx2sa46Fgt/TyKUFN/52Ox6Hr75pT3veiQsEwaMssTOSmVT\n\t3PTnDw78lAqw==", "DS3an+GZBDJnzhfoK9DqFOJOY0ko8fknyzMffC8QEz2Uag5rQ+rbMlOGDjCzGyxfjtpb0ms5S9\n\tGWEeCCnwYk7A==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.72,347,1580803200\"; d=\"scan'208\";a=\"268813609\"", "From": "Vitaly Lifshits <vitaly.lifshits@intel.com>", "To": "intel-wired-lan@osuosl.org", "Date": "Sun, 5 Apr 2020 15:16:04 +0300", "Message-Id": "<20200405121604.36654-1-vitaly.lifshits@intel.com>", "X-Mailer": "git-send-email 2.11.0", "Subject": "[Intel-wired-lan] [PATCH v4] igc: add support to interrupt, eeprom, \n\tregisters and link self-tests", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Introduced igc_diag.c and igc_diag.h, these files have the\ndiagnostics functionality of igc driver. For the time being\nthese files are being used by ethtool self-test callbacks.\nWhich mean that interrupt, eeprom, registers and link self-tests for\nethtool were implemented.\n\nSigned-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>\nReported-by: kbuild test robot <lkp@intel.com>\nReported-by: Dan Carpenter <dan.carpenter@oracle.com>\n---\nv2: Fix return 0/1 to boolean value in igc_reg_test function\nv3: Address community comments\nv4: Fix interrupt test and address community comments\n---\n drivers/net/ethernet/intel/igc/Makefile | 2 +-\n drivers/net/ethernet/intel/igc/igc.h | 4 +\n drivers/net/ethernet/intel/igc/igc_diag.c | 336 +++++++++++++++++++++++++++\n drivers/net/ethernet/intel/igc/igc_diag.h | 37 +++\n drivers/net/ethernet/intel/igc/igc_ethtool.c | 63 +++++\n drivers/net/ethernet/intel/igc/igc_main.c | 4 +-\n drivers/net/ethernet/intel/igc/igc_regs.h | 2 +\n 7 files changed, 445 insertions(+), 3 deletions(-)\n create mode 100644 drivers/net/ethernet/intel/igc/igc_diag.c\n create mode 100644 drivers/net/ethernet/intel/igc/igc_diag.h", "diff": "diff --git a/drivers/net/ethernet/intel/igc/Makefile b/drivers/net/ethernet/intel/igc/Makefile\nindex 3652f211f351..1c3051db9085 100644\n--- a/drivers/net/ethernet/intel/igc/Makefile\n+++ b/drivers/net/ethernet/intel/igc/Makefile\n@@ -8,4 +8,4 @@\n obj-$(CONFIG_IGC) += igc.o\n \n igc-objs := igc_main.o igc_mac.o igc_i225.o igc_base.o igc_nvm.o igc_phy.o \\\n-igc_ethtool.o igc_ptp.o igc_dump.o igc_tsn.o\n+igc_diag.o igc_ethtool.o igc_ptp.o igc_dump.o igc_tsn.o\ndiff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h\nindex 8098acef4316..6c18c74a68fb 100644\n--- a/drivers/net/ethernet/intel/igc/igc.h\n+++ b/drivers/net/ethernet/intel/igc/igc.h\n@@ -198,6 +198,8 @@ struct igc_adapter {\n \tunsigned long link_check_timeout;\n \tstruct igc_info ei;\n \n+\tu32 test_icr;\n+\n \tstruct ptp_clock *ptp_clock;\n \tstruct ptp_clock_info ptp_caps;\n \tstruct work_struct ptp_tx_work;\n@@ -215,6 +217,8 @@ struct igc_adapter {\n \n void igc_up(struct igc_adapter *adapter);\n void igc_down(struct igc_adapter *adapter);\n+int igc_open(struct net_device *netdev);\n+int igc_close(struct net_device *netdev);\n int igc_setup_tx_resources(struct igc_ring *ring);\n int igc_setup_rx_resources(struct igc_ring *ring);\n void igc_free_tx_resources(struct igc_ring *ring);\ndiff --git a/drivers/net/ethernet/intel/igc/igc_diag.c b/drivers/net/ethernet/intel/igc/igc_diag.c\nnew file mode 100644\nindex 000000000000..32675020a3d2\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/igc/igc_diag.c\n@@ -0,0 +1,336 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2020 Intel Corporation */\n+\n+#include \"igc.h\"\n+#include \"igc_diag.h\"\n+\n+struct igc_reg_test reg_test[] = {\n+\t{ IGC_FCAL,\t1,\tPATTERN_TEST,\t0xFFFFFFFF,\t0xFFFFFFFF },\n+\t{ IGC_FCAH,\t1,\tPATTERN_TEST,\t0x0000FFFF,\t0xFFFFFFFF },\n+\t{ IGC_FCT,\t1,\tPATTERN_TEST,\t0x0000FFFF,\t0xFFFFFFFF },\n+\t{ IGC_RDBAH(0), 4,\tPATTERN_TEST,\t0xFFFFFFFF,\t0xFFFFFFFF },\n+\t{ IGC_RDBAL(0),\t4,\tPATTERN_TEST,\t0xFFFFFF80,\t0xFFFFFF80 },\n+\t{ IGC_RDLEN(0),\t4,\tPATTERN_TEST,\t0x000FFF80,\t0x000FFFFF },\n+\t{ IGC_RDT(0),\t4,\tPATTERN_TEST,\t0x0000FFFF,\t0x0000FFFF },\n+\t{ IGC_FCRTH,\t1,\tPATTERN_TEST,\t0x0003FFF0,\t0x0003FFF0 },\n+\t{ IGC_FCTTV,\t1,\tPATTERN_TEST,\t0x0000FFFF,\t0x0000FFFF },\n+\t{ IGC_TIPG,\t1,\tPATTERN_TEST,\t0x3FFFFFFF,\t0x3FFFFFFF },\n+\t{ IGC_TDBAH(0),\t4,\tPATTERN_TEST,\t0xFFFFFFFF, 0xFFFFFFFF },\n+\t{ IGC_TDBAL(0),\t4,\tPATTERN_TEST,\t0xFFFFFF80, 0xFFFFFF80 },\n+\t{ IGC_TDLEN(0),\t4,\tPATTERN_TEST,\t0x000FFF80, 0x000FFFFF },\n+\t{ IGC_TDT(0),\t4,\tPATTERN_TEST,\t0x0000FFFF, 0x0000FFFF },\n+\t{ IGC_RCTL,\t1,\tSET_READ_TEST,\t0xFFFFFFFF,\t0x00000000 },\n+\t{ IGC_RCTL,\t1,\tSET_READ_TEST,\t0x04CFB2FE,\t0x003FFFFB },\n+\t{ IGC_RCTL,\t1,\tSET_READ_TEST,\t0x04CFB2FE,\t0xFFFFFFFF },\n+\t{ IGC_TCTL,\t1,\tSET_READ_TEST,\t0xFFFFFFFF,\t0x00000000 },\n+\t{ IGC_RA,\t16,\tTABLE64_TEST_LO,\n+\t\t\t\t\t\t0xFFFFFFFF,\t0xFFFFFFFF },\n+\t{ IGC_RA,\t16,\tTABLE64_TEST_HI,\n+\t\t\t\t\t\t0x900FFFFF,\t0xFFFFFFFF },\n+\t{ IGC_MTA,\t128,\tTABLE32_TEST,\n+\t\t\t\t\t\t0xFFFFFFFF,\t0xFFFFFFFF },\n+\t{ 0, 0, 0, 0}\n+};\n+\n+static bool reg_pattern_test(struct igc_adapter *adapter, u64 *data, int reg,\n+\t\t\t u32 mask, u32 write)\n+{\n+\tstruct igc_hw *hw = &adapter->hw;\n+\tu32 pat, val, before;\n+\tstatic const u32 test_pattern[] = {\n+\t\t0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF\n+\t};\n+\n+\tfor (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {\n+\t\tbefore = rd32(reg);\n+\t\twr32(reg, test_pattern[pat] & write);\n+\t\tval = rd32(reg);\n+\t\tif (val != (test_pattern[pat] & write & mask)) {\n+\t\t\tnetdev_err(adapter->netdev,\n+\t\t\t\t \"pattern test reg %04X failed: got 0x%08X expected 0x%08X\",\n+\t\t\t\t reg, val, test_pattern[pat] & write & mask);\n+\t\t\t*data = reg;\n+\t\t\twr32(reg, before);\n+\t\t\treturn false;\n+\t\t}\n+\t\twr32(reg, before);\n+\t}\n+\treturn true;\n+}\n+\n+static bool reg_set_and_check(struct igc_adapter *adapter, u64 *data, int reg,\n+\t\t\t u32 mask, u32 write)\n+{\n+\tstruct igc_hw *hw = &adapter->hw;\n+\tu32 val, before;\n+\n+\tbefore = rd32(reg);\n+\twr32(reg, write & mask);\n+\tval = rd32(reg);\n+\tif ((write & mask) != (val & mask)) {\n+\t\tnetdev_err(adapter->netdev,\n+\t\t\t \"set/check reg %04X test failed: got 0x%08X expected 0x%08X\",\n+\t\t\t reg, (val & mask), (write & mask));\n+\t\t*data = reg;\n+\t\twr32(reg, before);\n+\t\treturn false;\n+\t}\n+\twr32(reg, before);\n+\treturn true;\n+}\n+\n+bool igc_reg_test(struct igc_adapter *adapter, u64 *data)\n+{\n+\tstruct igc_reg_test *test = reg_test;\n+\tstruct igc_hw *hw = &adapter->hw;\n+\tu32 value, before, after;\n+\tu32 i, toggle, b = false;\n+\n+\t/* Because the status register is such a special case,\n+\t * we handle it separately from the rest of the register\n+\t * tests. Some bits are read-only, some toggle, and some\n+\t * are writeable.\n+\t */\n+\ttoggle = 0x6800D3;\n+\tbefore = rd32(IGC_STATUS);\n+\tvalue = before & toggle;\n+\twr32(IGC_STATUS, toggle);\n+\tafter = rd32(IGC_STATUS) & toggle;\n+\tif (value != after) {\n+\t\tnetdev_err(adapter->netdev,\n+\t\t\t \"failed STATUS register test got: 0x%08X expected: 0x%08X\",\n+\t\t\t after, value);\n+\t\t*data = 1;\n+\t\treturn false;\n+\t}\n+\t/* restore previous status */\n+\twr32(IGC_STATUS, before);\n+\n+\t/* Perform the remainder of the register test, looping through\n+\t * the test table until we either fail or reach the null entry.\n+\t */\n+\twhile (test->reg) {\n+\t\tfor (i = 0; i < test->array_len; i++) {\n+\t\t\tswitch (test->test_type) {\n+\t\t\tcase PATTERN_TEST:\n+\t\t\t\tb = reg_pattern_test(adapter, data,\n+\t\t\t\t\t\t test->reg + (i * 0x40),\n+\t\t\t\t\t\t test->mask,\n+\t\t\t\t\t\t test->write);\n+\t\t\t\tbreak;\n+\t\t\tcase SET_READ_TEST:\n+\t\t\t\tb = reg_set_and_check(adapter, data,\n+\t\t\t\t\t\t test->reg + (i * 0x40),\n+\t\t\t\t\t\t test->mask,\n+\t\t\t\t\t\t test->write);\n+\t\t\t\tbreak;\n+\t\t\tcase TABLE64_TEST_LO:\n+\t\t\t\tb = reg_pattern_test(adapter, data,\n+\t\t\t\t\t\t test->reg + (i * 8),\n+\t\t\t\t\t\t test->mask,\n+\t\t\t\t\t\t test->write);\n+\t\t\t\tbreak;\n+\t\t\tcase TABLE64_TEST_HI:\n+\t\t\t\tb = reg_pattern_test(adapter, data,\n+\t\t\t\t\t\t test->reg + 4 + (i * 8),\n+\t\t\t\t\t\t test->mask,\n+\t\t\t\t\t\t test->write);\n+\t\t\t\tbreak;\n+\t\t\tcase TABLE32_TEST:\n+\t\t\t\tb = reg_pattern_test(adapter, data,\n+\t\t\t\t\t\t test->reg + (i * 4),\n+\t\t\t\t\t\t test->mask,\n+\t\t\t\t\t\t test->write);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (!b)\n+\t\t\t\treturn false;\n+\t\t}\n+\t\ttest++;\n+\t}\n+\t*data = 0;\n+\treturn true;\n+}\n+\n+bool igc_eeprom_test(struct igc_adapter *adapter, u64 *data)\n+{\n+\tstruct igc_hw *hw = &adapter->hw;\n+\n+\t*data = 0;\n+\n+\tif (hw->nvm.ops.validate(hw) != IGC_SUCCESS) {\n+\t\t*data = 1;\n+\t\treturn false;\n+\t}\n+\n+\treturn true;\n+}\n+\n+static irqreturn_t igc_test_intr(int irq, void *data)\n+{\n+\tstruct igc_adapter *adapter = (struct igc_adapter *)data;\n+\tstruct igc_hw *hw = &adapter->hw;\n+\n+\tadapter->test_icr |= rd32(IGC_ICR);\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static irqreturn_t igc_test_intr_msix(int irq, void *data)\n+{\n+\tstruct igc_adapter *adapter = (struct igc_adapter *)data;\n+\tstruct igc_hw *hw = &adapter->hw;\n+\n+\tadapter->test_icr |= rd32(IGC_EICR);\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+bool igc_intr_test(struct igc_adapter *adapter, u64 *data)\n+{\n+\tstruct igc_hw *hw = &adapter->hw;\n+\tstruct net_device *netdev = adapter->netdev;\n+\tu32 mask, ics_mask = IGC_ICS_MASK_OTHER, i = 0, shared_int = true;\n+\tu32 irq = adapter->pdev->irq;\n+\n+\t*data = 0;\n+\n+\t/* Hook up test interrupt handler just for this test */\n+\tif (adapter->msix_entries) {\n+\t\tif (request_irq(adapter->msix_entries[0].vector,\n+\t\t\t\t&igc_test_intr_msix, 0,\n+\t\t\t\tnetdev->name, adapter)) {\n+\t\t\t*data = 1;\n+\t\t\treturn false;\n+\t\t}\n+\t\tics_mask = IGC_ICS_MASK_MSIX;\n+\t} else if (adapter->flags & IGC_FLAG_HAS_MSI) {\n+\t\tshared_int = false;\n+\t\tif (request_irq(irq,\n+\t\t\t\tigc_test_intr, 0, netdev->name, adapter)) {\n+\t\t\t*data = 1;\n+\t\t\treturn false;\n+\t\t}\n+\t} else if (!request_irq(irq, igc_test_intr, IRQF_PROBE_SHARED,\n+\t\t\t\tnetdev->name, adapter)) {\n+\t\tshared_int = false;\n+\t} else if (request_irq(irq, &igc_test_intr, IRQF_SHARED,\n+\t\t netdev->name, adapter)) {\n+\t\t*data = 1;\n+\t\treturn false;\n+\t}\n+\tnetdev_info(adapter->netdev, \"testing %s interrupt\",\n+\t\t (shared_int ? \"shared\" : \"unshared\"));\n+\n+\t/* Disable all the interrupts */\n+\twr32(IGC_IMC, ~0);\n+\twr32(IGC_EIMC, ~0);\n+\twrfl();\n+\tusleep_range(10000, 20000);\n+\n+\t/* Test each interrupt */\n+\tfor (; i < 31; i++) {\n+\t\t/* Interrupt to test */\n+\t\tmask = BIT(i);\n+\n+\t\tif (!(mask & ics_mask))\n+\t\t\tcontinue;\n+\n+\t\tif (!shared_int) {\n+\t\t\t/* Disable the interrupt to be reported in\n+\t\t\t * the cause register and then force the same\n+\t\t\t * interrupt and see if one gets posted. If\n+\t\t\t * an interrupt was posted to the bus, the\n+\t\t\t * test failed.\n+\t\t\t */\n+\t\t\tadapter->test_icr = 0;\n+\n+\t\t\t/* Flush any pending interrupts */\n+\t\t\twr32(IGC_ICR, ~0);\n+\n+\t\t\twr32(IGC_IMC, mask);\n+\t\t\twr32(IGC_ICS, mask);\n+\t\t\twrfl();\n+\t\t\tusleep_range(10000, 20000);\n+\n+\t\t\tif (adapter->test_icr & mask) {\n+\t\t\t\t*data = 3;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Enable the interrupt to be reported in\n+\t\t * the cause register and then force the same\n+\t\t * interrupt and see if one gets posted. If\n+\t\t * an interrupt was not posted to the bus, the\n+\t\t * test failed.\n+\t\t */\n+\t\tadapter->test_icr = 0;\n+\n+\t\twr32(IGC_EIMS, mask);\n+\t\twr32(IGC_EICS, mask);\n+\t\twrfl();\n+\t\tusleep_range(10000, 20000);\n+\n+\t\tif (!(adapter->test_icr & mask)) {\n+\t\t\t*data = 4;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (!shared_int) {\n+\t\t\t/* Disable the other interrupts to be reported in\n+\t\t\t * the cause register and then force the other\n+\t\t\t * interrupts and see if any get posted. If\n+\t\t\t * an interrupt was posted to the bus, the\n+\t\t\t * test failed.\n+\t\t\t */\n+\t\t\tadapter->test_icr = 0;\n+\n+\t\t\t/* Flush any pending interrupts */\n+\t\t\twr32(IGC_ICR, ~0);\n+\n+\t\t\twr32(IGC_IMC, ~mask);\n+\t\t\twr32(IGC_ICS, ~mask);\n+\t\t\twrfl();\n+\t\t\tusleep_range(10000, 20000);\n+\n+\t\t\tif (adapter->test_icr & mask) {\n+\t\t\t\t*data = 5;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/* Disable all the interrupts */\n+\twr32(IGC_EIMC, ~0);\n+\twr32(IGC_IMC, ~0);\n+\twrfl();\n+\tusleep_range(10000, 20000);\n+\n+\t/* Unhook test interrupt handler */\n+\tif (adapter->msix_entries)\n+\t\tfree_irq(adapter->msix_entries[0].vector, adapter);\n+\telse\n+\t\tfree_irq(irq, adapter);\n+\n+\treturn true;\n+}\n+\n+bool igc_link_test(struct igc_adapter *adapter, u64 *data)\n+{\n+\tbool link_up;\n+\n+\t*data = 0;\n+\n+\t/* add delay to give enough time for autonegotioation to finish */\n+\tif (adapter->hw.mac.autoneg)\n+\t\tssleep(5);\n+\n+\tlink_up = igc_has_link(adapter);\n+\tif (!link_up) {\n+\t\t*data = 1;\n+\t\treturn false;\n+\t}\n+\n+\treturn true;\n+}\ndiff --git a/drivers/net/ethernet/intel/igc/igc_diag.h b/drivers/net/ethernet/intel/igc/igc_diag.h\nnew file mode 100644\nindex 000000000000..3cffaad01d50\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/igc/igc_diag.h\n@@ -0,0 +1,37 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2020 Intel Corporation */\n+\n+bool igc_reg_test(struct igc_adapter *adapter, u64 *data);\n+bool igc_eeprom_test(struct igc_adapter *adapter, u64 *data);\n+bool igc_intr_test(struct igc_adapter *adapter, u64 *data);\n+bool igc_link_test(struct igc_adapter *adapter, u64 *data);\n+\n+struct igc_reg_test {\n+\tu16 reg;\n+\tu8 array_len;\n+\tu8 test_type;\n+\tu32 mask;\n+\tu32 write;\n+};\n+\n+/* In the hardware, registers are laid out either singly, in arrays\n+ * spaced 0x40 bytes apart, or in contiguous tables. We assume\n+ * most tests take place on arrays or single registers (handled\n+ * as a single-element array) and special-case the tables.\n+ * Table tests are always pattern tests.\n+ *\n+ * We also make provision for some required setup steps by specifying\n+ * registers to be written without any read-back testing.\n+ */\n+\n+#define PATTERN_TEST\t1\n+#define SET_READ_TEST\t2\n+#define TABLE32_TEST\t3\n+#define TABLE64_TEST_LO\t4\n+#define TABLE64_TEST_HI\t5\n+\n+/* For interrupt test we are using different registers\n+ * and masks for msi-x interrupts and the other methods\n+ */\n+#define IGC_ICS_MASK_OTHER\t0x774CFED5\n+#define IGC_ICS_MASK_MSIX\t0xF\ndiff --git a/drivers/net/ethernet/intel/igc/igc_ethtool.c b/drivers/net/ethernet/intel/igc/igc_ethtool.c\nindex 0a8c4a7412a4..c14196663ebb 100644\n--- a/drivers/net/ethernet/intel/igc/igc_ethtool.c\n+++ b/drivers/net/ethernet/intel/igc/igc_ethtool.c\n@@ -6,6 +6,7 @@\n #include <linux/pm_runtime.h>\n \n #include \"igc.h\"\n+#include \"igc_diag.h\"\n \n /* forward declaration */\n struct igc_stats {\n@@ -1896,6 +1897,67 @@ static int igc_set_link_ksettings(struct net_device *netdev,\n \treturn 0;\n }\n \n+static void igc_diag_test(struct net_device *netdev,\n+\t\t\t struct ethtool_test *eth_test, u64 *data)\n+{\n+\tstruct igc_adapter *adapter = netdev_priv(netdev);\n+\tbool if_running = netif_running(netdev);\n+\n+\tif (eth_test->flags == ETH_TEST_FL_OFFLINE) {\n+\t\tnetdev_info(adapter->netdev, \"offline testing starting\");\n+\t\tset_bit(__IGC_TESTING, &adapter->state);\n+\n+\t\t/* Link test performed before hardware reset so autoneg doesn't\n+\t\t * interfere with test result\n+\t\t */\n+\t\tif (!igc_link_test(adapter, &data[TEST_LINK]))\n+\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n+\n+\t\tif (if_running)\n+\t\t\tigc_close(netdev);\n+\t\telse\n+\t\t\tigc_reset(adapter);\n+\n+\t\tnetdev_info(adapter->netdev, \"register testing starting\");\n+\t\tif (!igc_reg_test(adapter, &data[TEST_REG]))\n+\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n+\n+\t\tigc_reset(adapter);\n+\n+\t\tnetdev_info(adapter->netdev, \"eeprom testing starting\");\n+\t\tif (!igc_eeprom_test(adapter, &data[TEST_EEP]))\n+\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n+\n+\t\tigc_reset(adapter);\n+\n+\t\tnetdev_info(adapter->netdev, \"interrupt testing starting\");\n+\t\tif (!igc_intr_test(adapter, &data[TEST_IRQ]))\n+\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n+\n+\t\tigc_reset(adapter);\n+\n+\t\t/* loopback test will be implemented in the future */\n+\t\tdata[TEST_LOOP] = 0;\n+\n+\t\tclear_bit(__IGC_TESTING, &adapter->state);\n+\t\tif (if_running)\n+\t\t\tigc_open(netdev);\n+\t} else {\n+\t\tnetdev_info(adapter->netdev, \"online testing starting\");\n+\n+\t\t/* register, eeprom, intr and loopback tests not run online */\n+\t\tdata[TEST_REG] = 0;\n+\t\tdata[TEST_EEP] = 0;\n+\t\tdata[TEST_IRQ] = 0;\n+\t\tdata[TEST_LOOP] = 0;\n+\n+\t\tif (!igc_link_test(adapter, &data[TEST_LINK]))\n+\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n+\t}\n+\n+\tmsleep_interruptible(4 * 1000);\n+}\n+\n static const struct ethtool_ops igc_ethtool_ops = {\n \t.supported_coalesce_params = ETHTOOL_COALESCE_USECS,\n \t.get_drvinfo\t\t= igc_get_drvinfo,\n@@ -1933,6 +1995,7 @@ static const struct ethtool_ops igc_ethtool_ops = {\n \t.complete\t\t= igc_ethtool_complete,\n \t.get_link_ksettings\t= igc_get_link_ksettings,\n \t.set_link_ksettings\t= igc_set_link_ksettings,\n+\t.self_test\t\t= igc_diag_test,\n };\n \n void igc_set_ethtool_ops(struct net_device *netdev)\ndiff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c\nindex f2bd4bb978a1..a605a02c0479 100644\n--- a/drivers/net/ethernet/intel/igc/igc_main.c\n+++ b/drivers/net/ethernet/intel/igc/igc_main.c\n@@ -4389,7 +4389,7 @@ static int __igc_open(struct net_device *netdev, bool resuming)\n \treturn err;\n }\n \n-static int igc_open(struct net_device *netdev)\n+int igc_open(struct net_device *netdev)\n {\n \treturn __igc_open(netdev, false);\n }\n@@ -4431,7 +4431,7 @@ static int __igc_close(struct net_device *netdev, bool suspending)\n \treturn 0;\n }\n \n-static int igc_close(struct net_device *netdev)\n+int igc_close(struct net_device *netdev)\n {\n \tif (netif_device_present(netdev) || netdev->dismantle)\n \t\treturn __igc_close(netdev, false);\ndiff --git a/drivers/net/ethernet/intel/igc/igc_regs.h b/drivers/net/ethernet/intel/igc/igc_regs.h\nindex 96dee3c1a5f7..ffb2f59ec434 100644\n--- a/drivers/net/ethernet/intel/igc/igc_regs.h\n+++ b/drivers/net/ethernet/intel/igc/igc_regs.h\n@@ -49,6 +49,7 @@\n #define IGC_FACTPS\t\t0x05B30\n \n /* Interrupt Register Description */\n+#define IGC_EICR\t\t0x01580 /* Ext. Interrupt Cause read - W0 */\n #define IGC_EICS\t\t0x01520 /* Ext. Interrupt Cause Set - W0 */\n #define IGC_EIMS\t\t0x01524 /* Ext. Interrupt Mask Set/Read - RW */\n #define IGC_EIMC\t\t0x01528 /* Ext. Interrupt Mask Clear - WO */\n@@ -119,6 +120,7 @@\n #define IGC_RLPML\t\t0x05004 /* Rx Long Packet Max Length */\n #define IGC_RFCTL\t\t0x05008 /* Receive Filter Control*/\n #define IGC_MTA\t\t\t0x05200 /* Multicast Table Array - RW Array */\n+#define IGC_RA\t\t\t0x05400 /* Receive Address - RW Array */\n #define IGC_UTA\t\t\t0x0A000 /* Unicast Table Array - RW */\n #define IGC_RAL(_n)\t\t(0x05400 + ((_n) * 0x08))\n #define IGC_RAH(_n)\t\t(0x05404 + ((_n) * 0x08))\n", "prefixes": [ "v4" ] }