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{
    "id": 1256983,
    "url": "http://patchwork.ozlabs.org/api/patches/1256983/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/8bd05d664cec0b4d72ee8f31b77d3f12b90e27a0.1584088476.git.jack.ping.chng@linux.intel.com/",
    "project": {
        "id": 46,
        "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api",
        "name": "Intel Wired Ethernet development",
        "link_name": "intel-wired-lan",
        "list_id": "intel-wired-lan.osuosl.org",
        "list_email": "intel-wired-lan@osuosl.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<8bd05d664cec0b4d72ee8f31b77d3f12b90e27a0.1584088476.git.jack.ping.chng@linux.intel.com>",
    "list_archive_url": null,
    "date": "2020-03-13T08:39:43",
    "name": "[next-queue,v3] gwdpa: gswip: Introduce Gigabit Ethernet Switch (GSWIP) device driver",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": false,
    "hash": "ecbbc9c5fc3c8e5d7eba4ba583e42970a89a398f",
    "submitter": {
        "id": 78112,
        "url": "http://patchwork.ozlabs.org/api/people/78112/?format=api",
        "name": "Jack Ping CHNG",
        "email": "jack.ping.chng@linux.intel.com"
    },
    "delegate": {
        "id": 68,
        "url": "http://patchwork.ozlabs.org/api/users/68/?format=api",
        "username": "jtkirshe",
        "first_name": "Jeff",
        "last_name": "Kirsher",
        "email": "jeffrey.t.kirsher@intel.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/8bd05d664cec0b4d72ee8f31b77d3f12b90e27a0.1584088476.git.jack.ping.chng@linux.intel.com/mbox/",
    "series": [
        {
            "id": 164966,
            "url": "http://patchwork.ozlabs.org/api/series/164966/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=164966",
            "date": "2020-03-13T08:39:43",
            "name": "[next-queue,v3] gwdpa: gswip: Introduce Gigabit Ethernet Switch (GSWIP) device driver",
            "version": 3,
            "mbox": "http://patchwork.ozlabs.org/series/164966/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1256983/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1256983/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<intel-wired-lan-bounces@osuosl.org>",
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        "Delivered-To": [
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            "intel-wired-lan@lists.osuosl.org"
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            "from orsmga008.jf.intel.com ([10.7.209.65])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t13 Mar 2020 01:40:03 -0700",
            "from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13])\n\tby orsmga008.jf.intel.com with ESMTP; 13 Mar 2020 01:39:59 -0700"
        ],
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        "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6",
        "X-Amp-Result": "SKIPPED(no attachment in message)",
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        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.70,548,1574150400\"; d=\"scan'208\";a=\"237147961\"",
        "From": "Jack Ping CHNG <jack.ping.chng@linux.intel.com>",
        "To": "intel-wired-lan@lists.osuosl.org",
        "Date": "Fri, 13 Mar 2020 16:39:43 +0800",
        "Message-Id": "<8bd05d664cec0b4d72ee8f31b77d3f12b90e27a0.1584088476.git.jack.ping.chng@linux.intel.com>",
        "X-Mailer": "git-send-email 2.11.0",
        "X-Mailman-Approved-At": "Tue, 17 Mar 2020 22:05:17 +0000",
        "Subject": "[Intel-wired-lan] [next-queue PATCH v3] gwdpa: gswip: Introduce\n\tGigabit Ethernet Switch (GSWIP) device driver",
        "X-BeenThere": "intel-wired-lan@osuosl.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>",
        "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>",
        "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>",
        "List-Post": "<mailto:intel-wired-lan@osuosl.org>",
        "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>",
        "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>",
        "Cc": "cheol.yong.kim@intel.com,\n\tAmireddy Mallikarjuna reddy <mallikarjunax.reddy@linux.intel.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=\"us-ascii\"",
        "Content-Transfer-Encoding": "7bit",
        "Errors-To": "intel-wired-lan-bounces@osuosl.org",
        "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>"
    },
    "content": "This driver enables the Intel's LGM SoC GSWIP block. GSWIP is a core module\ntailored for L2/L3/L4+ data plane and QoS functions. It allows CPUs and\nother accelerators connected to the SoC datapath to enqueue and dequeue\npackets through DMAs. Most configuration values are stored in tables\nsuch as Parsing and Classification Engine tables, Buffer Manager tables\nand Pseudo MAC tables.\n\nSigned-off-by: Jack Ping CHNG <jack.ping.chng@linux.intel.com>\nSigned-off-by: Amireddy Mallikarjuna reddy <mallikarjunax.reddy@linux.intel.com>\n---\nChanges:\n\nv3:\n- Removed redundant err print for platform_get_irq_byname\n- Fixed duplicated argument mac_get_mii_interface\n- Used common define for MAC/PMAC\n---\n drivers/net/ethernet/intel/Kconfig                 |  11 +\n drivers/net/ethernet/intel/Makefile                |   1 +\n drivers/net/ethernet/intel/gwdpa/Makefile          |   5 +\n drivers/net/ethernet/intel/gwdpa/gswip/Makefile    |  10 +\n drivers/net/ethernet/intel/gwdpa/gswip/gswip.h     | 448 ++++++++++++\n .../net/ethernet/intel/gwdpa/gswip/gswip_core.c    | 804 +++++++++++++++++++++\n .../net/ethernet/intel/gwdpa/gswip/gswip_core.h    |  90 +++\n drivers/net/ethernet/intel/gwdpa/gswip/gswip_dev.c | 179 +++++\n drivers/net/ethernet/intel/gwdpa/gswip/gswip_dev.h |  19 +\n drivers/net/ethernet/intel/gwdpa/gswip/gswip_mac.c | 225 ++++++\n .../net/ethernet/intel/gwdpa/gswip/gswip_port.c    | 330 +++++++++\n drivers/net/ethernet/intel/gwdpa/gswip/gswip_reg.h | 491 +++++++++++++\n drivers/net/ethernet/intel/gwdpa/gswip/gswip_tbl.c | 332 +++++++++\n drivers/net/ethernet/intel/gwdpa/gswip/gswip_tbl.h | 195 +++++\n drivers/net/ethernet/intel/gwdpa/gswip/lmac.c      |  46 ++\n drivers/net/ethernet/intel/gwdpa/gswip/mac_cfg.c   | 524 ++++++++++++++\n .../net/ethernet/intel/gwdpa/gswip/mac_common.h    | 238 ++++++\n drivers/net/ethernet/intel/gwdpa/gswip/mac_dev.c   | 186 +++++\n drivers/net/ethernet/intel/gwdpa/gswip/xgmac.c     | 643 ++++++++++++++++\n drivers/net/ethernet/intel/gwdpa/gswip/xgmac.h     | 236 ++++++\n 20 files changed, 5013 insertions(+)\n create mode 100644 drivers/net/ethernet/intel/gwdpa/Makefile\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/Makefile\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/gswip.h\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/gswip_core.c\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/gswip_core.h\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/gswip_dev.c\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/gswip_dev.h\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/gswip_mac.c\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/gswip_port.c\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/gswip_reg.h\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/gswip_tbl.c\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/gswip_tbl.h\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/lmac.c\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/mac_cfg.c\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/mac_common.h\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/mac_dev.c\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/xgmac.c\n create mode 100644 drivers/net/ethernet/intel/gwdpa/gswip/xgmac.h",
    "diff": "diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig\nindex 154e2e818ec6..82fa937cfa48 100644\n--- a/drivers/net/ethernet/intel/Kconfig\n+++ b/drivers/net/ethernet/intel/Kconfig\n@@ -341,4 +341,15 @@ config IGC\n \t  To compile this driver as a module, choose M here. The module\n \t  will be called igc.\n \n+config INTEL_GSWIP\n+\ttristate \"Intel(R) Gigabit Ethernet Switch IP support\"\n+\tdefault n\n+\tdepends on OF_MDIO\n+\thelp\n+\t  Turn on this option to build GSWIP driver.\n+\t  Gigabit Ethernet Switch is a hardware IP in the\n+\t  Intel Networking SoCs. This driver consists of\n+\t  core and mac. It is part of the Intel gateway\n+\t  datapath architecture.\n+\n endif # NET_VENDOR_INTEL\ndiff --git a/drivers/net/ethernet/intel/Makefile b/drivers/net/ethernet/intel/Makefile\nindex 3075290063f6..ab3281e9bc4c 100644\n--- a/drivers/net/ethernet/intel/Makefile\n+++ b/drivers/net/ethernet/intel/Makefile\n@@ -16,3 +16,4 @@ obj-$(CONFIG_IXGB) += ixgb/\n obj-$(CONFIG_IAVF) += iavf/\n obj-$(CONFIG_FM10K) += fm10k/\n obj-$(CONFIG_ICE) += ice/\n+obj-y += gwdpa/\ndiff --git a/drivers/net/ethernet/intel/gwdpa/Makefile b/drivers/net/ethernet/intel/gwdpa/Makefile\nnew file mode 100644\nindex 000000000000..ada65e907601\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/Makefile\n@@ -0,0 +1,5 @@\n+# SPDX-License-Identifier: GPL-2.0\n+#\n+# Makefile for the Intel datapath specific drivers.\n+#\n+obj-$(CONFIG_INTEL_GSWIP)\t+= gswip/\n\\ No newline at end of file\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/Makefile b/drivers/net/ethernet/intel/gwdpa/gswip/Makefile\nnew file mode 100644\nindex 000000000000..548b716d6984\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/Makefile\n@@ -0,0 +1,10 @@\n+# SPDX-License-Identifier: GPL-2.0\n+#\n+# Makefile for GSWIP\n+#\n+obj-y += gswip-dev.o gswip-core.o gswip-mac.o\n+\n+gswip-dev-y := gswip_dev.o\n+gswip-core-y := gswip_core.o gswip_port.o gswip_tbl.o\n+gswip-mac-y := mac_dev.o mac_cfg.o gswip_mac.o xgmac.o lmac.o\n+\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/gswip.h b/drivers/net/ethernet/intel/gwdpa/gswip/gswip.h\nnew file mode 100644\nindex 000000000000..1e8b4b5b146a\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/gswip.h\n@@ -0,0 +1,448 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2016-2019 Intel Corporation. */\n+#ifndef _DATAPATH_GSWIP_H_\n+#define _DATAPATH_GSWIP_H_\n+\n+#include <linux/device.h>\n+#include <linux/bits.h>\n+\n+#define BR_PORT_MAP_NUM\t\t16\n+#define PMAC_BSL_THRES_NUM\t3\n+#define PMAC_HEADER_NUM\t\t8\n+\n+enum gswip_cpu_parser_hdr_cfg {\n+\tGSWIP_CPU_PARSER_NIL,\n+\tGSWIP_CPU_PARSER_FLAGS,\n+\tGSWIP_CPU_PARSER_OFFSETS_FLAGS,\n+\tGSWIP_CPU_PARSER_RESERVED,\n+};\n+\n+struct gswip_cpu_port_cfg {\n+\tu8 lpid;\n+\tbool is_cpu_port;\n+\tbool spec_tag_ig;\n+\tbool spec_tag_eg;\n+\tbool fcs_chk;\n+\tbool fcs_generate;\n+\tenum gswip_cpu_parser_hdr_cfg no_mpe_parser_cfg;\n+\tenum gswip_cpu_parser_hdr_cfg mpe1_parser_cfg;\n+\tenum gswip_cpu_parser_hdr_cfg mpe2_parser_cfg;\n+\tenum gswip_cpu_parser_hdr_cfg mpe3_parser_cfg;\n+\tbool ts_rm_ptp_pkt;\n+\tbool ts_rm_non_ptp_pkt;\n+};\n+\n+enum gswip_pmac_short_frm_chk {\n+\tGSWIP_PMAC_SHORT_LEN_DIS,\n+\tGSWIP_PMAC_SHORT_LEN_ENA_UNTAG,\n+\tGSWIP_PMAC_SHORT_LEN_ENA_TAG,\n+\tGSWIP_PMAC_SHORT_LEN_RESERVED,\n+};\n+\n+enum gswip_pmac_proc_flags_eg_cfg {\n+\tGSWIP_PMAC_PROC_FLAGS_NONE,\n+\tGSWIP_PMAC_PROC_FLAGS_TC,\n+\tGSWIP_PMAC_PROC_FLAGS_FLAG,\n+\tGSWIP_PMAC_PROC_FLAGS_MIX,\n+};\n+\n+struct gswip_pmac_glb_cfg {\n+\tu8 pmac_id;\n+\tbool apad_en;\n+\tbool pad_en;\n+\tbool vpad_en;\n+\tbool svpad_en;\n+\tbool rx_fcs_dis;\n+\tbool tx_fcs_dis;\n+\tbool ip_trans_chk_reg_dis;\n+\tbool ip_trans_chk_ver_dis;\n+\tbool jumbo_en;\n+\tu16 max_jumbo_len;\n+\tu16 jumbo_thresh_len;\n+\tbool long_frm_chk_dis;\n+\tenum gswip_pmac_short_frm_chk short_frm_chk_type;\n+\tbool proc_flags_eg_cfg_en;\n+\tenum gswip_pmac_proc_flags_eg_cfg proc_flags_eg_cfg;\n+\tu16 bsl_thresh[PMAC_BSL_THRES_NUM];\n+};\n+\n+struct gswip_pmac_bp_map {\n+\tu8 pmac_id;\n+\tu8 tx_dma_chan_id;\n+\tu32 tx_q_mask;\n+\tu32 rx_port_mask;\n+};\n+\n+enum gswip_pmac_ig_cfg_src {\n+\tGSWIP_PMAC_IG_CFG_SRC_DMA_DESC,\n+\tGSWIP_PMAC_IG_CFG_SRC_DEF_PMAC,\n+\tGSWIP_PMAC_IG_CFG_SRC_PMAC,\n+};\n+\n+struct gswip_pmac_ig_cfg {\n+\tu8 pmac_id;\n+\tu8 tx_dma_chan_id;\n+\tbool err_pkt_disc;\n+\tbool class_def;\n+\tbool class_en;\n+\tenum gswip_pmac_ig_cfg_src sub_id;\n+\tbool src_port_id_def;\n+\tbool pmac_present;\n+\tu8 def_pmac_hdr[PMAC_HEADER_NUM];\n+};\n+\n+struct gswip_pmac_eg_cfg {\n+\tu8 pmac_id;\n+\tu8 dst_port_id;\n+\tu8 tc;\n+\tbool mpe1;\n+\tbool mpe2;\n+\tbool decrypt;\n+\tbool encrypt;\n+\tu8 flow_id_msb;\n+\tbool process_sel;\n+\tu8 rx_dma_chan_id;\n+\tbool rm_l2_hdr;\n+\tu8 num_byte_rm;\n+\tbool fcs_en;\n+\tbool pmac_en;\n+\tbool redir_en;\n+\tbool bsl_seg_disable;\n+\tu8 bsl_tc;\n+\tbool resv_dw1_en;\n+\tu8 resv_dw1;\n+\tbool resv_1dw0_en;\n+\tu8 resv_1dw0;\n+\tbool resv_2dw0_en;\n+\tu8 resv_2dw0;\n+\tbool tc_en;\n+};\n+\n+struct gswip_lpid2gpid {\n+\tu16 lpid;\n+\tu16 first_gpid;\n+\tu16 num_gpid;\n+\tu8 valid_bits;\n+};\n+\n+struct gswip_gpid2lpid {\n+\tu16 gpid;\n+\tu16 lpid;\n+\tu8 subif_grp_field;\n+\tbool subif_grp_field_ovr;\n+};\n+\n+enum gswip_ctp_port_config_mask {\n+\tGSWIP_CTP_PORT_CONFIG_MASK_BRIDGE_PORT_ID\t= BIT(0),\n+\tGSWIP_CTP_PORT_CONFIG_MASK_FORCE_TRAFFIC_CLASS\t= BIT(1),\n+\tGSWIP_CTP_PORT_CONFIG_MASK_INGRESS_VLAN\t\t= BIT(2),\n+\tGSWIP_CTP_PORT_CONFIG_MASK_INGRESS_VLAN_IGMP\t= BIT(3),\n+\tGSWIP_CTP_PORT_CONFIG_MASK_EGRESS_VLAN\t\t= BIT(4),\n+\tGSWIP_CTP_PORT_CONFIG_MASK_EGRESS_VLAN_IGMP\t= BIT(5),\n+\tGSWIP_CTP_PORT_CONFIG_MASK_INRESS_NTO1_VLAN\t= BIT(6),\n+\tGSWIP_CTP_PORT_CONFIG_MASK_EGRESS_NTO1_VLAN\t= BIT(7),\n+\tGSWIP_CTP_PORT_CONFIG_INGRESS_MARKING\t\t= BIT(8),\n+\tGSWIP_CTP_PORT_CONFIG_EGRESS_MARKING\t\t= BIT(9),\n+\tGSWIP_CTP_PORT_CONFIG_EGRESS_MARKING_OVERRIDE\t= BIT(10),\n+\tGSWIP_CTP_PORT_CONFIG_EGRESS_REMARKING\t\t= BIT(11),\n+\tGSWIP_CTP_PORT_CONFIG_INGRESS_METER\t\t= BIT(12),\n+\tGSWIP_CTP_PORT_CONFIG_EGRESS_METER\t\t= BIT(13),\n+\tGSWIP_CTP_PORT_CONFIG_BRIDGING_BYPASS\t\t= BIT(14),\n+\tGSWIP_CTP_PORT_CONFIG_FLOW_ENTRY\t\t= BIT(15),\n+\tGSWIP_CTP_PORT_CONFIG_LOOPBACK_AND_MIRROR\t= BIT(16),\n+\tGSWIP_CTP_PORT_CONFIG_MASK_FORCE\t\t= BIT(31),\n+};\n+\n+struct gswip_ctp_port_cfg {\n+\tu8 lpid;\n+\tu16 subif_id_grp;\n+\tu16 br_pid;\n+\tenum gswip_ctp_port_config_mask mask;\n+\tbool br_bypass;\n+};\n+\n+enum gswip_lport_mode {\n+\tGSWIP_LPORT_8BIT_WLAN,\n+\tGSWIP_LPORT_9BIT_WLAN,\n+\tGSWIP_LPORT_GPON,\n+\tGSWIP_LPORT_EPON,\n+\tGSWIP_LPORT_GINT,\n+\tGSWIP_LPORT_OTHER = 0xFF,\n+};\n+\n+struct gswip_ctp_port_info {\n+\tu8 lpid;\n+\tu16 first_pid;\n+\tu16 num_port;\n+\tenum gswip_lport_mode mode;\n+\tu16 br_pid;\n+};\n+\n+enum gswip_br_port_cfg_mask {\n+\tGSWIP_BR_PORT_CFG_MASK_BR_ID\t\t\t= BIT(0),\n+\tGSWIP_BR_PORT_CFG_MASK_IG_VLAN\t\t\t= BIT(1),\n+\tGSWIP_BR_PORT_CFG_MASK_EG_VLAN\t\t\t= BIT(2),\n+\tGSWIP_BR_PORT_CFG_MASK_IG_MARKING\t\t= BIT(3),\n+\tGSWIP_BR_PORT_CFG_MASK_EG_REMARKING\t\t= BIT(4),\n+\tGSWIP_BR_PORT_CFG_MASK_IG_METER\t\t\t= BIT(5),\n+\tGSWIP_BR_PORT_CFG_MASK_EG_SUB_METER\t\t= BIT(6),\n+\tGSWIP_BR_PORT_CFG_MASK_EG_CTP_MAPPING\t\t= BIT(7),\n+\tGSWIP_BR_PORT_CFG_MASK_BR_PORT_MAP\t\t= BIT(8),\n+\tGSWIP_BR_PORT_CFG_MASK_MCAST_DST_IP_LOOKUP\t= BIT(9),\n+\tGSWIP_BR_PORT_CFG_MASK_MCAST_SRC_IP_LOOKUP\t= BIT(10),\n+\tGSWIP_BR_PORT_CFG_MASK_MCAST_DST_MAC_LOOKUP\t= BIT(11),\n+\tGSWIP_BR_PORT_CFG_MASK_MCAST_SRC_MAC_LEARNING\t= BIT(12),\n+\tGSWIP_BR_PORT_CFG_MASK_MAC_SPOOFING\t\t= BIT(13),\n+\tGSWIP_BR_PORT_CFG_MASK_PORT_LOCK\t\t= BIT(14),\n+\tGSWIP_BR_PORT_CFG_MASK_MAC_LEARNING_LIMIT\t= BIT(15),\n+\tGSWIP_BR_PORT_CFG_MASK_MAC_LEARNED_COUNT\t= BIT(16),\n+\tGSWIP_BR_PORT_CFG_MASK_IG_VLAN_FILTER\t\t= BIT(17),\n+\tGSWIP_BR_PORT_CFG_MASK_EG_VLAN_FILTER1\t\t= BIT(18),\n+\tGSWIP_BR_PORT_CFG_MASK_EG_VLAN_FILTER2\t\t= BIT(19),\n+\tGSWIP_BR_PORT_CFG_MASK_FORCE\t\t\t= BIT(31),\n+};\n+\n+enum gswip_pmapper_mapping_mode {\n+\tGSWIP_PMAPPER_MAPPING_PCP,\n+\tGSWIP_PMAPPER_MAPPING_DSCP,\n+};\n+\n+enum gswip_br_port_eg_meter {\n+\tGSWIP_BR_PORT_EG_METER_BROADCAST,\n+\tGSWIP_BR_PORT_EG_METER_MULTICAST,\n+\tGSWIP_BR_PORT_EG_METER_UNKNOWN_MCAST_IP,\n+\tGSWIP_BR_PORT_EG_METER_UNKNOWN_MCAST_NON_IP,\n+\tGSWIP_BR_PORT_EG_METER_UNKNOWN_UCAST,\n+\tGSWIP_BR_PORT_EG_METER_OTHERS,\n+\tGSWIP_BR_PORT_EG_METER_MAX,\n+};\n+\n+struct gswip_br_port_alloc {\n+\tu8 br_id;\n+\tu8 br_pid;\n+};\n+\n+enum gswip_br_cfg_mask {\n+\tGSWIP_BR_CFG_MASK_MAC_LEARNING_LIMIT\t= BIT(0),\n+\tGSWIP_BR_CFG_MASK_MAC_LEARNED_COUNT\t= BIT(1),\n+\tGSWIP_BR_CFG_MASK_MAC_DISCARD_COUNT\t= BIT(2),\n+\tGSWIP_BR_CFG_MASK_SUB_METER\t\t= BIT(3),\n+\tGSWIP_BR_CFG_MASK_FORWARDING_MODE\t= BIT(4),\n+\tGSWIP_BR_CFG_MASK_FORCE\t\t\t= BIT(31),\n+};\n+\n+enum gswip_br_fwd_mode {\n+\tGSWIP_BR_FWD_FLOOD,\n+\tGSWIP_BR_FWD_DISCARD,\n+\tGSWIP_BR_FWD_CPU,\n+};\n+\n+struct gswip_br_alloc {\n+\tu8 br_id;\n+};\n+\n+struct gswip_br_cfg {\n+\tu8 br_id;\n+\tenum gswip_br_cfg_mask mask;\n+\tbool mac_lrn_limit_en;\n+\tu16 mac_lrn_limit;\n+\tu16 mac_lrn_count;\n+\tu32 lrn_disc_event;\n+\tenum gswip_br_fwd_mode fwd_bcast;\n+\tenum gswip_br_fwd_mode fwd_unk_mcast_ip;\n+\tenum gswip_br_fwd_mode fwd_unk_mcast_non_ip;\n+\tenum gswip_br_fwd_mode fwd_unk_ucast;\n+};\n+\n+struct gswip_qos_wred_q_cfg {\n+\tu8 qid;\n+\tu16 red_min;\n+\tu16 red_max;\n+\tu16 yellow_min;\n+\tu16 yellow_max;\n+\tu16 green_min;\n+\tu16 green_max;\n+};\n+\n+struct gswip_qos_wred_port_cfg {\n+\tu8 lpid;\n+\tu16 red_min;\n+\tu16 red_max;\n+\tu16 yellow_min;\n+\tu16 yellow_max;\n+\tu16 green_min;\n+\tu16 green_max;\n+};\n+\n+enum gswip_qos_q_map_mode {\n+\tGSWIP_QOS_QMAP_SINGLE_MD,\n+\tGSWIP_QOS_QMAP_SUBIFID_MD,\n+};\n+\n+struct gswip_qos_q_port {\n+\tu8 lpid;\n+\tbool extration_en;\n+\tenum gswip_qos_q_map_mode q_map_mode;\n+\tu8 tc_id;\n+\tu8 qid;\n+\tbool egress;\n+\tu8 redir_port_id;\n+\tbool en_ig_pce_bypass;\n+\tbool resv_port_mode;\n+};\n+\n+struct gswip_register {\n+\tu16 offset;\n+\tu16 data;\n+};\n+\n+enum {\n+\tSPEED_LMAC_10M,\n+\tSPEED_LMAC_100M,\n+\tSPEED_LMAC_200M,\n+\tSPEED_LMAC_1G,\n+\tSPEED_XGMAC_10M,\n+\tSPEED_XGMAC_100M,\n+\tSPEED_XGMAC_1G,\n+\tSPEED_XGMII_25G,\n+\tSPEED_XGMAC_5G,\n+\tSPEED_XGMAC_10G,\n+\tSPEED_GMII_25G,\n+\tSPEED_MAC_AUTO,\n+};\n+\n+enum gsw_portspeed {\n+\t/* 10 Mbit/s */\n+\tGSW_PORT_SPEED_10 = 10,\n+\n+\t/* 100 Mbit/s */\n+\tGSW_PORT_SPEED_100 = 100,\n+\n+\t/* 200 Mbit/s */\n+\tGSW_PORT_SPEED_200 = 200,\n+\n+\t/* 1000 Mbit/s */\n+\tGSW_PORT_SPEED_1000 = 1000,\n+\n+\t/* 2.5 Gbit/s */\n+\tGSW_PORT_SPEED_25000 = 25000,\n+\n+\t/* 10 Gbit/s */\n+\tGSW_PORT_SPEED_100000 = 100000,\n+};\n+\n+enum gsw_portlink_status {\n+\tLINK_AUTO,\n+\tLINK_UP,\n+\tLINK_DOWN,\n+};\n+\n+enum gsw_flow_control_modes {\n+\tFC_AUTO,\n+\tFC_RX,\n+\tFC_TX,\n+\tFC_RXTX,\n+\tFC_DIS,\n+\tFC_INVALID,\n+};\n+\n+/* Ethernet port interface mode. */\n+enum gsw_mii_mode {\n+\t/* Normal PHY interface (twisted pair), use internal MII Interface */\n+\tGSW_PORT_HW_MII,\n+\n+\t/* Reduced MII interface in normal mode */\n+\tGSW_PORT_HW_RMII,\n+\n+\t/* GMII or MII, depending upon the speed */\n+\tGSW_PORT_HW_GMII,\n+\n+\t/* RGMII mode */\n+\tGSW_PORT_HW_RGMII,\n+\n+\t/* XGMII mode */\n+\tGSW_PORT_HW_XGMII,\n+};\n+\n+struct core_common_ops {\n+\tint (*enable)(struct device *dev, bool enable);\n+\tint (*cpu_port_cfg_get)(struct device *dev,\n+\t\t\t\tstruct gswip_cpu_port_cfg *cpu);\n+\tint (*reg_get)(struct device *dev, struct gswip_register *param);\n+\tint (*reg_set)(struct device *dev, struct gswip_register *param);\n+};\n+\n+struct core_pmac_ops {\n+\tint (*gbl_cfg_set)(struct device *dev, struct gswip_pmac_glb_cfg *pmac);\n+\tint (*bp_map_get)(struct device *dev, struct gswip_pmac_bp_map *bp);\n+\tint (*ig_cfg_set)(struct device *dev, struct gswip_pmac_ig_cfg *ig);\n+\tint (*eg_cfg_set)(struct device *dev, struct gswip_pmac_eg_cfg *eg);\n+};\n+\n+struct core_gpid_ops {\n+\tint (*lpid2gpid_set)(struct device *dev,\n+\t\t\t     struct gswip_lpid2gpid *lp2gp);\n+\tint (*lpid2gpid_get)(struct device *dev,\n+\t\t\t     struct gswip_lpid2gpid *lp2gp);\n+\tint (*gpid2lpid_set)(struct device *dev,\n+\t\t\t     struct gswip_gpid2lpid *gp2lp);\n+\tint (*gpid2lpid_get)(struct device *dev,\n+\t\t\t     struct gswip_gpid2lpid *gp2lp);\n+};\n+\n+struct core_ctp_ops {\n+\tint (*alloc)(struct device *dev, struct gswip_ctp_port_info *ctp);\n+\tint (*free)(struct device *dev, u8 lpid);\n+};\n+\n+struct core_br_port_ops {\n+\tint (*alloc)(struct device *dev, struct gswip_br_port_alloc *bp);\n+\tint (*free)(struct device *dev, struct gswip_br_port_alloc *bp);\n+};\n+\n+struct core_br_ops {\n+\tint (*alloc)(struct device *dev, struct gswip_br_alloc *br);\n+\tint (*free)(struct device *dev, struct gswip_br_alloc *br);\n+};\n+\n+struct core_qos_ops {\n+\tint (*q_port_set)(struct device *dev, struct gswip_qos_q_port *qport);\n+\tint (*wred_q_cfg_set)(struct device *dev,\n+\t\t\t      struct gswip_qos_wred_q_cfg *wredq);\n+\tint (*wred_port_cfg_set)(struct device *dev,\n+\t\t\t\t struct gswip_qos_wred_port_cfg *wredp);\n+};\n+\n+struct gsw_mac_ops {\n+\t/* Initialize MAC */\n+\tint (*init)(struct device *dev);\n+\n+\tint (*set_macaddr)(struct device *dev, u8 *mac_addr);\n+\tint (*get_link_sts)(struct device *dev);\n+\n+\tint (*get_duplex)(struct device *dev);\n+\n+\tint (*set_speed)(struct device *dev, u8 speed);\n+\tint (*get_speed)(struct device *dev);\n+\n+\tu32 (*get_mtu)(struct device *dev);\n+\tint (*set_mtu)(struct device *dev, u32 mtu);\n+\n+\tu32 (*get_flowctrl)(struct device *dev);\n+\tint (*set_flowctrl)(struct device *dev, u32 val);\n+\n+\tint (*get_pfsa)(struct device *dev, u8 *addr, u32 *mode);\n+\tint (*set_pfsa)(struct device *dev, u8 *mac_addr, u32 macif);\n+\n+\tint (*get_mii_if)(struct device *dev);\n+\tint (*set_mii_if)(struct device *dev, u32 mii_mode);\n+\n+\tu32 (*get_lpi)(struct device *dev);\n+\n+\tint (*get_fcsgen)(struct device *dev);\n+};\n+\n+struct gsw_adap_ops {\n+\tint (*sw_core_enable)(struct device *dev, u32 val);\n+};\n+#endif\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/gswip_core.c b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_core.c\nnew file mode 100644\nindex 000000000000..164840beaae4\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_core.c\n@@ -0,0 +1,804 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2016-2019 Intel Corporation. */\n+\n+#include <asm/unaligned.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/of_platform.h>\n+\n+#include \"gswip_core.h\"\n+#include \"gswip_dev.h\"\n+#include \"gswip_reg.h\"\n+#include \"gswip_tbl.h\"\n+#include \"mac_common.h\"\n+\n+#define GSWIP_VER\t\t0x32\n+\n+/* TX DMA channels for PMAC0 to PMAC2 */\n+#define PMAC0_TX_DMACHID_START\t0\n+#define PMAC0_TX_DMACHID_END\t16\n+#define PMAC1_TX_DMACHID_START\t0\n+#define PMAC1_TX_DMACHID_END\t16\n+#define PMAC2_TX_DMACHID_START\t0\n+#define PMAC2_TX_DMACHID_END\t16\n+\n+#define MAX_JUMBO_FRM_LEN\t10000\n+\n+/* Data Protocol Unit (DPU) */\n+enum dpu {\n+\tDPU,\n+\tNON_DPU,\n+};\n+\n+enum queue_id {\n+\tQUEUE0,\n+\tQUEUE1,\n+\tQUEUE2,\n+\tQUEUE3,\n+\tQUEUE4,\n+\tQUEUE5,\n+\tQUEUE6,\n+\tQUEUE7,\n+\tQUEUE8,\n+\tQUEUE9,\n+\tQUEUE10,\n+};\n+\n+enum traffic_class {\n+\tTC0,\n+\tTC1,\n+\tTC2,\n+\tTC3,\n+\tTC_MAX,\n+};\n+\n+struct eg_pce_bypass_path {\n+\t/* egress logical port id */\n+\tu8 eg_pid;\n+\t/* local extracted */\n+\tbool ext;\n+\t/* queue id */\n+\tu8 qid;\n+\t/* redirect logical port id */\n+\tu8 redir_pid;\n+};\n+\n+struct ig_pce_bypass_path {\n+\t/* ingress logical port id */\n+\tu8 ig_pid;\n+\t/* local extracted */\n+\tbool ext;\n+\t/* traffic class */\n+\tu8 tc_start;\n+\tu8 tc_end;\n+\t/* queue id */\n+\tu8 qid;\n+\t/* redirect logical port id */\n+\tu8 redir_pid;\n+};\n+\n+/* default GSWIP egress PCE bypass path Q-map */\n+static struct eg_pce_bypass_path eg_pce_byp_path[] = {\n+\t{MAC2,  false, QUEUE0, MAC2 },\n+\t{MAC3,  false, QUEUE1, MAC3 },\n+\t{MAC4,  false, QUEUE2, MAC4 },\n+\t{MAC5,  false, QUEUE3, MAC5 },\n+\t{MAC6,  false, QUEUE4, MAC6 },\n+\t{MAC7,  false, QUEUE5, MAC7 },\n+\t{MAC8,  false, QUEUE6, MAC8 },\n+\t{MAC9,  false, QUEUE7, MAC9 },\n+\t{MAC10, false, QUEUE8, MAC10},\n+};\n+\n+/* default GSWIP ingress PCE bypass path Q-map */\n+static struct ig_pce_bypass_path ig_pce_byp_path[] = {\n+\t{PMAC0, false, TC0, TC_MAX, QUEUE10, PMAC2},\n+\t{MAC2,  false, TC0, TC_MAX, QUEUE10, PMAC2},\n+\t{MAC3,  false, TC0, TC_MAX, QUEUE10, PMAC2},\n+\t{MAC4,  false, TC0, TC_MAX, QUEUE10, PMAC2},\n+\t{MAC5,  false, TC0, TC_MAX, QUEUE10, PMAC2},\n+\t{MAC6,  false, TC0, TC_MAX, QUEUE10, PMAC2},\n+\t{MAC7,  false, TC0, TC_MAX, QUEUE10, PMAC2},\n+\t{MAC8,  false, TC0, TC_MAX, QUEUE10, PMAC2},\n+\t{MAC9,  false, TC0, TC_MAX, QUEUE10, PMAC2},\n+\t{MAC10, false, TC0, TC_MAX, QUEUE10, PMAC2},\n+};\n+\n+static inline int pmac_ig_cfg(struct gswip_core_priv *priv, u8 pmac_id, u8 dpu)\n+{\n+\tconst struct core_pmac_ops *pmac_ops =  priv->ops.pmac_ops;\n+\tu8 start[] = { PMAC0_TX_DMACHID_START,\n+\t\t       PMAC1_TX_DMACHID_START,\n+\t\t       PMAC2_TX_DMACHID_START };\n+\tu8 end[] = { PMAC0_TX_DMACHID_END,\n+\t\t     PMAC1_TX_DMACHID_END,\n+\t\t     PMAC2_TX_DMACHID_END };\n+\tu8 pmac[] = { PMAC0, PMAC1, PMAC2 };\n+\tstruct gswip_pmac_ig_cfg ig_cfg = {0};\n+\tint i, ret;\n+\n+\tig_cfg.pmac_id = pmac_id;\n+\tig_cfg.err_pkt_disc = true;\n+\tig_cfg.class_en = true;\n+\n+\tfor (i = start[pmac_id]; i < end[pmac_id]; i++) {\n+\t\tig_cfg.tx_dma_chan_id = i;\n+\t\tig_cfg.def_pmac_hdr[2] = FIELD_PREP(PMAC_IGCFG_HDR_ID,\n+\t\t\t\t\t\t    pmac[pmac_id]);\n+\n+\t\tret = pmac_ops->ig_cfg_set(priv->dev, &ig_cfg);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static inline int pmac_eg_cfg(struct gswip_core_priv *priv, u8 pmac_id, u8 dpu)\n+{\n+\tconst struct core_pmac_ops *pmac_ops =  priv->ops.pmac_ops;\n+\tstruct gswip_pmac_eg_cfg pmac_eg = {0};\n+\n+\tpmac_eg.pmac_id = pmac_id;\n+\tpmac_eg.pmac_en = true;\n+\tpmac_eg.bsl_seg_disable = true;\n+\n+\treturn pmac_ops->eg_cfg_set(priv->dev, &pmac_eg);\n+}\n+\n+static inline int pmac_glbl_cfg(struct gswip_core_priv *priv, u8 pmac_id)\n+{\n+\tconst struct core_pmac_ops *pmac_ops =  priv->ops.pmac_ops;\n+\tstruct gswip_pmac_glb_cfg pmac_cfg = {0};\n+\n+\tpmac_cfg.pmac_id = pmac_id;\n+\tpmac_cfg.rx_fcs_dis = true;\n+\tpmac_cfg.jumbo_en = true;\n+\tpmac_cfg.max_jumbo_len = MAX_JUMBO_FRM_LEN;\n+\tpmac_cfg.long_frm_chk_dis = true;\n+\tpmac_cfg.short_frm_chk_type = GSWIP_PMAC_SHORT_LEN_ENA_UNTAG;\n+\tpmac_cfg.proc_flags_eg_cfg_en = true;\n+\tpmac_cfg.proc_flags_eg_cfg = GSWIP_PMAC_PROC_FLAGS_MIX;\n+\n+\treturn pmac_ops->gbl_cfg_set(priv->dev, &pmac_cfg);\n+}\n+\n+static int gswip_core_pmac_init_nondpu(struct gswip_core_priv *priv)\n+{\n+\tint i, ret;\n+\n+\tfor (i = 0; i < priv->num_pmac; i++) {\n+\t\tret = pmac_glbl_cfg(priv, i);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tret = pmac_ig_cfg(priv, i, NON_DPU);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tret = pmac_eg_cfg(priv, i, NON_DPU);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int gswip_core_set_def_eg_pce_bypass_qmap(struct gswip_core_priv *priv,\n+\t\t\t\t\t\t enum gswip_qos_q_map_mode mode)\n+{\n+\tconst struct core_qos_ops *qos_ops =  priv->ops.qos_ops;\n+\tint num_elem = ARRAY_SIZE(eg_pce_byp_path);\n+\tstruct gswip_qos_q_port q_map = {0};\n+\tint i, ret;\n+\n+\tq_map.egress = true;\n+\tq_map.q_map_mode = mode;\n+\n+\tfor (i = 0; i < num_elem; i++) {\n+\t\tq_map.lpid = eg_pce_byp_path[i].eg_pid;\n+\t\tq_map.extration_en = eg_pce_byp_path[i].ext;\n+\t\tq_map.qid = eg_pce_byp_path[i].qid;\n+\t\tq_map.redir_port_id = eg_pce_byp_path[i].redir_pid;\n+\n+\t\tret = qos_ops->q_port_set(priv->dev, &q_map);\n+\t\tif (ret)\n+\t\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int gswip_core_set_def_ig_pce_bypass_qmap(struct gswip_core_priv *priv)\n+{\n+\tconst struct core_qos_ops *qos_ops =  priv->ops.qos_ops;\n+\tint num_elem = ARRAY_SIZE(ig_pce_byp_path);\n+\tstruct gswip_qos_q_port q_map = {0};\n+\tint i, j, ret;\n+\n+\tq_map.en_ig_pce_bypass = true;\n+\n+\tfor (i = 0; i < num_elem; i++) {\n+\t\tfor (j = ig_pce_byp_path[i].tc_start;\n+\t\t     j < ig_pce_byp_path[i].tc_end; j++) {\n+\t\t\tq_map.lpid = ig_pce_byp_path[i].ig_pid;\n+\t\t\tq_map.qid = ig_pce_byp_path[i].qid;\n+\t\t\tq_map.redir_port_id = ig_pce_byp_path[i].redir_pid;\n+\t\t\tq_map.tc_id = j;\n+\n+\t\t\tret = qos_ops->q_port_set(priv->dev, &q_map);\n+\t\t\tif (ret)\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static inline u16 pmac_reg(u16 offset, u8 id)\n+{\n+\tu16 pmac_offset[] = { 0, PMAC_REG_OFFSET_1, PMAC_REG_OFFSET_2 };\n+\n+\treturn offset += pmac_offset[id];\n+}\n+\n+/* PMAC global configuration */\n+static int gswip_pmac_glb_cfg_set(struct device *dev,\n+\t\t\t\t  struct gswip_pmac_glb_cfg *pmac)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tu16 bsl_reg[] = { PMAC_BSL_LEN0, PMAC_BSL_LEN1, PMAC_BSL_LEN2 };\n+\tu16 ctrl_reg[] = { PMAC_CTRL_0, PMAC_CTRL_1,\n+\t\t\t   PMAC_CTRL_2, PMAC_CTRL_4 };\n+\tu16 ctrl[PMAC_CTRL_NUM] = {0};\n+\tu8 id;\n+\tint i;\n+\n+\tif (pmac->pmac_id >= priv->num_pmac) {\n+\t\tdev_err(priv->dev, \"Invalid pmac id %d\\n\", pmac->pmac_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tctrl[0] = FIELD_PREP(PMAC_CTRL_0_FCSEN, pmac->rx_fcs_dis) |\n+\t\t  FIELD_PREP(PMAC_CTRL_0_APADEN, pmac->apad_en) |\n+\t\t  FIELD_PREP(PMAC_CTRL_0_VPAD2EN, pmac->svpad_en) |\n+\t\t  FIELD_PREP(PMAC_CTRL_0_VPADEN, pmac->vpad_en) |\n+\t\t  FIELD_PREP(PMAC_CTRL_0_PADEN, pmac->pad_en) |\n+\t\t  FIELD_PREP(PMAC_CTRL_0_FCS, pmac->tx_fcs_dis) |\n+\t\t  FIELD_PREP(PMAC_CTRL_0_CHKREG, pmac->ip_trans_chk_reg_dis) |\n+\t\t  FIELD_PREP(PMAC_CTRL_0_CHKVER, pmac->ip_trans_chk_ver_dis);\n+\n+\tif (pmac->jumbo_en) {\n+\t\tctrl[1] = pmac->max_jumbo_len,\n+\t\tctrl[2] = FIELD_PREP(PMAC_CTRL_2_MLEN, 1);\n+\t}\n+\n+\tctrl[2] |= FIELD_PREP(PMAC_CTRL_2_LCHKL, pmac->long_frm_chk_dis);\n+\n+\tswitch (pmac->short_frm_chk_type) {\n+\tcase GSWIP_PMAC_SHORT_LEN_DIS:\n+\t\tctrl[2] |= FIELD_PREP(PMAC_CTRL_2_LCHKS, 0);\n+\t\tbreak;\n+\n+\tcase GSWIP_PMAC_SHORT_LEN_ENA_UNTAG:\n+\t\tctrl[2] |= FIELD_PREP(PMAC_CTRL_2_LCHKS, 1);\n+\t\tbreak;\n+\n+\tcase GSWIP_PMAC_SHORT_LEN_ENA_TAG:\n+\t\tctrl[2] |= FIELD_PREP(PMAC_CTRL_2_LCHKS, 2);\n+\t\tbreak;\n+\n+\tcase GSWIP_PMAC_SHORT_LEN_RESERVED:\n+\t\tctrl[2] |= FIELD_PREP(PMAC_CTRL_2_LCHKS, 3);\n+\t\tbreak;\n+\t}\n+\n+\tswitch (pmac->proc_flags_eg_cfg) {\n+\tcase GSWIP_PMAC_PROC_FLAGS_NONE:\n+\t\tbreak;\n+\n+\tcase GSWIP_PMAC_PROC_FLAGS_TC:\n+\t\tctrl[3] |= FIELD_PREP(PMAC_CTRL_4_FLAGEN, 0);\n+\t\tbreak;\n+\n+\tcase GSWIP_PMAC_PROC_FLAGS_FLAG:\n+\t\tctrl[3] |= FIELD_PREP(PMAC_CTRL_4_FLAGEN, 1);\n+\t\tbreak;\n+\n+\tcase GSWIP_PMAC_PROC_FLAGS_MIX:\n+\t\tctrl[3] |= FIELD_PREP(PMAC_CTRL_4_FLAGEN, 2);\n+\t\tbreak;\n+\t}\n+\n+\tid = pmac->pmac_id;\n+\n+\tfor (i = 0; i < PMAC_CTRL_NUM; i++)\n+\t\tregmap_write(priv->regmap, pmac_reg(ctrl_reg[i], id), ctrl[i]);\n+\n+\tfor (i = 0; i < PMAC_BSL_NUM; i++)\n+\t\tregmap_write(priv->regmap, pmac_reg(bsl_reg[i], id),\n+\t\t\t     pmac->bsl_thresh[i]);\n+\n+\treturn 0;\n+}\n+\n+/* PMAC backpressure configuration */\n+static int gswip_pmac_bp_map_get(struct device *dev,\n+\t\t\t\t struct gswip_pmac_bp_map *bp)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tstruct pmac_tbl_prog pmac_tbl = {0};\n+\tint ret;\n+\n+\tpmac_tbl.id = PMAC_BP_MAP;\n+\tpmac_tbl.pmac_id = bp->pmac_id;\n+\tpmac_tbl.addr = FIELD_GET(PMAC_BPMAP_TX_DMA_CH, bp->tx_dma_chan_id);\n+\tpmac_tbl.num_val = PMAC_BP_MAP_TBL_VAL_NUM;\n+\n+\tret = gswip_pmac_table_read(priv, &pmac_tbl);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\tbp->rx_port_mask = pmac_tbl.val[0];\n+\tbp->tx_q_mask = pmac_tbl.val[1];\n+\tbp->tx_q_mask |= FIELD_PREP(PMAC_BPMAP_TX_Q_UPPER, pmac_tbl.val[2]);\n+\n+\treturn 0;\n+}\n+\n+/* PMAC ingress configuration */\n+static int gswip_pmac_ig_cfg_set(struct device *dev,\n+\t\t\t\t struct gswip_pmac_ig_cfg *ig)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tstruct pmac_tbl_prog pmac_tbl = {0};\n+\tu16 *val;\n+\tu16 i;\n+\n+\tpmac_tbl.id = PMAC_IG_CFG;\n+\tpmac_tbl.pmac_id = ig->pmac_id;\n+\tpmac_tbl.addr = FIELD_GET(PMAC_IGCFG_TX_DMA_CH, ig->tx_dma_chan_id);\n+\n+\tval = &pmac_tbl.val[0];\n+\tfor (i = 0; i < 4; i++)\n+\t\tval[i] = get_unaligned_be16(&ig->def_pmac_hdr[i * 2]);\n+\n+\tswitch (ig->sub_id) {\n+\tcase GSWIP_PMAC_IG_CFG_SRC_DMA_DESC:\n+\t\tbreak;\n+\n+\tcase GSWIP_PMAC_IG_CFG_SRC_PMAC:\n+\tcase GSWIP_PMAC_IG_CFG_SRC_DEF_PMAC:\n+\t\tval[4] = PMAC_IGCFG_VAL4_SUBID_MODE;\n+\t\tbreak;\n+\t}\n+\n+\tval[4] |= FIELD_PREP(PMAC_IGCFG_VAL4_PMAC_FLAG, ig->pmac_present) |\n+\t\t  FIELD_PREP(PMAC_IGCFG_VAL4_CLASSEN_MODE, ig->class_en) |\n+\t\t  FIELD_PREP(PMAC_IGCFG_VAL4_CLASS_MODE, ig->class_def) |\n+\t\t  FIELD_PREP(PMAC_IGCFG_VAL4_ERR_DP, ig->err_pkt_disc) |\n+\t\t  FIELD_PREP(PMAC_IGCFG_VAL4_SPPID_MODE, ig->src_port_id_def);\n+\n+\tpmac_tbl.num_val = PMAC_IG_CFG_TBL_VAL_NUM;\n+\n+\treturn gswip_pmac_table_write(priv, &pmac_tbl);\n+}\n+\n+/* PMAC egress configuration */\n+static int gswip_pmac_eg_cfg_set(struct device *dev,\n+\t\t\t\t struct gswip_pmac_eg_cfg *eg)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tstruct pmac_tbl_prog pmac_tbl = {0};\n+\tu16 ctrl, pmac_ctrl4;\n+\tu16 *val;\n+\n+\tpmac_ctrl4 = pmac_reg(PMAC_CTRL_4, eg->pmac_id);\n+\n+\tpmac_tbl.id = PMAC_EG_CFG;\n+\tpmac_tbl.pmac_id = eg->pmac_id;\n+\tpmac_tbl.addr = FIELD_PREP(PMAC_EGCFG_DST_PORT_ID, eg->dst_port_id)\n+\t\t\t| FIELD_PREP(PMAC_EGCFG_FLOW_ID_MSB,\n+\t\t\t\t     eg->flow_id_msb);\n+\n+\tctrl = reg_rbits(priv, pmac_ctrl4, PMAC_CTRL_4_FLAGEN);\n+\n+\tif (ctrl == PMAC_RX_FSM_IDLE) {\n+\t\tpmac_tbl.addr |= FIELD_PREP(PMAC_EGCFG_TC_4BITS, eg->tc);\n+\t} else if (ctrl == PMAC_RX_FSM_IGCFG) {\n+\t\tpmac_tbl.addr |= FIELD_PREP(PMAC_EGCFG_MPE1, eg->mpe1) |\n+\t\t\t\t FIELD_PREP(PMAC_EGCFG_MPE2, eg->mpe2) |\n+\t\t\t\t FIELD_PREP(PMAC_EGCFG_ECRYPT, eg->encrypt) |\n+\t\t\t\t FIELD_PREP(PMAC_EGCFG_DECRYPT, eg->decrypt);\n+\t} else if (ctrl == PMAC_RX_FSM_DASA) {\n+\t\tpmac_tbl.addr |= FIELD_PREP(PMAC_EGCFG_TC_2BITS, eg->tc) |\n+\t\t\t\t FIELD_PREP(PMAC_EGCFG_MPE1, eg->mpe1) |\n+\t\t\t\t FIELD_PREP(PMAC_EGCFG_MPE2, eg->mpe2);\n+\t}\n+\n+\tval = &pmac_tbl.val[0];\n+\tval[0] = FIELD_PREP(PMAC_EGCFG_VAL0_REDIR, eg->redir_en) |\n+\t\t FIELD_PREP(PMAC_EGCFG_VAL0_RES_3BITS, ctrl) |\n+\t\t   FIELD_PREP(PMAC_EGCFG_VAL0_BSL, eg->bsl_tc) |\n+\t\t   FIELD_PREP(PMAC_EGCFG_VAL0_RES_2BITS, eg->resv_2dw0);\n+\n+\tval[1] = FIELD_PREP(PMAC_EGCFG_VAL1_RX_DMA_CH, eg->rx_dma_chan_id);\n+\n+\tval[2] = FIELD_PREP(PMAC_EGCFG_VAL2_FCS_MODE, eg->fcs_en) |\n+\t\t   FIELD_PREP(PMAC_EGCFG_VAL2_PMAC_FLAG, eg->pmac_en);\n+\n+\tif (eg->rm_l2_hdr) {\n+\t\tval[2] |= PMAC_EGCFG_VAL2_L2HD_RM_MODE |\n+\t\t\t    FIELD_PREP(PMAC_EGCFG_VAL2_L2HD_RM,\n+\t\t\t\t       eg->num_byte_rm);\n+\t}\n+\n+\tpmac_tbl.num_val = PMAC_EG_CFG_TBL_VAL_NUM;\n+\n+\treturn gswip_pmac_table_write(priv, &pmac_tbl);\n+}\n+\n+static int gswip_cpu_port_cfg_get(struct device *dev,\n+\t\t\t\t  struct gswip_cpu_port_cfg *cpu)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tu16 lpid, val;\n+\n+\tlpid = cpu->lpid;\n+\tif (lpid >= priv->num_lport) {\n+\t\tdev_err(priv->dev, \"Invalid cpu port id %d > %d\\n\",\n+\t\t\tlpid, priv->num_lport);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tcpu->is_cpu_port = lpid == priv->cpu_port;\n+\tcpu->spec_tag_ig = reg_rbits(priv, PCE_PCTRL_0(lpid),\n+\t\t\t\t     PCE_PCTRL_0_IGSTEN);\n+\tcpu->fcs_chk = reg_rbits(priv, SDMA_PCTRL(lpid), SDMA_PCTRL_FCSIGN);\n+\n+\treg_r16(priv, FDMA_PASR, &val);\n+\tcpu->no_mpe_parser_cfg = FIELD_GET(FDMA_PASR_CPU, val);\n+\tcpu->mpe1_parser_cfg = FIELD_GET(FDMA_PASR_MPE1, val);\n+\tcpu->mpe2_parser_cfg = FIELD_GET(FDMA_PASR_MPE2, val);\n+\tcpu->mpe3_parser_cfg = FIELD_GET(FDMA_PASR_MPE3, val);\n+\n+\treg_r16(priv, FDMA_PCTRL(lpid), &val);\n+\tcpu->spec_tag_eg = FIELD_GET(FDMA_PCTRL_STEN, val);\n+\tcpu->ts_rm_ptp_pkt = FIELD_GET(FDMA_PCTRL_TS_PTP, val);\n+\tcpu->ts_rm_non_ptp_pkt = FIELD_GET(FDMA_PCTRL_TS_NONPTP, val);\n+\n+\treturn 0;\n+}\n+\n+static int gswip_register_get(struct device *dev, struct gswip_register *param)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\n+\treg_r16(priv, param->offset, &param->data);\n+\n+\treturn 0;\n+}\n+\n+static int gswip_register_set(struct device *dev, struct gswip_register *param)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\n+\tregmap_write(priv->regmap, param->offset, param->data);\n+\n+\treturn 0;\n+}\n+\n+/* Global Port ID/ Logical Port ID */\n+static int gswip_lpid2gpid_set(struct device *dev,\n+\t\t\t       struct gswip_lpid2gpid *lp2gp)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tu16 lpid, first_gpid, last_gpid, val;\n+\n+\tlpid = lp2gp->lpid;\n+\tfirst_gpid = lp2gp->first_gpid;\n+\tlast_gpid = first_gpid + lp2gp->num_gpid - 1;\n+\n+\tif (lpid >= priv->num_lport) {\n+\t\tdev_err(priv->dev, \"Invalid lpid %d >= %d\\n\",\n+\t\t\tlpid, priv->num_lport);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (last_gpid >= priv->num_glb_port) {\n+\t\tdev_err(priv->dev, \"Invalid last gpid %d >= %d\\n\",\n+\t\t\tlast_gpid, priv->num_glb_port);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tval = FIELD_PREP(ETHSW_GPID_STARTID_STARTID, first_gpid) |\n+\t      FIELD_PREP(ETHSW_GPID_STARTID_BITS, lp2gp->valid_bits);\n+\tregmap_write(priv->regmap, ETHSW_GPID_STARTID(lpid), val);\n+\n+\treg_wbits(priv, ETHSW_GPID_ENDID(lpid),\n+\t\t  ETHSW_GPID_ENDID_ENDID, last_gpid);\n+\n+\treturn 0;\n+}\n+\n+static int gswip_lpid2gpid_get(struct device *dev,\n+\t\t\t       struct gswip_lpid2gpid *lp2gp)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tu16 lpid, val;\n+\n+\tlpid = lp2gp->lpid;\n+\tif (lpid >= priv->num_lport) {\n+\t\tdev_err(priv->dev, \"Invalid lpid %d >= %d\\n\",\n+\t\t\tlpid, priv->num_lport);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treg_r16(priv, ETHSW_GPID_STARTID(lpid), &val);\n+\tlp2gp->first_gpid = FIELD_GET(ETHSW_GPID_STARTID_STARTID, val);\n+\tlp2gp->valid_bits = FIELD_GET(ETHSW_GPID_STARTID_BITS, val);\n+\n+\treg_r16(priv, ETHSW_GPID_ENDID(lpid), &val);\n+\tlp2gp->num_gpid = val - lp2gp->first_gpid + 1;\n+\n+\treturn 0;\n+}\n+\n+static int gswip_gpid2lpid_set(struct device *dev,\n+\t\t\t       struct gswip_gpid2lpid *gp2lp)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tu16 val = 0;\n+\n+\tif (gp2lp->lpid >= priv->num_lport) {\n+\t\tdev_err(priv->dev, \"Invalid lpid %d >= %d\\n\",\n+\t\t\tgp2lp->lpid, priv->num_lport);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (gp2lp->gpid >= priv->num_glb_port) {\n+\t\tdev_err(priv->dev, \"Invalid gpid %d >= %d\\n\",\n+\t\t\tgp2lp->gpid, priv->num_glb_port);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tval = FIELD_PREP(GPID_RAM_VAL_LPID, gp2lp->lpid) |\n+\t      FIELD_PREP(GPID_RAM_VAL_SUBID_GRP, gp2lp->subif_grp_field) |\n+\t      FIELD_PREP(GPID_RAM_VAL_OV, gp2lp->subif_grp_field_ovr);\n+\n+\tregmap_write(priv->regmap, GPID_RAM_VAL, val);\n+\n+\tif (tbl_rw_tmout(priv, GPID_RAM_CTRL, GPID_RAM_CTRL_BAS)) {\n+\t\tdev_err(priv->dev, \"failed to access gpid table\\n\");\n+\t\treturn -EBUSY;\n+\t}\n+\n+\treg_r16(priv, GPID_RAM_CTRL, &val);\n+\n+\tupdate_val(&val, GPID_RAM_CTRL_ADDR, gp2lp->gpid);\n+\tval |= FIELD_PREP(GPID_RAM_CTRL_OPMOD, 1) |\n+\t       FIELD_PREP(GPID_RAM_CTRL_BAS, 1);\n+\n+\tregmap_write(priv->regmap, GPID_RAM_CTRL, val);\n+\n+\tif (tbl_rw_tmout(priv, GPID_RAM_CTRL, GPID_RAM_CTRL_BAS)) {\n+\t\tdev_err(priv->dev, \"failed to write gpid table\\n\");\n+\t\treturn -EBUSY;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int gswip_gpid2lpid_get(struct device *dev,\n+\t\t\t       struct gswip_gpid2lpid *gp2lp)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tu16 val;\n+\n+\tif (gp2lp->gpid >= priv->num_glb_port) {\n+\t\tdev_err(priv->dev, \"gpid %d >= %d\\n\",\n+\t\t\tgp2lp->gpid, priv->num_glb_port);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (tbl_rw_tmout(priv, GPID_RAM_CTRL, GPID_RAM_CTRL_BAS)) {\n+\t\tdev_err(priv->dev, \"failed to access gpid table\\n\");\n+\t\treturn -EBUSY;\n+\t}\n+\n+\treg_r16(priv, GPID_RAM_CTRL, &val);\n+\n+\tupdate_val(&val, GPID_RAM_CTRL_ADDR, gp2lp->gpid);\n+\tval |= FIELD_PREP(GPID_RAM_CTRL_OPMOD, 0) |\n+\t       FIELD_PREP(GPID_RAM_CTRL_BAS, 1);\n+\n+\tregmap_write(priv->regmap, GPID_RAM_CTRL, val);\n+\n+\tif (tbl_rw_tmout(priv, GPID_RAM_CTRL, GPID_RAM_CTRL_BAS)) {\n+\t\tdev_err(priv->dev, \"failed to read gpid table\\n\");\n+\t\treturn -EBUSY;\n+\t}\n+\n+\treg_r16(priv, GPID_RAM_VAL, &val);\n+\n+\tgp2lp->lpid = FIELD_GET(GPID_RAM_VAL_LPID, val);\n+\tgp2lp->subif_grp_field = FIELD_GET(GPID_RAM_VAL_SUBID_GRP, val);\n+\tgp2lp->subif_grp_field_ovr = FIELD_GET(GPID_RAM_VAL_OV, val);\n+\n+\treturn 0;\n+}\n+\n+static int gswip_enable(struct device *dev, bool enable)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tu16 i;\n+\n+\tfor (i = 0; i < priv->num_lport; i++) {\n+\t\treg_wbits(priv, FDMA_PCTRL(i), FDMA_PCTRL_EN, enable);\n+\t\treg_wbits(priv, SDMA_PCTRL(i), SDMA_PCTRL_PEN, enable);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct core_common_ops gswip_core_common_ops = {\n+\t.enable = gswip_enable,\n+\t.cpu_port_cfg_get = gswip_cpu_port_cfg_get,\n+\t.reg_get = gswip_register_get,\n+\t.reg_set = gswip_register_set,\n+};\n+\n+static const struct core_pmac_ops gswip_core_pmac_ops = {\n+\t.gbl_cfg_set = gswip_pmac_glb_cfg_set,\n+\t.bp_map_get = gswip_pmac_bp_map_get,\n+\t.ig_cfg_set = gswip_pmac_ig_cfg_set,\n+\t.eg_cfg_set = gswip_pmac_eg_cfg_set,\n+};\n+\n+static const struct core_gpid_ops gswip_core_gpid_ops = {\n+\t.lpid2gpid_set = gswip_lpid2gpid_set,\n+\t.lpid2gpid_get = gswip_lpid2gpid_get,\n+\t.gpid2lpid_set = gswip_gpid2lpid_set,\n+\t.gpid2lpid_get = gswip_gpid2lpid_get,\n+};\n+\n+static int gswip_core_setup_ops(struct gswip_core_priv *priv)\n+{\n+\tstruct core_ops *ops =  &priv->ops;\n+\n+\tops->common_ops = &gswip_core_common_ops;\n+\tops->pmac_ops = &gswip_core_pmac_ops;\n+\tops->gpid_ops = &gswip_core_gpid_ops;\n+\n+\treturn 0;\n+}\n+\n+static int gswip_core_get_hw_cap(struct gswip_core_priv *priv)\n+{\n+\tu16 val;\n+\n+\tpriv->ver = reg_rbits(priv, ETHSW_VERSION, ETHSW_VERSION_REV_ID);\n+\tif (priv->ver != GSWIP_VER) {\n+\t\tdev_err(priv->dev, \"Wrong hardware ip version %d\\n\",\n+\t\t\tpriv->ver);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpriv->num_phy_port = reg_rbits(priv, ETHSW_CAP_1, ETHSW_CAP_1_PPORTS);\n+\n+\treg_r16(priv, ETHSW_CAP_1, &val);\n+\tpriv->num_lport = priv->num_phy_port;\n+\tpriv->num_lport += FIELD_GET(ETHSW_CAP_1_VPORTS, val);\n+\tpriv->num_q = FIELD_GET(ETHSW_CAP_1_QUEUE, val);\n+\n+\tpriv->num_pmac = reg_rbits(priv, ETHSW_CAP_13, ETHSW_CAP_13_PMAC);\n+\n+\treg_r16(priv, ETHSW_CAP_17, &val);\n+\tpriv->num_br = (1 << FIELD_GET(ETHSW_CAP_17_BRG, val));\n+\tpriv->num_br_port = (1 << FIELD_GET(ETHSW_CAP_17_BRGPT, val));\n+\n+\treg_r16(priv, ETHSW_CAP_18, &priv->num_ctp);\n+\n+\tpriv->num_glb_port = priv->num_br_port * 2;\n+\n+\treturn 0;\n+}\n+\n+static int gswip_core_init(struct gswip_core_priv *priv)\n+{\n+\tpriv->br_map = devm_kzalloc(priv->dev, BITS_TO_LONGS(priv->num_br),\n+\t\t\t\t    GFP_KERNEL);\n+\tif (!priv->br_map)\n+\t\treturn -ENOMEM;\n+\n+\tpriv->br_port_map = devm_kzalloc(priv->dev,\n+\t\t\t\t\t BITS_TO_LONGS(priv->num_br_port),\n+\t\t\t\t\t GFP_KERNEL);\n+\tif (!priv->br_port_map)\n+\t\treturn -ENOMEM;\n+\n+\tpriv->ctp_port_map = devm_kzalloc(priv->dev,\n+\t\t\t\t\t  BITS_TO_LONGS(priv->num_ctp),\n+\t\t\t\t\t  GFP_KERNEL);\n+\tif (!priv->ctp_port_map)\n+\t\treturn -ENOMEM;\n+\n+\tspin_lock_init(&priv->tbl_lock);\n+\n+\tgswip_core_setup_ops(priv);\n+\tgswip_core_setup_port_ops(priv);\n+\n+\treturn 0;\n+}\n+\n+static int gswip_core_setup(struct gswip_core_priv *priv)\n+{\n+\tint ret;\n+\n+\tret = gswip_core_set_def_eg_pce_bypass_qmap(priv,\n+\t\t\t\t\t\t    GSWIP_QOS_QMAP_SINGLE_MD);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = gswip_core_set_def_ig_pce_bypass_qmap(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = gswip_core_pmac_init_nondpu(priv);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int gswip_core_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct device *parent = dev->parent;\n+\tstruct gswip_core_priv *priv;\n+\tstruct gswip_pdata *pdata = parent->platform_data;\n+\tint ret;\n+\n+\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tpriv->pdev = pdev;\n+\tpriv->dev = dev;\n+\tpriv->regmap = pdata->core_regmap;\n+\n+\tplatform_set_drvdata(pdev, priv);\n+\n+\tret = gswip_core_get_hw_cap(priv);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\tret = gswip_core_init(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = gswip_core_setup(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id gswip_core_of_match_table[] = {\n+\t{ .compatible = \"gswip-core\" },\n+\t{}\n+};\n+\n+MODULE_DEVICE_TABLE(of, gswip_core);\n+\n+static struct platform_driver gswip_core_drv = {\n+\t.probe = gswip_core_probe,\n+\t.driver = {\n+\t\t.name = \"gswip_core\",\n+\t\t.of_match_table = gswip_core_of_match_table,\n+\t},\n+};\n+\n+module_platform_driver(gswip_core_drv);\n+\n+MODULE_LICENSE(\"GPL v2\");\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/gswip_core.h b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_core.h\nnew file mode 100644\nindex 000000000000..614a9089c1b0\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_core.h\n@@ -0,0 +1,90 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2016-2019 Intel Corporation. */\n+#ifndef _GSWIP_CORE_H_\n+#define _GSWIP_CORE_H_\n+\n+#include <linux/bitfield.h>\n+#include <linux/delay.h>\n+#include <linux/regmap.h>\n+\n+#include \"gswip.h\"\n+\n+/* table should be ready in 30 clock cycle */\n+#define TBL_BUSY_TIMEOUT_US\t1\n+\n+struct core_ops {\n+\tconst struct core_common_ops *common_ops;\n+\tconst struct core_pmac_ops *pmac_ops;\n+\tconst struct core_gpid_ops *gpid_ops;\n+\tconst struct core_ctp_ops *ctp_ops;\n+\tconst struct core_br_port_ops *br_port_ops;\n+\tconst struct core_br_ops *br_ops;\n+\tconst struct core_qos_ops *qos_ops;\n+};\n+\n+struct gswip_core_priv {\n+\tstruct device *dev;\n+\n+\tunsigned long *br_map;\n+\tunsigned long *br_port_map;\n+\tunsigned long *ctp_port_map;\n+\tvoid *pdev;\n+\n+\tu8 cpu_port;\n+\tu8 num_lport;\n+\tu8 num_br;\n+\tu8 num_br_port;\n+\tu16 num_ctp;\n+\tu16 num_glb_port;\n+\tu16 num_pmac;\n+\tu16 num_phy_port;\n+\tu16 num_q;\n+\n+\tu16 ver;\n+\tstruct regmap *regmap;\n+\t/* table read/write lock */\n+\tspinlock_t tbl_lock;\n+\n+\tstruct core_ops ops;\n+};\n+\n+static inline void update_val(u16 *val, u16 mask, u16 set)\n+{\n+\t*val &= ~mask;\n+\t*val |= FIELD_PREP(mask, set);\n+}\n+\n+static inline void reg_r16(struct gswip_core_priv *priv, u16 reg, u16 *val)\n+{\n+\tunsigned int reg_val;\n+\n+\tregmap_read(priv->regmap, reg, &reg_val);\n+\t*val = reg_val;\n+}\n+\n+static inline void reg_wbits(struct gswip_core_priv *priv,\n+\t\t\t     u16 reg, u16 mask, u16 val)\n+{\n+\tregmap_update_bits(priv->regmap, reg, mask, FIELD_PREP(mask, val));\n+}\n+\n+static inline u16 reg_rbits(struct gswip_core_priv *priv, u16 reg, u16 mask)\n+{\n+\tunsigned int reg_val;\n+\n+\tregmap_read(priv->regmap, reg, &reg_val);\n+\treturn FIELD_GET(mask, reg_val);\n+}\n+\n+/* Access table with timeout */\n+static inline int tbl_rw_tmout(struct gswip_core_priv *priv, u16 reg, u16 mask)\n+{\n+\tunsigned int val;\n+\n+\treturn regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask),\n+\t\t\t\t\t0, TBL_BUSY_TIMEOUT_US);\n+}\n+\n+int gswip_core_setup_port_ops(struct gswip_core_priv *priv);\n+\n+#endif\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/gswip_dev.c b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_dev.c\nnew file mode 100644\nindex 000000000000..492e0dfd7159\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_dev.c\n@@ -0,0 +1,179 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2016-2019 Intel Corporation. */\n+\n+#include <linux/clk.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_address.h>\n+#include <linux/of_platform.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+#include <linux/reset.h>\n+\n+#include \"gswip.h\"\n+#include \"gswip_dev.h\"\n+\n+#define GSWIP_SUBDEV_MAC_MAX\t9\n+#define GSWIP_SUBDEV_CORE_MAX\t1\n+#define GSWIP_MAC_DEV_NAME\t\"gswip_mac\"\n+#define GSWIP_CORE_DEV_NAME\t\"gswip_core\"\n+\n+struct gswip_priv {\n+\tstruct device *dev;\n+\tu32 id;\n+\tint num_subdev_mac;\n+\tint num_subdev_core;\n+\tstruct gswip_pdata pdata;\n+};\n+\n+static int regmap_reg_write(void *context, unsigned int reg, unsigned int val)\n+{\n+\tstruct gswip_pdata *pdata = context;\n+\n+\twritew(val, pdata->core + reg);\n+\n+\treturn 0;\n+}\n+\n+static int regmap_reg_read(void *context, unsigned int reg, unsigned int *val)\n+{\n+\tstruct gswip_pdata *pdata = context;\n+\n+\t*val = readw(pdata->core + reg);\n+\n+\treturn 0;\n+}\n+\n+static const struct regmap_config gswip_core_regmap_config = {\n+\t.reg_bits = 16,\n+\t.val_bits = 16,\n+\t.reg_stride = 4,\n+\t.reg_write = regmap_reg_write,\n+\t.reg_read = regmap_reg_read,\n+\t.fast_io = true,\n+};\n+\n+static int np_gswip_parse_dt(struct platform_device *pdev,\n+\t\t\t     struct gswip_priv *priv)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct device_node *node = dev->of_node;\n+\tstruct gswip_pdata *pdata = &priv->pdata;\n+\tstruct device_node *np;\n+\n+\tpdata->sw = devm_platform_ioremap_resource_byname(pdev, \"switch\");\n+\tif (IS_ERR(pdata->sw))\n+\t\treturn PTR_ERR(pdata->sw);\n+\n+\tpdata->lmac = devm_platform_ioremap_resource_byname(pdev, \"lmac\");\n+\tif (IS_ERR(pdata->lmac))\n+\t\treturn PTR_ERR(pdata->lmac);\n+\n+\tpdata->core = devm_platform_ioremap_resource_byname(pdev, \"core\");\n+\tif (IS_ERR(pdata->core))\n+\t\treturn PTR_ERR(pdata->core);\n+\tpdata->core_regmap = devm_regmap_init(dev, NULL, pdata,\n+\t\t\t\t\t      &gswip_core_regmap_config);\n+\tif (IS_ERR(pdata->core_regmap))\n+\t\treturn PTR_ERR(pdata->core_regmap);\n+\n+\tpdata->sw_irq = platform_get_irq_byname(pdev, \"switch\");\n+\tif (pdata->sw_irq < 0)\n+\t\treturn -ENODEV;\n+\n+\tpdata->core_irq = platform_get_irq_byname(pdev, \"core\");\n+\tif (pdata->core_irq < 0)\n+\t\treturn -ENODEV;\n+\n+\tpdata->ptp_clk = devm_clk_get(dev, \"ptp\");\n+\tif (IS_ERR(pdata->ptp_clk))\n+\t\treturn PTR_ERR(pdata->ptp_clk);\n+\n+\tpdata->sw_clk = devm_clk_get(dev, \"switch\");\n+\tif (IS_ERR(pdata->sw_clk))\n+\t\treturn PTR_ERR(pdata->sw_clk);\n+\n+\tfor_each_node_by_name(node, GSWIP_MAC_DEV_NAME) {\n+\t\tpriv->num_subdev_mac++;\n+\t\tif (priv->num_subdev_mac > GSWIP_SUBDEV_MAC_MAX) {\n+\t\t\tdev_err(dev, \"too many GSWIP mac subdevices\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (!priv->num_subdev_mac) {\n+\t\tdev_err(dev, \"GSWIP mac subdevice not found\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tnp = of_find_node_by_name(node, GSWIP_CORE_DEV_NAME);\n+\tif (np) {\n+\t\tpriv->num_subdev_core++;\n+\t\tof_node_put(np);\n+\t} else {\n+\t\tdev_err(dev, \"GSWIP core subdevice not found\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id gswip_of_match_table[] = {\n+\t{ .compatible = \"intel,lgm-gswip\" },\n+\t{}\n+};\n+MODULE_DEVICE_TABLE(of, gswip_of_match_table);\n+\n+static int np_gswip_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct reset_control *rcu_reset;\n+\tstruct gswip_priv *priv;\n+\tint ret;\n+\n+\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tpriv->dev = dev;\n+\n+\tret = np_gswip_parse_dt(pdev, priv);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to parse device tree\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tdev->id = priv->id;\n+\n+\trcu_reset = devm_reset_control_get_optional(dev, NULL);\n+\tif (IS_ERR(rcu_reset)) {\n+\t\tdev_err(dev, \"error getting reset control of gswip\\n\");\n+\t\treturn PTR_ERR(rcu_reset);\n+\t}\n+\n+\treset_control_assert(rcu_reset);\n+\tudelay(1);\n+\treset_control_deassert(rcu_reset);\n+\n+\tdev_set_drvdata(dev, priv);\n+\n+\tdev->platform_data = &priv->pdata;\n+\n+\tret = devm_of_platform_populate(dev);\n+\n+\treturn ret;\n+}\n+\n+static struct platform_driver np_gswip_driver = {\n+\t.probe = np_gswip_probe,\n+\t.driver = {\n+\t\t.name = \"np_gswip\",\n+\t\t.of_match_table = gswip_of_match_table,\n+\t},\n+};\n+\n+module_platform_driver(np_gswip_driver);\n+\n+MODULE_LICENSE(\"GPL v2\");\n+\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/gswip_dev.h b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_dev.h\nnew file mode 100644\nindex 000000000000..bdf5f26bc2ce\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_dev.h\n@@ -0,0 +1,19 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2016-2019 Intel Corporation. */\n+#ifndef _GSWIP_DEV_H\n+#define _GSWIP_DEV_H\n+\n+struct gswip_pdata {\n+\tvoid __iomem *sw;\n+\tvoid __iomem *lmac;\n+\tvoid __iomem *core;\n+\tint sw_irq;\n+\tint core_irq;\n+\tstruct clk *ptp_clk;\n+\tstruct clk *sw_clk;\n+\tbool intr_flag;\n+\tstruct regmap *core_regmap;\n+};\n+\n+#endif\n+\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/gswip_mac.c b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_mac.c\nnew file mode 100644\nindex 000000000000..eb8c8049a77f\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_mac.c\n@@ -0,0 +1,225 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2016-2019 Intel Corporation. */\n+\n+#include <linux/bitfield.h>\n+#include <linux/types.h>\n+\n+#include \"mac_common.h\"\n+\n+int sw_core_enable(struct device *dev, u32 val)\n+{\n+\tstruct gswip_mac *priv = dev_get_drvdata(dev);\n+\tu32 reg;\n+\n+\tspin_lock_bh(&priv->sw_lock);\n+\treg = sw_read(priv, GSWIP_CFG);\n+\treg &= ~GSWIP_CFG_CORE_SE_EN;\n+\treg |= FIELD_PREP(GSWIP_CFG_CORE_SE_EN, val);\n+\tsw_write(priv, GSWIP_CFG, reg);\n+\tspin_unlock_bh(&priv->sw_lock);\n+\n+\treturn 0;\n+}\n+\n+int sw_set_mac_rxfcs_op(struct gswip_mac *priv, u32 val)\n+{\n+\tu32 mac_op_cfg;\n+\n+\tmac_op_cfg = sw_read(priv, MAC_OP_CFG_REG(priv->mac_idx));\n+\tif (FIELD_GET(MAC_OP_CFG_RX_FCS, mac_op_cfg) != val) {\n+\t\tmac_op_cfg &= ~MAC_OP_CFG_RX_FCS;\n+\t\tmac_op_cfg |= FIELD_PREP(MAC_OP_CFG_RX_FCS, val);\n+\t\tsw_write(priv, MAC_OP_CFG_REG(priv->mac_idx), mac_op_cfg);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int sw_set_eee_cap(struct gswip_mac *priv, u32 val)\n+{\n+\tu32 aneg_eee;\n+\n+\taneg_eee = sw_read(priv, ANEG_EEE_REG(priv->mac_idx));\n+\taneg_eee &= ~ANEG_EEE_CAP;\n+\taneg_eee |= FIELD_PREP(ANEG_EEE_CAP, val);\n+\tsw_write(priv, ANEG_EEE_REG(priv->mac_idx), aneg_eee);\n+\n+\treturn 0;\n+}\n+\n+int sw_set_fe_intf(struct gswip_mac *priv, u32 macif)\n+{\n+\tu32 mac_if_cfg;\n+\n+\tmac_if_cfg = sw_read(priv, MAC_IF_CFG_REG(priv->mac_idx));\n+\n+\tif (macif == LMAC_MII)\n+\t\tmac_if_cfg &= ~MAC_IF_CFG_CFGFE;\n+\telse\n+\t\tmac_if_cfg |= MAC_IF_CFG_CFGFE;\n+\n+\tsw_write(priv, MAC_IF_CFG_REG(priv->mac_idx), mac_if_cfg);\n+\n+\treturn 0;\n+}\n+\n+int sw_set_1g_intf(struct gswip_mac *priv, u32 macif)\n+{\n+\tu32 mac_if_cfg;\n+\n+\tmac_if_cfg = sw_read(priv, MAC_IF_CFG_REG(priv->mac_idx));\n+\n+\tif (macif == LMAC_GMII)\n+\t\tmac_if_cfg &= ~MAC_IF_CFG_CFG1G;\n+\telse\n+\t\tmac_if_cfg |= MAC_IF_CFG_CFG1G;\n+\n+\tsw_write(priv, MAC_IF_CFG_REG(priv->mac_idx), mac_if_cfg);\n+\n+\treturn 0;\n+}\n+\n+int sw_set_2G5_intf(struct gswip_mac *priv, u32 macif)\n+{\n+\tu32 mac_if_cfg;\n+\n+\tmac_if_cfg = sw_read(priv, MAC_IF_CFG_REG(priv->mac_idx));\n+\n+\tif (macif == XGMAC_GMII)\n+\t\tmac_if_cfg &= ~MAC_IF_CFG_CFG2G5;\n+\telse\n+\t\tmac_if_cfg |= MAC_IF_CFG_CFG2G5;\n+\n+\tsw_write(priv, MAC_IF_CFG_REG(priv->mac_idx), mac_if_cfg);\n+\n+\treturn 0;\n+}\n+\n+int sw_set_speed(struct gswip_mac *priv, u8 speed)\n+{\n+\tu16 phy_mode = 0;\n+\tu8 speed_msb = 0, speed_lsb = 0;\n+\n+\tphy_mode = sw_read(priv, PHY_MODE_REG(priv->mac_idx));\n+\n+\t/* clear first */\n+\tphy_mode &= ~PHY_MODE_SPEED_MSB & ~PHY_MODE_SPEED_LSB;\n+\n+\tspeed_msb = FIELD_GET(SPEED_MSB, speed);\n+\tspeed_lsb = FIELD_GET(SPEED_LSB, speed);\n+\tphy_mode |= FIELD_PREP(PHY_MODE_SPEED_MSB, speed_msb);\n+\tphy_mode |= FIELD_PREP(PHY_MODE_SPEED_LSB, speed_lsb);\n+\n+\tsw_write(priv, PHY_MODE_REG(priv->mac_idx), phy_mode);\n+\n+\treturn 0;\n+}\n+\n+int sw_set_duplex_mode(struct gswip_mac *priv, u32 val)\n+{\n+\tu16 phy_mode;\n+\n+\tphy_mode = sw_read(priv, PHY_MODE_REG(priv->mac_idx));\n+\tif (FIELD_GET(PHY_MODE_FDUP, phy_mode) != val) {\n+\t\tphy_mode &= ~PHY_MODE_FDUP;\n+\t\tphy_mode |= FIELD_PREP(PHY_MODE_FDUP, val);\n+\t\tsw_write(priv, PHY_MODE_REG(priv->mac_idx), phy_mode);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int sw_get_duplex_mode(struct gswip_mac *priv)\n+{\n+\tu16 phy_mode;\n+\tint val;\n+\n+\tphy_mode = sw_read(priv, PHY_STAT_REG(priv->mac_idx));\n+\tval = FIELD_GET(PHY_STAT_FDUP, phy_mode);\n+\n+\treturn val;\n+}\n+\n+int sw_get_linkstatus(struct gswip_mac *priv)\n+{\n+\tu16 phy_mode;\n+\tint linkst;\n+\n+\tphy_mode = sw_read(priv, PHY_STAT_REG(priv->mac_idx));\n+\tlinkst = FIELD_GET(PHY_STAT_LSTAT, phy_mode);\n+\n+\treturn linkst;\n+}\n+\n+int sw_set_linkstatus(struct gswip_mac *priv, u8 linkst)\n+{\n+\tu16 phy_mode;\n+\tu8 val;\n+\n+\tphy_mode = sw_read(priv, PHY_MODE_REG(priv->mac_idx));\n+\tval = FIELD_GET(PHY_MODE_LINKST, phy_mode);\n+\tif (val != linkst) {\n+\t\tphy_mode &= ~PHY_MODE_LINKST;\n+\t\tphy_mode |= FIELD_PREP(PHY_MODE_LINKST, linkst);\n+\t\tsw_write(priv, PHY_MODE_REG(priv->mac_idx), phy_mode);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int sw_set_flowctrl(struct gswip_mac *priv, u8 val, u32 mode)\n+{\n+\tu16 phy_mode;\n+\n+\tphy_mode = sw_read(priv, PHY_MODE_REG(priv->mac_idx));\n+\n+\tswitch (mode) {\n+\tcase FCONRX:\n+\t\tphy_mode &= ~PHY_MODE_FCONRX;\n+\t\tphy_mode |= FIELD_PREP(PHY_MODE_FCONRX, val);\n+\t\tbreak;\n+\n+\tcase FCONTX:\n+\t\tphy_mode &= ~PHY_MODE_FCONTX;\n+\t\tphy_mode |= FIELD_PREP(PHY_MODE_FCONTX, val);\n+\t\tbreak;\n+\t}\n+\n+\tsw_write(priv, PHY_MODE_REG(priv->mac_idx), phy_mode);\n+\n+\treturn 0;\n+}\n+\n+u32 sw_get_speed(struct gswip_mac *priv)\n+{\n+\tu16 phy_mode = 0;\n+\tu32 speed_msb, speed_lsb, speed;\n+\n+\tphy_mode = sw_read(priv, PHY_STAT_REG(priv->mac_idx));\n+\tspeed_msb = FIELD_GET(PHY_STAT_SPEED_MSB, phy_mode);\n+\tspeed_lsb = FIELD_GET(PHY_STAT_SPEED_LSB, phy_mode);\n+\tspeed = (speed_msb << 2) | speed_lsb;\n+\n+\treturn speed;\n+}\n+\n+u32 sw_mac_get_mtu(struct gswip_mac *priv)\n+{\n+\tu32 reg, val;\n+\n+\treg = sw_read(priv, MAC_MTU_CFG_REG(priv->mac_idx));\n+\tval = FIELD_PREP(MAC_MTU_CFG_MTU, reg);\n+\n+\treturn val;\n+}\n+\n+int sw_mac_set_mtu(struct gswip_mac *priv, u32 mtu)\n+{\n+\tu32 val;\n+\n+\tval = sw_mac_get_mtu(priv);\n+\tif (val != mtu)\n+\t\tsw_write(priv, MAC_MTU_CFG_REG(priv->mac_idx), mtu);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/gswip_port.c b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_port.c\nnew file mode 100644\nindex 000000000000..1fd611db9ffc\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_port.c\n@@ -0,0 +1,330 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2016-2019 Intel Corporation.*/\n+#include \"gswip_core.h\"\n+#include \"gswip_reg.h\"\n+#include \"gswip_tbl.h\"\n+\n+#define ENABLE\t\t1\n+#define DISABLE\t\t0\n+\n+static int gswip_ctp_port_set(struct gswip_core_priv *priv,\n+\t\t\t      struct gswip_ctp_port_info *ctp)\n+{\n+\tu16 val, last_port;\n+\n+\tval = ctp->first_pid;\n+\tlast_port = ctp->first_pid + ctp->num_port - 1;\n+\n+\tswitch (ctp->mode) {\n+\tcase GSWIP_LPORT_8BIT_WLAN:\n+\t\tval |= FIELD_PREP(ETHSW_CTP_STARTID_MD, MD_WLAN8);\n+\t\tbreak;\n+\n+\tcase GSWIP_LPORT_9BIT_WLAN:\n+\t\tval |= FIELD_PREP(ETHSW_CTP_STARTID_MD, MD_WLAN8);\n+\t\tbreak;\n+\tcase GSWIP_LPORT_GPON:\n+\tcase GSWIP_LPORT_EPON:\n+\tcase GSWIP_LPORT_GINT:\n+\tcase GSWIP_LPORT_OTHER:\n+\t\tval |= FIELD_PREP(ETHSW_CTP_STARTID_MD, MD_OTHER);\n+\t\tbreak;\n+\t}\n+\n+\tregmap_write(priv->regmap, ETHSW_CTP_STARTID(ctp->lpid), val);\n+\tregmap_write(priv->regmap, ETHSW_CTP_ENDID(ctp->lpid), last_port);\n+\n+\treturn 0;\n+}\n+\n+static int gswip_ctp_port_get(struct gswip_core_priv *priv,\n+\t\t\t      struct gswip_ctp_port_info *ctp)\n+{\n+\tu16 val, last_port;\n+\n+\treg_r16(priv, ETHSW_CTP_STARTID(ctp->lpid), &val);\n+\n+\tctp->mode = FIELD_GET(ETHSW_CTP_STARTID_MD, val);\n+\tctp->first_pid = FIELD_GET(ETHSW_CTP_STARTID_STARTID, val);\n+\n+\tlast_port = reg_rbits(priv, ETHSW_CTP_ENDID(ctp->lpid),\n+\t\t\t      ETHSW_CTP_ENDID_ENDID);\n+\tctp->num_port = last_port - ctp->first_pid + 1;\n+\n+\treturn 0;\n+}\n+\n+static int gswip_ctp_port_alloc(struct device *dev,\n+\t\t\t\tstruct gswip_ctp_port_info *ctp)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tu16 first_ctp;\n+\tint ret;\n+\n+\tif (!ctp->num_port || ctp->num_port >= priv->num_ctp) {\n+\t\tdev_err(priv->dev, \"Invalid num of ctp port requested %d\\n\",\n+\t\t\tctp->num_port);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfirst_ctp = bitmap_find_next_zero_area(priv->ctp_port_map,\n+\t\t\t\t\t       priv->num_ctp, 0,\n+\t\t\t\t\t       ctp->num_port, 0);\n+\tif (first_ctp >= priv->num_ctp) {\n+\t\tdev_err(priv->dev, \"Failed to find contiguous ctp port\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tbitmap_set(priv->ctp_port_map, first_ctp, ctp->num_port);\n+\tctp->first_pid = first_ctp;\n+\n+\tret = gswip_ctp_port_set(priv, ctp);\n+\tif (ret) {\n+\t\tbitmap_clear(priv->ctp_port_map, first_ctp, ctp->num_port);\n+\t\treturn ret;\n+\t}\n+\n+\treg_wbits(priv, SDMA_PCTRL(ctp->lpid), SDMA_PCTRL_PEN, ENABLE);\n+\n+\treturn 0;\n+}\n+\n+static int gswip_ctp_port_free(struct device *dev, u8 lpid)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tstruct gswip_ctp_port_info ctp;\n+\n+\tif (lpid >= priv->num_lport) {\n+\t\tdev_err(priv->dev, \"Invalid lpid %d\\n\", lpid);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tctp.lpid = lpid;\n+\tgswip_ctp_port_get(priv, &ctp);\n+\n+\treg_wbits(priv, SDMA_PCTRL(lpid), SDMA_PCTRL_PEN, DISABLE);\n+\tregmap_write(priv->regmap, ETHSW_CTP_STARTID(lpid), 0);\n+\tregmap_write(priv->regmap, ETHSW_CTP_ENDID(lpid), 0);\n+\n+\tbitmap_clear(priv->ctp_port_map, ctp.first_pid, ctp.num_port);\n+\n+\treturn 0;\n+}\n+\n+static int gswip_bridge_port_alloc(struct device *dev,\n+\t\t\t\t   struct gswip_br_port_alloc *bp)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tstruct pce_tbl_prog pce_tbl = {0};\n+\tint ret;\n+\n+\tbp->br_pid = find_first_zero_bit(priv->br_port_map, priv->num_br_port);\n+\tif (bp->br_pid >= priv->num_br_port) {\n+\t\tdev_err(priv->dev, \"failed to alloc bridge port\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tset_bit(bp->br_pid, priv->br_port_map);\n+\n+\tpce_tbl.id = PCE_IG_BRP_CFG;\n+\tpce_tbl.addr = bp->br_pid;\n+\tpce_tbl.val[4] = PCE_MAC_LIMIT_NUM |\n+\t\t\t FIELD_PREP(PCE_IGBGP_VAL4_BR_ID, bp->br_id);\n+\n+\tret = gswip_pce_table_write(priv, &pce_tbl);\n+\tif (ret) {\n+\t\tclear_bit(bp->br_pid, priv->br_port_map);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int gswip_bridge_port_free(struct device *dev,\n+\t\t\t\t  struct gswip_br_port_alloc *bp)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tstruct pce_tbl_prog pce_tbl = {0};\n+\tu16 br_pid;\n+\tint ret;\n+\n+\tbr_pid = bp->br_pid;\n+\tif (br_pid >= priv->num_br_port) {\n+\t\tdev_err(priv->dev, \"brige port id %d >=%d\\n\",\n+\t\t\tbr_pid, priv->num_br_port);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!test_bit(br_pid, priv->br_port_map)) {\n+\t\tdev_err(priv->dev, \"bridge port id %d is not in used\\n\",\n+\t\t\tbr_pid);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpce_tbl.id = PCE_IG_BRP_CFG;\n+\tpce_tbl.addr = br_pid;\n+\tpce_tbl.val[4] = PCE_MAC_LIMIT_NUM;\n+\n+\tret = gswip_pce_table_write(priv, &pce_tbl);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tclear_bit(br_pid, priv->br_port_map);\n+\n+\treturn 0;\n+}\n+\n+static int gswip_bridge_alloc(struct device *dev, struct gswip_br_alloc *br)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\n+\tbr->br_id = find_first_zero_bit(priv->br_map, priv->num_br);\n+\tif (br->br_id >= priv->num_br) {\n+\t\tdev_err(priv->dev, \"failed to alloc bridge\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tset_bit(br->br_id, priv->br_map);\n+\n+\treturn 0;\n+}\n+\n+static int gswip_bridge_free(struct device *dev, struct gswip_br_alloc *br)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tstruct pce_tbl_prog pce_tbl = {0};\n+\tu16 br_id;\n+\tint ret;\n+\n+\tif (br->br_id >= priv->num_br) {\n+\t\tdev_err(priv->dev, \"bridge id %d >= %d\\n\",\n+\t\t\tbr->br_id, priv->num_br);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tbr_id = br->br_id;\n+\tif (!test_bit(br_id, priv->br_map)) {\n+\t\tdev_err(priv->dev, \"bridge id %d not allocated\\n\", br_id);\n+\t\treturn 0;\n+\t}\n+\n+\tpce_tbl.id = PCE_BR_CFG;\n+\tpce_tbl.addr = br_id;\n+\tpce_tbl.val[0] = PCE_MAC_LIMIT_NUM;\n+\n+\tret = gswip_pce_table_write(priv, &pce_tbl);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tclear_bit(br_id, priv->br_map);\n+\n+\treturn 0;\n+}\n+\n+/* Set queue for a logical port based on egress/ingress packet.\n+ * Then map the queue to an egress port.\n+ *  +----------------------+               +---------------------+\n+ *  | ingress logical port | -> queue/s -> | egress logical port |\n+ *  +----------------------+               +---------------------+\n+ */\n+static int gswip_qos_q_port_set(struct device *dev,\n+\t\t\t\tstruct gswip_qos_q_port *qport)\n+{\n+\tstruct gswip_core_priv *priv = dev_get_drvdata(dev);\n+\tstruct pce_tbl_prog pce_tbl = {0};\n+\tstruct bm_tbl_prog bm_tbl = {0};\n+\tu16 eg_port, val;\n+\tu8 qid;\n+\tint ret;\n+\n+\tqid = qport->qid;\n+\n+\tif (qport->egress) {\n+\t\t/* Egress packet always bypass PCE.\n+\t\t * Queue identifier is set in the SDMA_BYPASS register\n+\t\t * for each logical port.\n+\t\t */\n+\t\treg_r16(priv, SDMA_BYPASS(qport->lpid), &val);\n+\n+\t\tif (!qport->extration_en) {\n+\t\t\tif (qport->q_map_mode == GSWIP_QOS_QMAP_SINGLE_MD)\n+\t\t\t\tval |= FIELD_PREP(SDMA_BYPASS_MD, 1);\n+\t\t\telse\n+\t\t\t\tval |= FIELD_PREP(SDMA_BYPASS_MD, 0);\n+\n+\t\t\tval |= FIELD_PREP(SDMA_BYPASS_NMQID, qid);\n+\t\t} else {\n+\t\t\tval |= FIELD_PREP(SDMA_BYPASS_EXTQID, qid);\n+\t\t}\n+\n+\t\tregmap_write(priv->regmap, SDMA_BYPASS(qport->lpid), val);\n+\t} else {\n+\t\t/* Ingress packet can bypass or not bypass PCE.\n+\t\t * Queue identifier is set in the Queue Mapping Table\n+\t\t * under PCE Table Programming. This table will be used\n+\t\t * for bypass/no bypass case.\n+\t\t */\n+\t\tpce_tbl.id = PCE_Q_MAP;\n+\t\tpce_tbl.addr = qport->tc_id;\n+\t\tpce_tbl.addr |= FIELD_PREP(PCE_Q_MAP_EG_PID, qport->lpid);\n+\n+\t\tif (qport->en_ig_pce_bypass || qport->resv_port_mode) {\n+\t\t\tpce_tbl.addr |= PCE_Q_MAP_IG_PORT_MODE;\n+\t\t} else {\n+\t\t\tif (qport->extration_en)\n+\t\t\t\tpce_tbl.addr |= PCE_Q_MAP_LOCAL_EXTRACT;\n+\t\t}\n+\n+\t\tpce_tbl.val[0] = qid;\n+\t\tret = gswip_pce_table_write(priv, &pce_tbl);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\treg_wbits(priv, SDMA_BYPASS(qport->lpid),\n+\t\t\t  SDMA_BYPASS_PCEBYP, qport->en_ig_pce_bypass);\n+\t}\n+\n+\t/* Redirect port id for table is bit 4, and bit (2,0) */\n+\teg_port = FIELD_GET(BM_Q_MAP_VAL4_REDIR_PID, qport->redir_port_id);\n+\tval = FIELD_GET(BM_Q_MAP_VAL4_REDIR_PID_MSB, qport->redir_port_id);\n+\teg_port |= FIELD_PREP(BM_Q_MAP_VAL4_REDIR_PID_BIT4, val);\n+\n+\t/* Map queue to an egress port. */\n+\tbm_tbl.id = BM_Q_MAP;\n+\tbm_tbl.val[0] = eg_port;\n+\tbm_tbl.num_val = 1;\n+\tbm_tbl.qmap.qid = qid;\n+\n+\treturn gswip_bm_table_write(priv, &bm_tbl);\n+}\n+\n+static const struct core_ctp_ops gswip_core_ctp_ops = {\n+\t.alloc = gswip_ctp_port_alloc,\n+\t.free = gswip_ctp_port_free,\n+};\n+\n+static const struct core_br_port_ops gswip_core_br_port_ops = {\n+\t.alloc = gswip_bridge_port_alloc,\n+\t.free = gswip_bridge_port_free,\n+};\n+\n+static const struct core_br_ops gswip_core_br_ops = {\n+\t.alloc = gswip_bridge_alloc,\n+\t.free = gswip_bridge_free,\n+};\n+\n+static const struct core_qos_ops gswip_core_qos_ops = {\n+\t.q_port_set = gswip_qos_q_port_set,\n+};\n+\n+int gswip_core_setup_port_ops(struct gswip_core_priv *priv)\n+{\n+\tstruct core_ops *ops =  &priv->ops;\n+\n+\tops->ctp_ops = &gswip_core_ctp_ops;\n+\tops->br_port_ops = &gswip_core_br_port_ops;\n+\tops->br_ops = &gswip_core_br_ops;\n+\tops->qos_ops = &gswip_core_qos_ops;\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/gswip_reg.h b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_reg.h\nnew file mode 100644\nindex 000000000000..50a13b68ef85\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_reg.h\n@@ -0,0 +1,491 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2016-2019 Intel Corporation.\n+ *\n+ * GSWIP-O Top and Legacy MAC Register Description.\n+ */\n+#ifndef _GSWIP_REG_H\n+#define _GSWIP_REG_H\n+\n+#define ETHSW_CAP_1\t\t\t0x001c\n+#define ETHSW_CAP_1_PPORTS\t\tGENMASK(3, 0)\n+#define ETHSW_CAP_1_VPORTS\t\tGENMASK(7, 4)\n+#define ETHSW_CAP_1_QUEUE\t\tGENMASK(14, 8)\n+#define ETHSW_CAP_1_GMAC\t\tBIT(15)\n+\n+#define ETHSW_VERSION\t\t\t0x004c\n+#define ETHSW_VERSION_REV_ID\t\tGENMASK(7, 0)\n+#define ETHSW_VERSION_MOD_ID\t\tGENMASK(15, 8)\n+\n+#define ETHSW_CAP_13\t\t\t0x0058\n+#define ETHSW_CAP_13_EVLAN\t\tGENMASK(3, 0)\n+#define ETHSW_CAP_13_INTRMON\t\tGENMASK(7, 4)\n+#define ETHSW_CAP_13_PAYLOAD\t\tGENMASK(11, 8)\n+#define ETHSW_CAP_13_PMAC\t\tGENMASK(15, 12)\n+\n+#define ETHSW_CAP_17\t\t\t0x0068\n+#define ETHSW_CAP_17_BRGPT\t\tGENMASK(3, 0)\n+#define ETHSW_CAP_17_BRG\t\tGENMASK(7, 4)\n+#define ETHSW_CAP_17_PMAP\t\tGENMASK(11, 8)\n+\n+#define ETHSW_CAP_18\t\t\t0x006c\n+#define ETHSW_CAP_18_CTP\t\tGENMASK(15, 0)\n+\n+#define BM_RAM_VAL_OFFSET\t\t4\n+#define BM_RAM_VAL_0\t\t\t0x010c\n+#define BM_RAM_VAL_0_VAL0\t\tGENMASK(15, 0)\n+\n+#define BM_RAM_ADDR\t\t\t0x0110\n+#define BM_RAM_ADDR_ADDR\t\tGENMASK(15, 0)\n+\n+#define BM_RAM_CTRL\t\t\t0x0114\n+#define BM_RAM_CTRL_ADDR\t\tGENMASK(4, 0)\n+#define BM_RAM_CTRL_OPMOD\t\tBIT(5)\n+#define BM_RAM_CTRL_RMON\t\tBIT(6)\n+#define BM_RAM_CTRL_BAS\t\t\tBIT(15)\n+\n+#define BM_RMON_GCTRL\t\t\t0x0188\n+#define BM_RMON_GCTRL_METER_RES\t\tBIT(1)\n+#define BM_RMON_GCTRL_ALLITF_RES\tBIT(2)\n+#define BM_RMON_GCTRL_INT_RES\t\tBIT(3)\n+#define BM_RMON_GCTRL_ITFID\t\tGENMASK(11, 4)\n+#define BM_RMON_GCTRL_PMAC_RES\t\tBIT(12)\n+#define BM_RMON_GCTRL_MRMON\t\tBIT(14)\n+#define BM_RMON_GCTRL_INTMON\t\tBIT(15)\n+\n+#define BM_PCFG_OFFSET\t\t\t8\n+#define BM_PCFG(x)\t\t\t(0x0200 + BM_PCFG_OFFSET * (x))\n+#define BM_PCFG_CNTEN\t\t\tBIT(0)\n+\n+#define BM_RMON_CTRL_OFFSET\t\t8\n+#define BM_RMON_CTRL(x)\t\t\t(0x0204 + BM_RMON_CTRL_OFFSET * (x))\n+#define BM_RMON_CTRL_RAM1_RES\t\tBIT(0)\n+#define BM_RMON_CTRL_RAM2_RES\t\tBIT(1)\n+\n+#define BM_PWRED_RTH_0_OFFSET\t\t24\n+#define BM_PWRED_RTH_0(x)\t\t(0x0280 + BM_PWRED_RTH_0_OFFSET * (x))\n+#define BM_PWRED_RTH_0_MINTH\t\tGENMASK(9, 0)\n+\n+#define BM_PWRED_RTH_1_OFFSET\t\t24\n+#define BM_PWRED_RTH_1(x)\t\t(0x0284 + BM_PWRED_RTH_1_OFFSET * (x))\n+#define BM_PWRED_RTH_1_MAXTH\t\tGENMASK(9, 0)\n+\n+#define BM_PWRED_YTH_0_OFFSET\t\t24\n+#define BM_PWRED_YTH_0(x)\t\t(0x0288 + BM_PWRED_YTH_0_OFFSET * (x))\n+#define BM_PWRED_YTH_0_MINTH\t\tGENMASK(9, 0)\n+\n+#define BM_PWRED_YTH_1_OFFSET\t\t24\n+#define BM_PWRED_YTH_1(x)\t\t(0x028c + BM_PWRED_YTH_1_OFFSET * (x))\n+#define BM_PWRED_YTH_1_MAXTH\t\tGENMASK(9, 0)\n+\n+#define BM_PWRED_GTH_0_OFFSET\t\t24\n+#define BM_PWRED_GTH_0(x)\t\t(0x0290 + BM_PWRED_GTH_0_OFFSET * (x))\n+#define BM_PWRED_GTH_0_MINTH\t\tGENMASK(9, 0)\n+\n+#define BM_PWRED_GTH_1_OFFSET\t\t24\n+#define BM_PWRED_GTH_1(x)\t\t(0x0294 + BM_PWRED_GTH_1_OFFSET * (x))\n+#define BM_PWRED_GTH_1_MAXTH\t\tGENMASK(9, 0)\n+\n+#define PCE_TBL_VAL_30\t\t\t0x1014\n+#define PCE_TBL_VAL_29\t\t\t0x1018\n+#define PCE_TBL_VAL_28\t\t\t0x101c\n+#define PCE_TBL_VAL_27\t\t\t0x1020\n+#define PCE_TBL_VAL_26\t\t\t0x1024\n+\n+#define PCE_TBL_KEY_33\t\t\t0x1038\n+#define PCE_TBL_KEY_32\t\t\t0x103c\n+#define PCE_TBL_KEY_31\t\t\t0x1040\n+#define PCE_TBL_KEY_30\t\t\t0x1044\n+#define PCE_TBL_KEY_29\t\t\t0x1048\n+#define PCE_TBL_KEY_28\t\t\t0x104c\n+#define PCE_TBL_KEY_27\t\t\t0x1050\n+#define PCE_TBL_KEY_26\t\t\t0x1054\n+#define PCE_TBL_KEY_25\t\t\t0x1058\n+#define PCE_TBL_KEY_24\t\t\t0x105c\n+#define PCE_TBL_KEY_23\t\t\t0x1060\n+#define PCE_TBL_KEY_22\t\t\t0x1064\n+#define PCE_TBL_KEY_21\t\t\t0x1068\n+#define PCE_TBL_KEY_20\t\t\t0x106c\n+#define PCE_TBL_KEY_19\t\t\t0x1070\n+#define PCE_TBL_KEY_18\t\t\t0x1074\n+#define PCE_TBL_KEY_17\t\t\t0x1078\n+#define PCE_TBL_KEY_16\t\t\t0x107c\n+\n+#define PCE_TBL_VAL_25\t\t\t0x1080\n+#define PCE_TBL_VAL_24\t\t\t0x1084\n+#define PCE_TBL_VAL_23\t\t\t0x1088\n+#define PCE_TBL_VAL_22\t\t\t0x108c\n+#define PCE_TBL_VAL_21\t\t\t0x1090\n+#define PCE_TBL_VAL_20\t\t\t0x1094\n+#define PCE_TBL_VAL_19\t\t\t0x1098\n+#define PCE_TBL_VAL_18\t\t\t0x109c\n+#define PCE_TBL_VAL_17\t\t\t0x10a0\n+#define PCE_TBL_VAL_16\t\t\t0x10a4\n+\n+#define PCE_TBL_MASK_3\t\t\t0x10a8\n+#define PCE_TBL_MASK_2\t\t\t0x10ac\n+#define PCE_TBL_MASK_1\t\t\t0x10b0\n+\n+#define PCE_TBL_VAL_15\t\t\t0x10b4\n+#define PCE_TBL_VAL_14\t\t\t0x10b8\n+#define PCE_TBL_VAL_13\t\t\t0x10bc\n+#define PCE_TBL_VAL_12\t\t\t0x10c0\n+#define PCE_TBL_VAL_11\t\t\t0x10c4\n+#define PCE_TBL_VAL_10\t\t\t0x10c8\n+#define PCE_TBL_VAL_9\t\t\t0x10cc\n+#define PCE_TBL_VAL_8\t\t\t0x10d0\n+#define PCE_TBL_VAL_7\t\t\t0x10d4\n+#define PCE_TBL_VAL_6\t\t\t0x10d8\n+#define PCE_TBL_VAL_5\t\t\t0x10dc\n+\n+#define PCE_TBL_KEY_15\t\t\t0x01e0\n+#define PCE_TBL_KEY_14\t\t\t0x10e4\n+#define PCE_TBL_KEY_13\t\t\t0x10e8\n+#define PCE_TBL_KEY_12\t\t\t0x10ec\n+#define PCE_TBL_KEY_11\t\t\t0x10f0\n+#define PCE_TBL_KEY_10\t\t\t0x10f4\n+#define PCE_TBL_KEY_9\t\t\t0x10f8\n+#define PCE_TBL_KEY_8\t\t\t0x10fc\n+#define PCE_TBL_KEY_7\t\t\t0x1100\n+#define PCE_TBL_KEY_6\t\t\t0x1104\n+#define PCE_TBL_KEY_5\t\t\t0x1108\n+#define PCE_TBL_KEY_4\t\t\t0x110c\n+#define PCE_TBL_KEY_3\t\t\t0x1110\n+#define PCE_TBL_KEY_2\t\t\t0x1114\n+#define PCE_TBL_KEY_1\t\t\t0x1118\n+#define PCE_TBL_KEY_0\t\t\t0x111c\n+\n+#define PCE_TBL_MASK_0\t\t\t0x1120\n+\n+#define PCE_TBL_VAL_4\t\t\t0x1124\n+#define PCE_TBL_VAL_3\t\t\t0x1128\n+#define PCE_TBL_VAL_2\t\t\t0x112c\n+#define PCE_TBL_VAL_1\t\t\t0x1130\n+#define PCE_TBL_VAL_0\t\t\t0x1134\n+\n+#define PCE_TBL_ADDR\t\t\t0x1138\n+#define PCE_TBL_ADDR_ADDR\t\tGENMASK(11, 0)\n+\n+#define PCE_TBL_CTRL\t\t\t0x113c\n+#define PCE_TBL_CTRL_ADDR\t\tGENMASK(4, 0)\n+#define PCE_TBL_CTRL_OPMOD\t\tGENMASK(6, 5)\n+#define PCE_TBL_CTRL_GMAP\t\tGENMASK(10, 7)\n+#define PCE_TBL_CTRL_KEYFORM\t\tBIT(11)\n+#define PCE_TBL_CTRL_VLD\t\tBIT(12)\n+#define PCE_TBL_CTRL_TYPE\t\tBIT(13)\n+#define PCE_TBL_CTRL_EXTOP\t\tBIT(14)\n+#define PCE_TBL_CTRL_BAS\t\tBIT(15)\n+\n+#define PCE_PCTRL_OFFSET\t\t40\n+#define PCE_PCTRL_0(x)\t\t\t(0x1200 + PCE_PCTRL_OFFSET * (x))\n+#define PCE_PCTRL_0_PSTATE\t\tGENMASK(2, 0)\n+#define PCE_PCTRL_0_AGEDIS\t\tBIT(3)\n+#define PCE_PCTRL_0_PLOCK\t\tBIT(4)\n+#define PCE_PCTRL_0_TVM\t\t\tBIT(5)\n+#define PCE_PCTRL_0_VREP\t\tBIT(6)\n+#define PCE_PCTRL_0_CMOD\t\tBIT(7)\n+#define PCE_PCTRL_0_DPEN\t\tBIT(8)\n+#define PCE_PCTRL_0_CLPEN\t\tBIT(9)\n+#define PCE_PCTRL_0_PCPEN\t\tBIT(10)\n+#define PCE_PCTRL_0_IGSTEN\t\tBIT(11)\n+#define PCE_PCTRL_0_EGSTEN\t\tBIT(12)\n+#define PCE_PCTRL_0_MCST\t\tBIT(13)\n+#define PCE_PCTRL_0_SPFDIS\t\tBIT(14)\n+#define PCE_PCTRL_0_MSTP\t\tBIT(15)\n+\n+#define FDMA_PASR\t\t\t0x291c\n+#define FDMA_PASR_CPU\t\t\tGENMASK(1, 0)\n+#define FDMA_PASR_MPE1\t\t\tGENMASK(3, 2)\n+#define FDMA_PASR_MPE2\t\t\tGENMASK(5, 4)\n+#define FDMA_PASR_MPE3\t\t\tGENMASK(7, 6)\n+\n+#define FDMA_PCTRL_OFFSET\t\t24\n+#define FDMA_PCTRL(x)\t\t\t(0x2a00 + FDMA_PCTRL_OFFSET * (x))\n+#define FDMA_PCTRL_EN\t\t\tBIT(0)\n+#define FDMA_PCTRL_STEN\t\t\tBIT(1)\n+#define FDMA_PCTRL_DSCPRM\t\tBIT(2)\n+#define FDMA_PCTRL_VLANMOD\t\tBIT(3)\n+#define FDMA_PCTRL_TS_PTP\t\tBIT(4)\n+#define FDMA_PCTRL_TS_NONPTP\t\tBIT(5)\n+#define FDMA_PCTRL_HEADER_SHORT\t\tBIT(6)\n+#define FDMA_PCTRL_VLANTPID\t\tBIT(7)\n+\n+#define SDMA_PCTRL_OFFSET\t\t24\n+#define SDMA_PCTRL(x)\t\t\t(0x2f00 + SDMA_PCTRL_OFFSET * (x))\n+#define SDMA_PCTRL_PEN\t\t\tBIT(0)\n+#define SDMA_PCTRL_FCEN\t\t\tBIT(1)\n+#define SDMA_PCTRL_MFCEN\t\tBIT(2)\n+#define SDMA_PCTRL_PAUFWD\t\tBIT(3)\n+#define SDMA_PCTRL_FCSFWD\t\tBIT(4)\n+#define SDMA_PCTRL_FCSIGN\t\tBIT(5)\n+#define SDMA_PCTRL_USFWD\t\tBIT(6)\n+#define SDMA_PCTRL_OSFWD\t\tBIT(7)\n+#define SDMA_PCTRL_LENFWD\t\tBIT(8)\n+#define SDMA_PCTRL_ALGFWD\t\tBIT(9)\n+#define SDMA_PCTRL_PHYEFWD\t\tBIT(10)\n+#define SDMA_PCTRL_PTHR\t\t\tGENMASK(12, 11)\n+#define SDMA_PCTRL_DTHR\t\t\tGENMASK(14, 13)\n+\n+#define SDMA_PRIO_OFFSET\t\t24\n+#define SDMA_PRIO(x)\t\t\t(0x2f04 + SDMA_PRIO_OFFSET * (x))\n+#define SDMA_PRIO_BIT10\t\t\tGENMASK(1, 0)\n+#define SDMA_PRIO_USIGN\t\t\tBIT(2)\n+#define SDMA_PRIO_OSIGN\t\t\tBIT(3)\n+#define SDMA_PRIO_LENIGN\t\tBIT(4)\n+#define SDMA_PRIO_ALGIGN\t\tBIT(5)\n+#define SDMA_PRIO_PHYEIGN\t\tBIT(6)\n+#define SDMA_PRIO_MIN_IFG\t\tGENMASK(11, 7)\n+\n+#define SDMA_BYPASS_OFFSET\t\t24\n+#define SDMA_BYPASS(x)\t\t\t(0x2f10 + SDMA_BYPASS_OFFSET * (x))\n+#define SDMA_BYPASS_MD\t\t\tBIT(0)\n+#define SDMA_BYPASS_NMQID\t\tGENMASK(5, 1)\n+#define SDMA_BYPASS_EXTQID\t\tGENMASK(10, 6)\n+#define SDMA_BYPASS_PCEBYP\t\tBIT(11)\n+#define SDMA_BYPASS_IGMIR\t\tBIT(12)\n+#define SDMA_BYPASS_EGMIR\t\tBIT(13)\n+\n+#define PMAC_CTRL_0\t\t\t0x340c\n+#define PMAC_CTRL_0_CHKVER\t\tBIT(5)\n+#define PMAC_CTRL_0_CHKREG\t\tBIT(6)\n+#define PMAC_CTRL_0_FCS\t\t\tBIT(7)\n+#define PMAC_CTRL_0_PADEN\t\tBIT(8)\n+#define PMAC_CTRL_0_VPADEN\t\tBIT(9)\n+#define PMAC_CTRL_0_VPAD2EN\t\tBIT(10)\n+#define PMAC_CTRL_0_APADEN\t\tBIT(11)\n+#define PMAC_CTRL_0_FCSEN\t\tBIT(12)\n+\n+#define PMAC_CTRL_1\t\t\t0x3410\n+#define PMAC_CTRL_1_MLEN\t\tGENMASK(13, 0)\n+\n+#define PMAC_CTRL_2\t\t\t0x3414\n+#define PMAC_CTRL_2_LCHKS\t\tGENMASK(1, 0)\n+#define PMAC_CTRL_2_LCHKL\t\tBIT(2)\n+#define PMAC_CTRL_2_MLEN\t\tBIT(3)\n+\n+#define PMAC_CTRL_4\t\t\t0x341c\n+#define PMAC_CTRL_4_FLAGEN\t\tGENMASK(1, 0)\n+#define PMAC_RX_FSM_IDLE\t\t0x00\n+#define PMAC_RX_FSM_IGCFG\t\t0x01\n+#define PMAC_RX_FSM_DASA\t\t0x10\n+\n+#define PMAC_CTRL_NUM\t\t\t4\n+\n+#define PMAC_REG_OFFSET_1\t\t0x200\n+#define PMAC_REG_OFFSET_2\t\t0x600\n+\n+#define\tPMAC_BSL_LEN0\t\t\t0x3440\n+#define\tPMAC_BSL_LEN0_LEN0\t\tGENMASK(15, 0)\n+\n+#define\tPMAC_BSL_LEN1\t\t\t0x3444\n+#define\tPMAC_BSL_LEN1_LEN1\t\tGENMASK(15, 0)\n+\n+#define\tPMAC_BSL_LEN2\t\t\t0x3448\n+#define\tPMAC_BSL_LEN2_LEN2\t\tGENMASK(15, 0)\n+\n+#define PMAC_BSL_NUM\t\t\t3\n+\n+#define PMAC_TBL_VAL_OFFSET\t\t0x200\n+#define PMAC_TBL_VAL(_x)\t\t\\\n+\t\t\t\t({ typeof(_x) (x) = (_x); \\\n+\t\t\t\t(0x3510 + PMAC_TBL_VAL_OFFSET * (x) * (x)); })\n+#define PMAC_TBL_VAL_0_VAL0\t\tGENMASK(15, 0)\n+\n+#define PMAC_TBL_VAL_SFT\t\t4\n+\n+#define PMAC_TBL_ADDR_OFFSET\t\t0x200\n+#define PMAC_TBL_ADDR(_x)\t\t\\\n+\t\t\t\t({ typeof(_x) (x) = (_x); \\\n+\t\t\t\t(0x3514 + PMAC_TBL_ADDR_OFFSET * (x) * (x)); })\n+#define PMAC_TBL_ADDR_ADDR\t\tGENMASK(11, 0)\n+\n+#define PMAC_TBL_CTRL_OFFSET\t\t0x200\n+#define PMAC_TBL_CTRL(_x)\t\t\\\n+\t\t\t\t({ typeof(_x) (x) = (_x); \\\n+\t\t\t\t(0x3518 + PMAC_TBL_CTRL_OFFSET * (x) * (x)); })\n+#define PMAC_TBL_CTRL_ADDR\t\tGENMASK(2, 0)\n+#define PMAC_TBL_CTRL_OPMOD\t\tBIT(5)\n+#define PMAC_TBL_CTRL_BAS\t\tBIT(15)\n+\n+#define ETHSW_CTP_STARTID_OFFSET\t8\n+#define ETHSW_CTP_STARTID(x)\t\t\\\n+\t\t\t\t(0x3a00 + ETHSW_CTP_STARTID_OFFSET * (x))\n+#define ETHSW_CTP_STARTID_STARTID\tGENMASK(8, 0)\n+#define ETHSW_CTP_STARTID_MD\t\tGENMASK(15, 14)\n+#define MD_WLAN8\t\t\t0\n+#define MD_WLAN9\t\t\t1\n+#define MD_OTHER\t\t\t2\n+\n+#define ETHSW_CTP_ENDID_0\t\t0x3a04\n+#define ETHSW_CTP_ENDID(x)\t\t\\\n+\t\t\t(ETHSW_CTP_ENDID_0 + ETHSW_CTP_STARTID_OFFSET * (x))\n+#define ETHSW_CTP_ENDID_ENDID\t\tGENMASK(8, 0)\n+\n+#define ETHSW_GPID_STARTID_OFFSET\t8\n+#define ETHSW_GPID_STARTID(x)\t\t\\\n+\t\t\t\t(0x3a80 + ETHSW_GPID_STARTID_OFFSET * (x))\n+#define ETHSW_GPID_STARTID_BITS\t\tGENMASK(14, 12)\n+#define ETHSW_GPID_STARTID_STARTID\tGENMASK(7, 0)\n+\n+#define ETHSW_GPID_ENDID_OFFSET\t\t8\n+#define ETHSW_GPID_ENDID(x)\t\t\\\n+\t\t\t\t(0x3a84 + ETHSW_GPID_ENDID_OFFSET * (x))\n+#define ETHSW_GPID_ENDID_ENDID\t\tGENMASK(8, 0)\n+\n+#define GPID_RAM_VAL\t\t\t0x3b00\n+#define GPID_RAM_VAL_OV\t\t\tBIT(15)\n+#define GPID_RAM_VAL_SUBID_GRP\t\tGENMASK(11, 4)\n+#define GPID_RAM_VAL_LPID\t\tGENMASK(3, 0)\n+\n+#define GPID_RAM_CTRL\t\t\t0x3b04\n+#define GPID_RAM_CTRL_BAS\t\tBIT(15)\n+#define GPID_RAM_CTRL_OPMOD\t\tBIT(8)\n+#define GPID_RAM_CTRL_ADDR\t\tGENMASK(7, 0)\n+\n+/** GSWIP-O Top Register Description **/\n+#define GSWIP_CFG\t\t\t0x0000\n+#define GSWIP_CFG_SS_HWRES_ON\t\tBIT(1)\n+#define GSWIP_CFG_CLK_MD\t\tGENMASK(3, 2)\n+#define GSWIP_CFG_CLK_MUX_SEL\t\tGENMASK(12, 11)\n+#define GSWIP_CFG_CORE_SE_EN\t\tBIT(15)\n+\n+#define MACSEC_EN\t\t\t0x0008\n+#define GSWIPSS_IER0\t\t\t0x0010\n+\n+#define GSWIPSS_ISR0\t\t\t0x0014\n+#define GSWIPSS_I_XGMAC2\t\tBIT(2)\n+#define GSWIPSS_I_XGMAC3\t\tBIT(3)\n+#define GSWIPSS_I_XGMAC4\t\tBIT(4)\n+#define GSWIPSS_I_XGMAC5\t\tBIT(5)\n+#define GSWIPSS_I_XGMAC6\t\tBIT(6)\n+#define GSWIPSS_I_XGMAC7\t\tBIT(7)\n+#define GSWIPSS_I_XGMAC8\t\tBIT(8)\n+#define GSWIPSS_I_XGMAC9\t\tBIT(9)\n+#define GSWIPSS_I_XGMAC10\t\tBIT(10)\n+\n+#define GSWIPSS_IER1\t\t\t0x0018\n+#define GSWIPSS_ISR1\t\t\t0x001c\n+#define GSWIPSS_SPTAG_ETYPE\t\t0x0038\n+#define GSWIPSS_1588_CFG0\t\t0x0050\n+#define GSWIPSS_1588_CFG1\t\t0x0054\n+#define GSWIPSS_NCO1_LSB\t\t0x0060\n+#define GSWIPSS_NCO1_USB\t\t0x0064\n+#define GSWIPSS_NCO2_LSB\t\t0x0068\n+#define GSWIPSS_NC02_MSB\t\t0x006c\n+#define GSWIPSS_NCO3_LSB\t\t0x0070\n+#define GSWIPSS_NCO3_MSB\t\t0x0074\n+#define GSWIPSS_NC04_LSB\t\t0x0078\n+#define GSWIPSS_NC04_MSB\t\t0x007c\n+#define GSWIP_MEMLS0\t\t\t0x0080\n+#define GSWIP_MEMLS1\t\t\t0x0084\n+\n+/* GSWIP-O Top: MAC Registers */\n+#define MAC_IF_CFG\t\t\t0X1200\n+#define MAC_IF_CFG_CFG2G5\t\tBIT(0)\n+#define MAC_IF_CFG_CFG1G\t\tBIT(1)\n+#define MAC_IF_CFG_CFGFE\t\tBIT(2)\n+#define MAC_IF_CFG_PTP_DIS\t\tBIT(11)\n+#define MAC_IF_CFG_MAC_EN\t\tBIT(12)\n+#define MAC_IF_CFG_XGMAC_RES\t\tBIT(13)\n+#define MAC_IF_CFG_LMAC_RES\t\tBIT(14)\n+#define MAC_IF_CFG_ADAP_RES\t\tBIT(15)\n+\n+#define MAC_OP_CFG\t\t\t0X1204\n+#define MAC_OP_CFG_RX_SPTAG\t\tGENMASK(1, 0)\n+#define MAC_OP_CFG_RX_TIME\t\tGENMASK(3, 2)\n+#define MAC_OP_CFG_RX_FCS\t\tGENMASK(5, 4)\n+#define MAC_OP_CFG_RX_FCS_M0\t\t0x00\n+#define MAC_OP_CFG_RX_FCS_M1\t\t0x01\n+#define MAC_OP_CFG_RX_FCS_M2\t\t0X02\n+#define MAC_OP_CFG_RX_FCS_M3\t\t0x03\n+\n+#define MAC_MTU_CFG\t\t\t0X1208\n+#define MAC_MTU_CFG_MTU\t\t\tGENMASK(13, 0)\n+\n+#define PHY_MODE\t\t\t0x1270\n+#define PHY_MODE_FCONRX\t\t\tGENMASK(6, 5)\n+#define PHY_MODE_FCONTX\t\t\tGENMASK(8, 7)\n+#define PHY_MODE_FCON_AUTO\t\t0x00\n+#define PHY_MODE_FCON_EN\t\t0x01\n+#define PHY_MODE_FCON_DIS\t\t0x11\n+#define PHY_MODE_FDUP\t\t\tGENMASK(10, 9)\n+#define PHY_MODE_FDUP_AUTO\t\t0x00\n+#define PHY_MODE_FDUP_FD\t\t0x01\n+#define PHY_MODE_FDUP_HD\t\t0x11\n+#define PHY_MODE_SPEED_LSB\t\tGENMASK(12, 11)\n+#define PHY_MODE_LINKST\t\t\tGENMASK(14, 13)\n+#define PHY_MODE_LINKST_AUTO\t\t0x00\n+#define PHY_MODE_LINKST_UP\t\t0x01\n+#define PHY_MODE_LINKST_DOWN\t\t0x10\n+#define PHY_MODE_SPEED_MSB\t\tBIT(15)\n+#define PHY_MODE_SPEED_10M\t\t0x000\n+#define PHY_MODE_SPEED_100M\t\t0x001\n+#define PHY_MODE_SPEED_1G\t\t0x010\n+#define PHY_MODE_SPEED_10G\t\t0x011\n+#define PHY_MODE_SPEED_2G5\t\t0x100\n+#define PHY_MODE_SPEED_5G\t\t0x101\n+#define PHY_MODE_SPEED_FLEX\t\t0x110\n+#define PHY_MODE_SPEED_AUTO\t\t0x111\n+\n+#define PHY_STAT\t\t\t0x1274\n+#define PHY_STAT_FDUP\t\t\tBIT(2)\n+#define PHY_STAT_SPEED_LSB\t\tGENMASK(4, 3)\n+#define PHY_STAT_LSTAT\t\t\tBIT(5)\n+#define PHY_STAT_SPEED_MSB\t\tBIT(11)\n+\n+#define ANEG_EEE\t\t\t0x1278\n+#define ANEG_EEE_CAP\t\t\tGENMASK(1, 0)\n+#define ANEG_EEE_CAP_AUTO\t\t0x00\n+#define ANEG_EEE_CAP_ON\t\t\t0x01\n+#define ANEG_EEE_CAP_OFF\t\t0x11\n+#define ANEG_EEE_CLK_STOP_CAP\t\tGENMASK(3, 2)\n+\n+#define MAC_Q_INC\t\t\t0x100\n+#define MAC_IF_CFG_REG(x)\t\t(MAC_IF_CFG + ((x) - MAC2) * MAC_Q_INC)\n+#define MAC_OP_CFG_REG(x)\t\t(MAC_OP_CFG + ((x) - MAC2) * MAC_Q_INC)\n+#define MAC_MTU_CFG_REG(x)\t\t\\\n+\t\t\t\t(MAC_MTU_CFG + ((x) - MAC2) * MAC_Q_INC)\n+#define PHY_MODE_REG(x)\t\t\t(PHY_MODE + ((x) - MAC2) * MAC_Q_INC)\n+#define PHY_STAT_REG(x)\t\t\t(PHY_STAT + ((x) - MAC2) * MAC_Q_INC)\n+#define ANEG_EEE_REG(x)\t\t\t(ANEG_EEE + ((x) - MAC2) * MAC_Q_INC)\n+\n+/* GSWIP-O TOP: XGMAC indirect access */\n+#define XGMAC_CTRL\t\t\t0x1280\n+#define XGMAC_REGACC_DATA0\t\t0x1290\n+#define XGMAC_REGACC_DATA1\t\t0x1294\n+\n+#define XGMAC_REGACC_CTRL\t\t0x1298\n+#define XGMAC_REGACC_CTRL_ADDR\t\tGENMASK(13, 0)\n+#define XGMAC_REGACC_CTRL_OPMOD_WR\tBIT(14)\n+#define XGMAC_REGACC_CTRL_ADDR_BAS\tBIT(15)\n+\n+/** Legacy MAC Register Description **/\n+\n+/* Legacy MAC: Common Registers */\n+#define MAC_TEST\t\t\t0x0300\n+#define MAC_PFAD_CFG\t\t\t0x0304\n+#define MAC_PFSA_0\t\t\t0x0308\n+#define MAC_PFSA_1\t\t\t0x030c\n+#define MAC_PFSA_2\t\t\t0x0310\n+#define LMAC_IER\t\t\t0x0320\n+#define LMAC_ISR\t\t\t0x0324\n+#define LMAC_I_MAC2\t\t\tBIT(0)\n+\n+#define LMAC_CNT_LSB\t\t\t0x0328\n+#define LMAC_CNT_MSB\t\t\t0x032c\n+#define LMAC_CNT_ACC\t\t\t0x0330\n+\n+/* Legacy MAC: Single MAC Registers */\n+#define MAC_CTRL0\t\t\t0x040c\n+#define MAC_CTRL0_GMII\t\t\tGENMASK(1, 0)\n+#define MAC_CTRL0_FDUP\t\t\tGENMASK(3, 2)\n+#define MAC_CTRL0_FCON\t\t\tGENMASK(5, 4)\n+#define MAC_CTRL0_FCS\t\t\tBIT(7)\n+#define MAC_CTRL0_PADEN\t\t\tBIT(8)\n+#define MAC_CTRL0_VPADEN\t\tBIT(9)\n+#define MAC_CTRL0_VPAD2EN\t\tBIT(10)\n+#define MAC_CTRL0_APADEN\t\tBIT(11)\n+\n+#define LMAC_Q_INC\t\t\t0x30\n+#define MAC_CTRL0_REG(x)\t\t(MAC_CTRL0 + ((x) - MAC2) * LMAC_Q_INC)\n+\n+#endif /* _GSWIP_REG_H_ */\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/gswip_tbl.c b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_tbl.c\nnew file mode 100644\nindex 000000000000..18e75e75d7ab\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_tbl.c\n@@ -0,0 +1,332 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2016-2019 Intel Corporation.*/\n+#include <linux/kernel.h>\n+\n+#include \"gswip_core.h\"\n+#include \"gswip_reg.h\"\n+#include \"gswip_tbl.h\"\n+\n+enum tbl_opmode {\n+\tTBL_RD,\n+\tTBL_WR,\n+};\n+\n+enum tbl_busy_indication {\n+\tTBL_READY,\n+\tTBL_BUSY,\n+};\n+\n+enum pce_tbl_opmode {\n+\t/* Address-based read access  */\n+\tPCE_OPMODE_ADRD,\n+\t/* Address-based write access */\n+\tPCE_OPMODE_ADWR,\n+\t/* Key-based read access      */\n+\tPCE_OPMODE_KSRD,\n+\t/* Key-based write access     */\n+\tPCE_OPMODE_KSWR\n+};\n+\n+struct pce_tbl_config {\n+\tu16 num_key;\n+\tu16 num_mask;\n+\tu16 num_val;\n+};\n+\n+struct pce_tbl_reg_map {\n+\tconst u16 *key;\n+\tconst u16 *mask;\n+\tconst u16 *value;\n+};\n+\n+static const u16 pce_tbl_key[] = {\n+\tPCE_TBL_KEY_0, PCE_TBL_KEY_1,   PCE_TBL_KEY_2, PCE_TBL_KEY_3,\n+\tPCE_TBL_KEY_4, PCE_TBL_KEY_5,   PCE_TBL_KEY_6, PCE_TBL_KEY_7,\n+\tPCE_TBL_KEY_8, PCE_TBL_KEY_9,   PCE_TBL_KEY_10, PCE_TBL_KEY_11,\n+\tPCE_TBL_KEY_12, PCE_TBL_KEY_13, PCE_TBL_KEY_14, PCE_TBL_KEY_15,\n+\tPCE_TBL_KEY_16, PCE_TBL_KEY_17, PCE_TBL_KEY_18, PCE_TBL_KEY_19,\n+\tPCE_TBL_KEY_20, PCE_TBL_KEY_21, PCE_TBL_KEY_22, PCE_TBL_KEY_23,\n+\tPCE_TBL_KEY_24, PCE_TBL_KEY_25, PCE_TBL_KEY_26, PCE_TBL_KEY_27,\n+\tPCE_TBL_KEY_28, PCE_TBL_KEY_29, PCE_TBL_KEY_30, PCE_TBL_KEY_31,\n+\tPCE_TBL_KEY_32, PCE_TBL_KEY_33,\n+};\n+\n+static const u16 pce_tbl_mask[] = {\n+\tPCE_TBL_MASK_0, PCE_TBL_MASK_1, PCE_TBL_MASK_2, PCE_TBL_MASK_3,\n+};\n+\n+static const u16 pce_tbl_value[] = {\n+\tPCE_TBL_VAL_0, PCE_TBL_VAL_1,   PCE_TBL_VAL_2, PCE_TBL_VAL_3,\n+\tPCE_TBL_VAL_4, PCE_TBL_VAL_5,   PCE_TBL_VAL_6, PCE_TBL_VAL_7,\n+\tPCE_TBL_VAL_8, PCE_TBL_VAL_9,   PCE_TBL_VAL_10, PCE_TBL_VAL_11,\n+\tPCE_TBL_VAL_12, PCE_TBL_VAL_13, PCE_TBL_VAL_14, PCE_TBL_VAL_15,\n+\tPCE_TBL_VAL_16, PCE_TBL_VAL_17, PCE_TBL_VAL_18, PCE_TBL_VAL_19,\n+\tPCE_TBL_VAL_20, PCE_TBL_VAL_21, PCE_TBL_VAL_22, PCE_TBL_VAL_23,\n+\tPCE_TBL_VAL_24, PCE_TBL_VAL_25, PCE_TBL_VAL_26, PCE_TBL_VAL_27,\n+\tPCE_TBL_VAL_28, PCE_TBL_VAL_29, PCE_TBL_VAL_30,\n+};\n+\n+/* PCE table default entries for Key, Mask and Value.\n+ * Only minimum entries settings are required by default.\n+ */\n+static const struct pce_tbl_config pce_tbl_def_cfg[] = {\n+\t/* Parser ucode table                      */\n+\t{ 0,  0,  4 },\n+\t/* Dummy                                   */\n+\t{ 0,  0,  0 },\n+\t/* VLAN filter table                       */\n+\t{ 1,  0,  1 },\n+\t/* PPPoE table                             */\n+\t{ 1,  0,  0 },\n+\t/* Protocol table                          */\n+\t{ 1,  1,  0 },\n+\t/* Application table                       */\n+\t{ 1,  1,  0 },\n+\t/* IP DA/SA MSB table                      */\n+\t{ 4,  4,  0 },\n+\t/* IP DA/SA LSB table                      */\n+\t{ 4,  4,  0 },\n+\t/* Packet length table                     */\n+\t{ 1,  1,  0 },\n+\t/* Inner PCP/DEI table                     */\n+\t{ 0,  0,  1 },\n+\t/* DSCP table                              */\n+\t{ 0,  0,  1 },\n+\t/* MAC bridging table                      */\n+\t{ 4,  0,  10},\n+\t/* DSCP2PCP configuration table            */\n+\t{ 0,  0,  2 },\n+\t/* Multicast SW table                      */\n+\t{ 19, 0,  10},\n+\t/* Dummy                                   */\n+\t{ 0,  0,  0 },\n+\t/* Traffic Flow table                      */\n+\t{ 34, 0,  31},\n+\t/* PBB tunnel template configuration table */\n+\t{ 0,  0,  11},\n+\t/* Queue mapping table                     */\n+\t{ 0,  0,  1 },\n+\t/* Ingress CTP port configuration table    */\n+\t{ 0,  0,  9 },\n+\t/* Egress CTP port configuration table     */\n+\t{ 0,  0,  7 },\n+\t/* Ingress bridge port configuration table */\n+\t{ 0,  0,  18},\n+\t/* Egress bridge port configuration table  */\n+\t{ 0,  0,  14},\n+\t/* MAC DA table                            */\n+\t{ 3,  1,  0 },\n+\t/* MAC SA table                            */\n+\t{ 3,  1,  0 },\n+\t/* Flags table                             */\n+\t{ 1,  1,  0 },\n+\t/* Bridge configuration table              */\n+\t{ 0,  0,  10},\n+\t/* Outer PCP/DEI table                     */\n+\t{ 0,  0,  1 },\n+\t/* Color marking table                     */\n+\t{ 0,  0,  1 },\n+\t/* Color remarking table                   */\n+\t{ 0,  0,  1 },\n+\t/* Payload table                           */\n+\t{ 1,  1,  0 },\n+\t/* Extended VLAN operation table           */\n+\t{ 4,  0,  6 },\n+\t/* P-mapping configuration table           */\n+\t{ 0,  0,  1 },\n+};\n+\n+int gswip_pce_table_write(struct gswip_core_priv *priv,\n+\t\t\t  struct pce_tbl_prog *pce_tbl)\n+{\n+\tstruct regmap *regmap = priv->regmap;\n+\tu16 i, ctrl;\n+\n+\tspin_lock(&priv->tbl_lock);\n+\n+\t/* update key registers */\n+\tfor (i = 0; i < pce_tbl_def_cfg[pce_tbl->id].num_key; i++)\n+\t\tregmap_write(regmap, pce_tbl_key[i], pce_tbl->key[i]);\n+\n+\t/* update mask registers */\n+\tfor (i = 0; i < pce_tbl_def_cfg[pce_tbl->id].num_mask; i++)\n+\t\tregmap_write(regmap, pce_tbl_mask[i], pce_tbl->mask[i]);\n+\n+\t/* update value registers */\n+\tfor (i = 0; i < pce_tbl_def_cfg[pce_tbl->id].num_val; i++)\n+\t\tregmap_write(regmap, pce_tbl_value[i], pce_tbl->val[i]);\n+\n+\tctrl = FIELD_PREP(PCE_TBL_CTRL_ADDR, pce_tbl->id) |\n+\t       FIELD_PREP(PCE_TBL_CTRL_OPMOD, PCE_OPMODE_ADWR) |\n+\t       FIELD_PREP(PCE_TBL_CTRL_BAS, TBL_BUSY);\n+\n+\t/* update the pce table */\n+\tregmap_write(regmap, PCE_TBL_ADDR, pce_tbl->addr);\n+\tregmap_write(regmap, PCE_TBL_CTRL, ctrl);\n+\n+\tif (tbl_rw_tmout(priv, PCE_TBL_CTRL, PCE_TBL_CTRL_BAS)) {\n+\t\tdev_err(priv->dev, \"failed to write pce table\\n\");\n+\t\tspin_unlock(&priv->tbl_lock);\n+\t\treturn -EBUSY;\n+\t}\n+\n+\tspin_unlock(&priv->tbl_lock);\n+\n+\treturn 0;\n+}\n+\n+int gswip_pce_table_read(struct gswip_core_priv *priv,\n+\t\t\t struct pce_tbl_prog *pce_tbl)\n+{\n+\tu16 i, ctrl;\n+\n+\tspin_lock(&priv->tbl_lock);\n+\n+\tregmap_write(priv->regmap, PCE_TBL_ADDR, pce_tbl->addr);\n+\n+\tctrl = FIELD_PREP(PCE_TBL_CTRL_ADDR, pce_tbl->id) |\n+\t       FIELD_PREP(PCE_TBL_CTRL_OPMOD, PCE_OPMODE_ADRD) |\n+\t       FIELD_PREP(PCE_TBL_CTRL_BAS, TBL_BUSY);\n+\tregmap_write(priv->regmap, PCE_TBL_CTRL, ctrl);\n+\n+\tif (tbl_rw_tmout(priv, PCE_TBL_CTRL, PCE_TBL_CTRL_BAS)) {\n+\t\tdev_err(priv->dev, \"failed to read pce table\\n\");\n+\t\tspin_unlock(&priv->tbl_lock);\n+\t\treturn -EBUSY;\n+\t}\n+\n+\tfor (i = 0; i < pce_tbl_def_cfg[pce_tbl->id].num_key; i++)\n+\t\treg_r16(priv, pce_tbl_key[i], &pce_tbl->key[i]);\n+\n+\tfor (i = 0; i < pce_tbl_def_cfg[pce_tbl->id].num_mask; i++)\n+\t\treg_r16(priv, pce_tbl_mask[i], &pce_tbl->mask[i]);\n+\n+\tfor (i = 0; i < pce_tbl_def_cfg[pce_tbl->id].num_val; i++)\n+\t\treg_r16(priv, pce_tbl_value[i], &pce_tbl->val[i]);\n+\n+\tspin_unlock(&priv->tbl_lock);\n+\n+\treturn 0;\n+}\n+\n+int gswip_bm_table_write(struct gswip_core_priv *priv,\n+\t\t\t struct bm_tbl_prog *bm_tbl)\n+{\n+\tstruct regmap *regmap = priv->regmap;\n+\tu16 ctrl;\n+\tint i;\n+\n+\tspin_lock(&priv->tbl_lock);\n+\n+\tfor (i = 0; i < bm_tbl->num_val; i++)\n+\t\tregmap_write(regmap, (BM_RAM_VAL_0 - i * BM_RAM_VAL_OFFSET),\n+\t\t\t     bm_tbl->val[i]);\n+\n+\tregmap_write(regmap, BM_RAM_ADDR, bm_tbl->addr);\n+\n+\tctrl = bm_tbl->id;\n+\tctrl |= FIELD_PREP(BM_RAM_CTRL_OPMOD, TBL_WR);\n+\tctrl |= FIELD_PREP(BM_RAM_CTRL_BAS, TBL_BUSY);\n+\tregmap_write(regmap, BM_RAM_CTRL, ctrl);\n+\n+\tif (tbl_rw_tmout(priv, BM_RAM_CTRL, BM_RAM_CTRL_BAS)) {\n+\t\tdev_err(priv->dev, \"failed to write bm table\\n\");\n+\t\tspin_unlock(&priv->tbl_lock);\n+\t\treturn -EBUSY;\n+\t}\n+\n+\tspin_unlock(&priv->tbl_lock);\n+\n+\treturn 0;\n+}\n+\n+int gswip_bm_table_read(struct gswip_core_priv *priv,\n+\t\t\tstruct bm_tbl_prog *bm_tbl)\n+{\n+\tu16 ctrl;\n+\tint i;\n+\n+\tspin_lock(&priv->tbl_lock);\n+\n+\tregmap_write(priv->regmap, BM_RAM_ADDR, bm_tbl->addr);\n+\n+\tctrl = FIELD_PREP(BM_RAM_CTRL_ADDR, bm_tbl->id) |\n+\t       FIELD_PREP(BM_RAM_CTRL_OPMOD, TBL_RD) |\n+\t       FIELD_PREP(BM_RAM_CTRL_BAS, TBL_BUSY);\n+\tregmap_write(priv->regmap, BM_RAM_CTRL, ctrl);\n+\n+\tif (tbl_rw_tmout(priv, BM_RAM_CTRL, BM_RAM_CTRL_BAS)) {\n+\t\tdev_err(priv->dev, \"failed to read bm table\\n\");\n+\t\tspin_unlock(&priv->tbl_lock);\n+\t\treturn -EBUSY;\n+\t}\n+\n+\tfor (i = 0; i < bm_tbl->num_val; i++)\n+\t\treg_r16(priv, (BM_RAM_VAL_0 - i * BM_RAM_VAL_OFFSET),\n+\t\t\t&bm_tbl->val[i]);\n+\n+\tspin_unlock(&priv->tbl_lock);\n+\n+\treturn 0;\n+}\n+\n+int gswip_pmac_table_write(struct gswip_core_priv *priv,\n+\t\t\t   struct pmac_tbl_prog *pmac_tbl)\n+{\n+\tu16 pmac_id = pmac_tbl->pmac_id, ctrl;\n+\tint i;\n+\n+\tspin_lock(&priv->tbl_lock);\n+\n+\tfor (i = 0; i < pmac_tbl->num_val; i++)\n+\t\tregmap_write(priv->regmap,\n+\t\t\t     (PMAC_TBL_VAL(pmac_id) - i * PMAC_TBL_VAL_SFT),\n+\t\t\t     pmac_tbl->val[i]);\n+\n+\tregmap_write(priv->regmap, PMAC_TBL_ADDR(pmac_id), pmac_tbl->addr);\n+\n+\tctrl = FIELD_PREP(PMAC_TBL_CTRL_ADDR, pmac_tbl->id) |\n+\t       FIELD_PREP(PMAC_TBL_CTRL_OPMOD, TBL_WR) |\n+\t       FIELD_PREP(PMAC_TBL_CTRL_BAS, TBL_BUSY);\n+\tregmap_write(priv->regmap, PMAC_TBL_CTRL(pmac_id), ctrl);\n+\n+\tif (tbl_rw_tmout(priv, PMAC_TBL_CTRL(pmac_id), PMAC_TBL_CTRL_BAS)) {\n+\t\tdev_err(priv->dev, \"failed to write pmac table\\n\");\n+\t\tspin_unlock(&priv->tbl_lock);\n+\t\treturn -EBUSY;\n+\t}\n+\n+\tspin_unlock(&priv->tbl_lock);\n+\n+\treturn 0;\n+}\n+\n+int gswip_pmac_table_read(struct gswip_core_priv *priv,\n+\t\t\t  struct pmac_tbl_prog *pmac_tbl)\n+{\n+\tu16 pmac_id = pmac_tbl->pmac_id, ctrl;\n+\tint i;\n+\n+\tspin_lock(&priv->tbl_lock);\n+\n+\tregmap_write(priv->regmap, PMAC_TBL_ADDR(pmac_id), pmac_tbl->addr);\n+\n+\tctrl = FIELD_PREP(PMAC_TBL_CTRL_ADDR, pmac_tbl->id) |\n+\t       FIELD_PREP(PMAC_TBL_CTRL_OPMOD, TBL_RD) |\n+\t       FIELD_PREP(PMAC_TBL_CTRL_BAS, TBL_BUSY);\n+\tregmap_write(priv->regmap, PMAC_TBL_CTRL(pmac_id), ctrl);\n+\n+\tif (tbl_rw_tmout(priv, PMAC_TBL_CTRL(pmac_id), PMAC_TBL_CTRL_BAS)) {\n+\t\tdev_err(priv->dev, \"failed to read pmac table\\n\");\n+\t\tspin_unlock(&priv->tbl_lock);\n+\t\treturn -EBUSY;\n+\t}\n+\n+\tfor (i = 0; i < pmac_tbl->num_val; i++)\n+\t\treg_r16(priv, (PMAC_TBL_VAL(pmac_id) - i * PMAC_TBL_VAL_SFT),\n+\t\t\t&pmac_tbl->val[i]);\n+\n+\tspin_unlock(&priv->tbl_lock);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/gswip_tbl.h b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_tbl.h\nnew file mode 100644\nindex 000000000000..4bd92951e7ae\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/gswip_tbl.h\n@@ -0,0 +1,195 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2016-2019 Intel Corporation. */\n+#ifndef _GSW_TBL_RW_H_\n+#define _GSW_TBL_RW_H_\n+\n+#define PCE_TBL_KEY_NUM\t\t34\n+#define PCE_TBL_VAL_NUM\t\t31\n+#define PCE_TBL_MASK_NUM\t4\n+#define PCE_MAC_LIMIT_NUM\t255\n+\n+/* PCE queue mapping table */\n+#define PCE_Q_MAP_LOCAL_EXTRACT\t\t\tBIT(8)\n+#define PCE_Q_MAP_IG_PORT_MODE\t\t\tBIT(9)\n+#define PCE_Q_MAP_EG_PID\t\t\tGENMASK(7, 4)\n+\n+/* PCE ingress CTP port configuration table */\n+#define PCE_IGCTP_VAL4_BYPASS_BR\t\tBIT(15)\n+\n+/* PCE ingress bridge port configuration table */\n+#define PCE_IGBGP_VAL10_PORT_MAP_0\t\t10\n+#define PCE_IGBGP_VAL4_LRN_LIMIT\t\tGENMASK(7, 0)\n+#define PCE_IGBGP_VAL4_BR_ID\t\t\tGENMASK(13, 8)\n+\n+/* PCE EGBGP table */\n+#define PCE_EGBGP_VAL4_DST_SUBIF_ID_GRP\t\tGENMASK(7, 0)\n+#define PCE_EGBGP_VAL4_DST_LPID\t\t\tGENMASK(11, 8)\n+#define PCE_EGBGP_VAL4_PMAPPER\t\t\tBIT(14)\n+\n+/* PCE_BRGCFG table */\n+#define PCE_BRGCFG_VAL1_BCAST_FW_MODE\t\tGENMASK(1, 0)\n+#define PCE_BRGCFG_VAL1_UCAST_FW_MODE\t\tGENMASK(3, 2)\n+#define PCE_BRGCFG_VAL1_MCAST_NIP_FW_MODE\tGENMASK(5, 4)\n+#define PCE_BRGCFG_VAL1_MCAST_IP_FW_MODE\tGENMASK(7, 6)\n+#define PCE_BRGCFG_VAL3_LRN_DISC_CNT\t\tGENMASK(31, 16)\n+\n+/* BM_PQM_THRES table */\n+#define BM_PQM_THRES_Q_NUM\t\t\tGENMASK(7, 3)\n+\n+/* BM_Q_MAP table */\n+#define BM_Q_MAP_VAL4_REDIR_PID\t\t\tGENMASK(2, 0)\n+#define BM_Q_MAP_VAL4_REDIR_PID_MSB\t\tBIT(3)\n+#define BM_Q_MAP_VAL4_REDIR_PID_BIT4\t\tBIT(4)\n+\n+enum pce_tbl_id {\n+\tPCE_TFLOW\t= 0x0f,\n+\tPCE_Q_MAP\t= 0x11,\n+\tPCE_IG_CTP_CFG\t= 0x12,\n+\tPCE_EG_CTP_CFG\t= 0x13,\n+\tPCE_IG_BRP_CFG\t= 0x14,\n+\tPCE_EG_BRP_CFG\t= 0x15,\n+\tPCE_BR_CFG\t= 0x19,\n+\tPCE_PMAP\t= 0x1f,\n+};\n+\n+#define PCE_TBL_KEY_NUM\t\t34\n+#define PCE_TBL_VAL_NUM\t\t31\n+#define PCE_TBL_MASK_NUM\t4\n+\n+/* PCE programming table */\n+struct pce_tbl_prog {\n+\tenum pce_tbl_id id;\n+\tu16 val[PCE_TBL_VAL_NUM];\n+\tu16 key[PCE_TBL_KEY_NUM];\n+\tu16 mask[PCE_TBL_MASK_NUM];\n+\tu16 addr;\n+};\n+\n+/* BM programming table */\n+enum bm_tbl_id {\n+\tBM_CTP_RX_RMON\t\t= 0x00,\n+\tBM_CTP_TX_RMON\t\t= 0x01,\n+\tBM_BR_RX_RMON\t\t= 0x02,\n+\tBM_BR_TX_RMON\t\t= 0x03,\n+\tBM_CTP_PCE_BYPASS_RMON\t= 0x04,\n+\tBM_TFLOW_RX_RMON\t= 0x05,\n+\tBM_TFLOW_TX_RMON\t= 0x06,\n+\tBM_WFQ_PARAM\t\t= 0x07,\n+\tBM_PQM_THRES\t\t= 0x09,\n+\tBM_Q_MAP\t\t= 0x0e,\n+\tBM_PMAC_CNTR\t\t= 0x1c\n+};\n+\n+#define BM_RAM_VAL_MAX\t\t10\n+\n+struct rmon_cntr_tbl {\n+\tu16 ctr_offset : 6;\n+\tu16 port_offset : 10;\n+};\n+\n+struct qmap_tbl {\n+\tu16 qid : 6;\n+\tu16 reserved : 10;\n+};\n+\n+struct pmac_cntr_tbl {\n+\tu16 addr : 5;\n+\tu16 ctr_offset : 3;\n+\tu16 pmac_id : 3;\n+\tu16 reserved : 1;\n+\tu16 ctr_offset_hdr : 1;\n+\tu16 reserved1 : 3;\n+};\n+\n+struct bm_tbl_prog {\n+\tenum bm_tbl_id id;\n+\tunion {\n+\t\tstruct rmon_cntr_tbl rmon_cntr;\n+\t\tstruct qmap_tbl qmap;\n+\t\tstruct pmac_cntr_tbl pmac_cntr;\n+\t\tu16 addr;\n+\t};\n+\tu16 val[BM_RAM_VAL_MAX];\n+\tu32 num_val;\n+};\n+\n+/* PMAC programming table */\n+enum pmac_tbl_id {\n+\tPMAC_BP_MAP,\n+\tPMAC_IG_CFG,\n+\tPMAC_EG_CFG,\n+};\n+\n+#define PMAC_BP_MAP_TBL_VAL_NUM\t\t3\n+#define PMAC_IG_CFG_TBL_VAL_NUM\t\t5\n+#define PMAC_EG_CFG_TBL_VAL_NUM\t\t3\n+#define PMAC_TBL_VAL_MAX\t\t11\n+\n+/* PMAC_BP_MAP table */\n+/* Table Control */\n+#define PMAC_BPMAP_TX_DMA_CH\t\tGENMASK(4, 0)\n+/* PMAC_TBL_VAL_2 */\n+#define PMAC_BPMAP_TX_Q_UPPER\t\tGENMASK(31, 16)\n+\n+/* PMAC_IG_CFG table */\n+/* Table Control */\n+#define PMAC_IGCFG_TX_DMA_CH\t\tGENMASK(4, 0)\n+/* PMAC_TBL_VAL_2 */\n+#define PMAC_IGCFG_HDR_ID\t\tGENMASK(7, 4)\n+/* PMAC_TBL_VAL_4 */\n+#define PMAC_IGCFG_VAL4_PMAC_FLAG\tBIT(0)\n+#define PMAC_IGCFG_VAL4_SPPID_MODE\tBIT(1)\n+#define PMAC_IGCFG_VAL4_SUBID_MODE\tBIT(2)\n+#define PMAC_IGCFG_VAL4_CLASSEN_MODE\tBIT(3)\n+#define PMAC_IGCFG_VAL4_CLASS_MODE\tBIT(5)\n+#define PMAC_IGCFG_VAL4_ERR_DP\t\tBIT(7)\n+\n+/* PMAC_EG_CFG table */\n+/* Table Control */\n+#define PMAC_EGCFG_DST_PORT_ID\t\tGENMASK(3, 0)\n+#define PMAC_EGCFG_MPE1\t\t\tBIT(4)\n+#define PMAC_EGCFG_MPE2\t\t\tBIT(5)\n+#define PMAC_EGCFG_ECRYPT\t\tBIT(6)\n+#define PMAC_EGCFG_DECRYPT\t\tBIT(7)\n+#define PMAC_EGCFG_TC_4BITS\t\tGENMASK(7, 4)\n+#define PMAC_EGCFG_TC_2BITS\t\tGENMASK(7, 6)\n+#define PMAC_EGCFG_FLOW_ID_MSB\t\tGENMASK(9, 8)\n+/* PMAC_TBL_VAL_0 */\n+#define PMAC_EGCFG_VAL0_RES_2BITS\tGENMASK(1, 0)\n+#define PMAC_EGCFG_VAL0_RES_3BITS\tGENMASK(4, 2)\n+#define PMAC_EGCFG_VAL0_REDIR\t\tBIT(4)\n+#define PMAC_EGCFG_VAL0_BSL\t\tGENMASK(7, 5)\n+/* PMAC_TBL_VAL_1 */\n+#define PMAC_EGCFG_VAL1_RX_DMA_CH\tGENMASK(3, 0)\n+/* PMAC_TBL_VAL_2 */\n+#define PMAC_EGCFG_VAL2_PMAC_FLAG\tBIT(0)\n+#define PMAC_EGCFG_VAL2_FCS_MODE\tBIT(1)\n+#define PMAC_EGCFG_VAL2_L2HD_RM_MODE\tBIT(2)\n+#define PMAC_EGCFG_VAL2_L2HD_RM\t\tGENMASK(15, 8)\n+\n+struct pmac_tbl_prog {\n+\tu16 pmac_id;\n+\tenum pmac_tbl_id id;\n+\tu16 val[PMAC_TBL_VAL_MAX];\n+\tu8 num_val;\n+\tu16 addr;\n+};\n+\n+struct gswip_core_priv;\n+\n+int gswip_pce_table_init(void);\n+int gswip_pce_table_write(struct gswip_core_priv *priv,\n+\t\t\t  struct pce_tbl_prog *pce_tbl);\n+int gswip_pce_table_read(struct gswip_core_priv *priv,\n+\t\t\t struct pce_tbl_prog *pce_tbl);\n+int gswip_bm_table_read(struct gswip_core_priv *priv,\n+\t\t\tstruct bm_tbl_prog *bm_tbl);\n+int gswip_bm_table_write(struct gswip_core_priv *priv,\n+\t\t\t struct bm_tbl_prog *bm_tbl);\n+int gswip_pmac_table_read(struct gswip_core_priv *priv,\n+\t\t\t  struct pmac_tbl_prog *pmac_tbl);\n+int gswip_pmac_table_write(struct gswip_core_priv *priv,\n+\t\t\t   struct pmac_tbl_prog *pmac_tbl);\n+\n+#endif\n+\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/lmac.c b/drivers/net/ethernet/intel/gwdpa/gswip/lmac.c\nnew file mode 100644\nindex 000000000000..2fef9eaeeadc\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/lmac.c\n@@ -0,0 +1,46 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2016-2019 Intel Corporation. */\n+\n+#include <linux/bitfield.h>\n+#include <linux/types.h>\n+\n+#include \"mac_common.h\"\n+\n+int lmac_set_duplex_mode(struct gswip_mac *priv, u32 val)\n+{\n+\tu32 mac_ctrl0 = lmac_read(priv, MAC_CTRL0_REG(priv->mac_idx));\n+\n+\tif (FIELD_GET(MAC_CTRL0_FDUP, mac_ctrl0) != val) {\n+\t\tmac_ctrl0 &= ~MAC_CTRL0_FDUP;\n+\t\tmac_ctrl0 |= FIELD_PREP(MAC_CTRL0_FDUP, val);\n+\t\tlmac_write(priv, MAC_CTRL0_REG(priv->mac_idx), mac_ctrl0);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int lmac_set_flowcon_mode(struct gswip_mac *priv, u32 val)\n+{\n+\tu32 mac_ctrl0 = lmac_read(priv, MAC_CTRL0_REG(priv->mac_idx));\n+\n+\tif (FIELD_GET(MAC_CTRL0_FCON, mac_ctrl0) != val) {\n+\t\tmac_ctrl0 &= ~MAC_CTRL0_FCON;\n+\t\tmac_ctrl0 |= FIELD_PREP(MAC_CTRL0_FCON, val);\n+\t\tlmac_write(priv, MAC_CTRL0_REG(priv->mac_idx), mac_ctrl0);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int lmac_set_intf_mode(struct gswip_mac *priv, u32 val)\n+{\n+\tu32 mac_ctrl0 = lmac_read(priv, MAC_CTRL0_REG(priv->mac_idx));\n+\n+\tif (FIELD_GET(MAC_CTRL0_GMII, mac_ctrl0) != val) {\n+\t\tmac_ctrl0 &= ~MAC_CTRL0_GMII;\n+\t\tmac_ctrl0 |= FIELD_PREP(MAC_CTRL0_GMII, val);\n+\t\tlmac_write(priv, MAC_CTRL0_REG(priv->mac_idx), mac_ctrl0);\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/mac_cfg.c b/drivers/net/ethernet/intel/gwdpa/gswip/mac_cfg.c\nnew file mode 100644\nindex 000000000000..dcbcb3e3deab\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/mac_cfg.c\n@@ -0,0 +1,524 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2016-2019 Intel Corporation. */\n+\n+#include <linux/bitfield.h>\n+#include <linux/ethtool.h>\n+#include \"mac_common.h\"\n+\n+static int mac_speed_to_val(u32 speed)\n+{\n+\tint val;\n+\n+\tswitch (speed) {\n+\tcase SPEED_10M:\n+\t\tval = SPEED_10;\n+\t\tbreak;\n+\tcase SPEED_100M:\n+\t\tval = SPEED_100;\n+\t\tbreak;\n+\tcase SPEED_1G:\n+\t\tval = SPEED_1000;\n+\t\tbreak;\n+\tcase SPEED_10G:\n+\t\tval = SPEED_10000;\n+\t\tbreak;\n+\tcase SPEED_2G5:\n+\t\tval = SPEED_2500;\n+\t\tbreak;\n+\tcase SPEED_5G:\n+\t\tval = SPEED_5000;\n+\t\tbreak;\n+\tdefault:\n+\t\tval = SPEED_UNKNOWN;\n+\t}\n+\n+\treturn val;\n+}\n+\n+static int mac_get_speed(struct device *dev)\n+{\n+\tstruct gswip_mac *priv = dev_get_drvdata(dev);\n+\tu32 mac_speed;\n+\n+\tspin_lock_bh(&priv->mac_lock);\n+\tmac_speed = sw_get_speed(priv);\n+\tspin_unlock_bh(&priv->mac_lock);\n+\n+\treturn mac_speed_to_val(mac_speed);\n+}\n+\n+static int mac_set_physpeed(struct gswip_mac *priv, u32 phy_speed)\n+{\n+\tspin_lock_bh(&priv->mac_lock);\n+\txgmac_set_extcfg(priv, 1);\n+\n+\tswitch (phy_speed) {\n+\tdefault:\n+\tcase SPEED_MAC_AUTO:\n+\t\tsw_set_speed(priv, SPEED_AUTO);\n+\t\tbreak;\n+\n+\tcase SPEED_XGMAC_10G:\n+\t\txgmac_set_xgmii_speed(priv);\n+\t\tsw_set_speed(priv, SPEED_10G);\n+\t\tbreak;\n+\n+\tcase SPEED_GMII_25G:\n+\t\tsw_set_speed(priv, SPEED_2G5);\n+\t\tsw_set_2G5_intf(priv, XGMAC_GMII);\n+\t\txgmac_set_gmii_2500_speed(priv);\n+\t\tbreak;\n+\n+\tcase SPEED_XGMII_25G:\n+\t\tsw_set_speed(priv, SPEED_2G5);\n+\t\tsw_set_2G5_intf(priv, XGMAC_XGMII);\n+\t\txgmac_set_xgmii_2500_speed(priv);\n+\t\tbreak;\n+\n+\tcase SPEED_XGMAC_1G:\n+\t\tsw_set_speed(priv, SPEED_1G);\n+\t\tsw_set_1g_intf(priv, XGMAC_GMII);\n+\t\txgmac_set_gmii_speed(priv);\n+\t\txgmac_set_extcfg(priv, 1);\n+\t\tbreak;\n+\n+\tcase SPEED_XGMAC_10M:\n+\t\tsw_set_speed(priv, SPEED_10M);\n+\t\t/* FALLTHRU */\n+\tcase SPEED_XGMAC_100M:\n+\t\tif (phy_speed != SPEED_XGMAC_10M)\n+\t\t\tsw_set_speed(priv, SPEED_100M);\n+\n+\t\tsw_set_fe_intf(priv, XGMAC_GMII);\n+\t\tsw_set_1g_intf(priv, XGMAC_GMII);\n+\t\txgmac_set_gmii_speed(priv);\n+\t\tbreak;\n+\n+\tcase SPEED_LMAC_10M:\n+\t\tsw_set_speed(priv, SPEED_10M);\n+\t\t/* FALLTHRU */\n+\tcase SPEED_LMAC_100M:\n+\t\tif (phy_speed != SPEED_LMAC_10M)\n+\t\t\tsw_set_speed(priv, SPEED_100M);\n+\n+\t\tsw_set_fe_intf(priv, LMAC_MII);\n+\t\tlmac_set_intf_mode(priv, 1);\n+\t\tbreak;\n+\n+\tcase SPEED_LMAC_1G:\n+\t\tsw_set_speed(priv, SPEED_1G);\n+\t\tsw_set_1g_intf(priv, LMAC_GMII);\n+\t\tlmac_set_intf_mode(priv, 2);\n+\t\tbreak;\n+\t}\n+\tspin_unlock_bh(&priv->mac_lock);\n+\n+\treturn 0;\n+}\n+\n+static int mac_set_duplex(struct gswip_mac *priv, u32 mode)\n+{\n+\tu32 val;\n+\n+\tspin_lock_bh(&priv->mac_lock);\n+\tswitch (mode) {\n+\tdefault:\n+\tcase GSW_DUPLEX_AUTO:\n+\t\tval = PHY_MODE_FDUP_AUTO;\n+\t\tbreak;\n+\tcase GSW_DUPLEX_HALF:\n+\t\tval = PHY_MODE_FDUP_HD;\n+\t\tbreak;\n+\tcase GSW_DUPLEX_FULL:\n+\t\tval = PHY_MODE_FDUP_FD;\n+\t\tbreak;\n+\t}\n+\n+\tsw_set_duplex_mode(priv, val);\n+\tlmac_set_duplex_mode(priv, val);\n+\tspin_unlock_bh(&priv->mac_lock);\n+\n+\treturn 0;\n+}\n+\n+static int mac_get_duplex(struct device *dev)\n+{\n+\tstruct gswip_mac *priv = dev_get_drvdata(dev);\n+\tint val;\n+\n+\tspin_lock_bh(&priv->mac_lock);\n+\tval = sw_get_duplex_mode(priv);\n+\tspin_unlock_bh(&priv->mac_lock);\n+\n+\treturn val;\n+}\n+\n+static int mac_get_linksts(struct device *dev)\n+{\n+\tstruct gswip_mac *priv = dev_get_drvdata(dev);\n+\tint linksts;\n+\n+\tspin_lock_bh(&priv->mac_lock);\n+\tlinksts = sw_get_linkstatus(priv);\n+\tspin_unlock_bh(&priv->mac_lock);\n+\n+\treturn linksts;\n+}\n+\n+static int mac_set_linksts(struct gswip_mac *priv, u32 mode)\n+{\n+\tu8 val;\n+\n+\tspin_lock_bh(&priv->mac_lock);\n+\tswitch (mode) {\n+\tdefault:\n+\tcase LINK_AUTO:\n+\t\tval = PHY_MODE_LINKST_AUTO;\n+\t\tbreak;\n+\n+\tcase LINK_UP:\n+\t\tval = PHY_MODE_LINKST_UP;\n+\t\tbreak;\n+\n+\tcase LINK_DOWN:\n+\t\tval = PHY_MODE_LINKST_DOWN;\n+\t\tbreak;\n+\t}\n+\tsw_set_linkstatus(priv, val);\n+\tspin_unlock_bh(&priv->mac_lock);\n+\n+\treturn 0;\n+}\n+\n+static int mac_set_flowctrl(struct device *dev, u32 val)\n+{\n+\tstruct gswip_mac *priv = dev_get_drvdata(dev);\n+\n+\tif (val >= FC_INVALID)\n+\t\treturn -EINVAL;\n+\n+\tspin_lock_bh(&priv->mac_lock);\n+\tlmac_set_flowcon_mode(priv, val);\n+\n+\tswitch (val) {\n+\tdefault:\n+\tcase FC_AUTO:\n+\t\txgmac_tx_flow_ctl(priv, priv->pause_time, XGMAC_FC_EN);\n+\t\txgmac_rx_flow_ctl(priv, XGMAC_FC_EN);\n+\t\tsw_set_flowctrl(priv, PHY_MODE_FCON_AUTO, FCONRX);\n+\t\tsw_set_flowctrl(priv, PHY_MODE_FCON_AUTO, FCONTX);\n+\t\tbreak;\n+\n+\tcase FC_RX:\n+\t\t/* Disable TX in XGMAC and GSWSS */\n+\t\txgmac_tx_flow_ctl(priv, priv->pause_time, XGMAC_FC_DIS);\n+\t\tsw_set_flowctrl(priv, PHY_MODE_FCON_DIS, FCONTX);\n+\n+\t\t/* Enable RX in XGMAC and GSWSS */\n+\t\txgmac_rx_flow_ctl(priv, XGMAC_FC_EN);\n+\n+\t\tsw_set_flowctrl(priv, PHY_MODE_FCON_EN, FCONRX);\n+\t\tbreak;\n+\n+\tcase FC_TX:\n+\t\t/* Disable RX in XGMAC and GSWSS */\n+\t\txgmac_rx_flow_ctl(priv, XGMAC_FC_DIS);\n+\t\tsw_set_flowctrl(priv, PHY_MODE_FCON_DIS, FCONTX);\n+\n+\t\t/* Enable TX in XGMAC and GSWSS */\n+\t\txgmac_tx_flow_ctl(priv, priv->pause_time, XGMAC_FC_EN);\n+\t\tsw_set_flowctrl(priv, PHY_MODE_FCON_EN, FCONTX);\n+\t\tbreak;\n+\n+\tcase FC_RXTX:\n+\t\txgmac_tx_flow_ctl(priv, priv->pause_time, XGMAC_FC_EN);\n+\t\txgmac_rx_flow_ctl(priv, XGMAC_FC_EN);\n+\t\tsw_set_flowctrl(priv, PHY_MODE_FCON_EN, FCONRX);\n+\t\tsw_set_flowctrl(priv, PHY_MODE_FCON_EN, FCONTX);\n+\t\tbreak;\n+\n+\tcase FC_DIS:\n+\t\txgmac_tx_flow_ctl(priv, priv->pause_time, XGMAC_FC_DIS);\n+\t\txgmac_rx_flow_ctl(priv, XGMAC_FC_DIS);\n+\t\tsw_set_flowctrl(priv, PHY_MODE_FCON_DIS, FCONRX);\n+\t\tsw_set_flowctrl(priv, PHY_MODE_FCON_EN, FCONTX);\n+\t\tbreak;\n+\t}\n+\tspin_unlock_bh(&priv->mac_lock);\n+\n+\treturn 0;\n+}\n+\n+inline int get_2G5_intf(struct gswip_mac *priv)\n+{\n+\tu32 mac_if_cfg, macif;\n+\tint ret;\n+\n+\tmac_if_cfg = sw_read(priv, MAC_IF_CFG_REG(priv->mac_idx));\n+\tmacif = FIELD_PREP(MAC_IF_CFG_CFG2G5, mac_if_cfg);\n+\n+\tif (macif == 0)\n+\t\tret = XGMAC_GMII;\n+\telse if (macif == 1)\n+\t\tret = XGMAC_XGMII;\n+\telse\n+\t\tret = -EINVAL;\n+\n+\treturn ret;\n+}\n+\n+inline int get_1g_intf(struct gswip_mac *priv)\n+{\n+\tu32 mac_if_cfg, macif;\n+\tint ret;\n+\n+\tmac_if_cfg = sw_read(priv, MAC_IF_CFG_REG(priv->mac_idx));\n+\tmacif = FIELD_GET(MAC_IF_CFG_CFG1G, mac_if_cfg);\n+\n+\tif (macif == 0)\n+\t\tret = LMAC_GMII;\n+\telse if (macif == 1)\n+\t\tret = XGMAC_GMII;\n+\telse\n+\t\tret = -EINVAL;\n+\n+\treturn ret;\n+}\n+\n+inline int get_fe_intf(struct gswip_mac *priv)\n+{\n+\tu32 mac_if_cfg, macif;\n+\tint ret;\n+\n+\tmac_if_cfg = sw_read(priv, MAC_IF_CFG_REG(priv->mac_idx));\n+\tmacif = FIELD_GET(MAC_IF_CFG_CFGFE, mac_if_cfg);\n+\n+\tif (macif == 0)\n+\t\tret = LMAC_MII;\n+\telse if (macif == 1)\n+\t\tret = XGMAC_GMII;\n+\telse\n+\t\tret = -EINVAL;\n+\n+\treturn ret;\n+}\n+\n+static int mac_get_mii_interface(struct device *dev)\n+{\n+\tstruct gswip_mac *priv = dev_get_drvdata(dev);\n+\tint intf, ret;\n+\tu8 mac_speed;\n+\n+\tspin_lock_bh(&priv->mac_lock);\n+\tmac_speed = sw_get_speed(priv);\n+\tswitch (mac_speed) {\n+\tcase SPEED_10M:\n+\tcase SPEED_100M:\n+\t\tintf = get_fe_intf(priv);\n+\t\tif (intf == XGMAC_GMII)\n+\t\t\tret = GSW_PORT_HW_GMII;\n+\t\telse if (intf == LMAC_MII)\n+\t\t\tret = GSW_PORT_HW_MII;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase SPEED_1G:\n+\t\tintf = get_1g_intf(priv);\n+\t\tif (intf == LMAC_GMII || intf == XGMAC_GMII)\n+\t\t\tret = GSW_PORT_HW_GMII;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase SPEED_2G5:\n+\t\tintf = get_2G5_intf(priv);\n+\t\tif (intf == XGMAC_GMII)\n+\t\t\tret = GSW_PORT_HW_GMII;\n+\t\telse if (intf == XGMAC_XGMII)\n+\t\t\tret = GSW_PORT_HW_XGMII;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase SPEED_10G:\n+\t\tret = GSW_PORT_HW_XGMII;\n+\t\tbreak;\n+\n+\tcase SPEED_AUTO:\n+\t\tret = GSW_PORT_HW_XGMII;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t}\n+\tspin_unlock_bh(&priv->mac_lock);\n+\n+\treturn ret;\n+}\n+\n+inline u32 set_mii_if_fe(u32 mode)\n+{\n+\tu32 val = 0;\n+\n+\tswitch (mode) {\n+\tdefault:\n+\tcase LMAC_MII:\n+\t\tval &= ~MAC_IF_CFG_CFGFE;\n+\t\tbreak;\n+\n+\tcase XGMAC_GMII:\n+\t\tval |= MAC_IF_CFG_CFGFE;\n+\t\tbreak;\n+\t}\n+\n+\treturn val;\n+}\n+\n+inline u32 set_mii_if_1g(u32 mode)\n+{\n+\tu32 val = 0;\n+\n+\tswitch (mode) {\n+\tdefault:\n+\tcase LMAC_GMII:\n+\t\tval &= ~MAC_IF_CFG_CFG1G;\n+\t\tbreak;\n+\n+\tcase XGMAC_GMII:\n+\t\tval |= MAC_IF_CFG_CFG1G;\n+\t\tbreak;\n+\t}\n+\n+\treturn val;\n+}\n+\n+inline u32 set_mii_if_2G5(u32 mode)\n+{\n+\tu32 val = 0;\n+\n+\tswitch (mode) {\n+\tdefault:\n+\tcase XGMAC_GMII:\n+\t\tval &= ~MAC_IF_CFG_CFG2G5;\n+\t\tbreak;\n+\n+\tcase XGMAC_XGMII:\n+\t\tval |= MAC_IF_CFG_CFG2G5;\n+\t\tbreak;\n+\t}\n+\n+\treturn val;\n+}\n+\n+static int mac_set_mii_interface(struct device *dev, u32 mii_mode)\n+{\n+\tstruct gswip_mac *priv = dev_get_drvdata(dev);\n+\tu32 reg_val = 0;\n+\n+\tspin_lock_bh(&priv->mac_lock);\n+\treg_val = sw_read(priv, MAC_IF_CFG_REG(priv->mac_idx));\n+\n+\t/* Default modes...\n+\t *\t\t2.5G -\tXGMAC_GMII\n+\t *\t\t1G   -\tLMAC_GMII\n+\t *\t\tFE   -\tLMAC_MII\n+\t */\n+\tswitch (mii_mode) {\n+\tdefault:\n+\tcase GSW_PORT_HW_XGMII:\n+\t\treg_val |= set_mii_if_2G5(XGMAC_XGMII);\n+\t\tbreak;\n+\n+\tcase GSW_PORT_HW_GMII:\n+\t\treg_val |= set_mii_if_1g(XGMAC_GMII);\n+\t\treg_val |= set_mii_if_fe(XGMAC_GMII);\n+\t\treg_val |= set_mii_if_2G5(XGMAC_GMII);\n+\t\tbreak;\n+\n+\tcase GSW_PORT_HW_MII:\n+\t\treg_val |= set_mii_if_fe(LMAC_MII);\n+\t\tbreak;\n+\t}\n+\n+\tsw_write(priv, MAC_IF_CFG_REG(priv->mac_idx), reg_val);\n+\tspin_unlock_bh(&priv->mac_lock);\n+\n+\treturn 0;\n+}\n+\n+static u32 mac_get_mtu(struct device *dev)\n+{\n+\tstruct gswip_mac *priv = dev_get_drvdata(dev);\n+\tu32 val;\n+\n+\tspin_lock_bh(&priv->mac_lock);\n+\tval = sw_mac_get_mtu(priv);\n+\tspin_unlock_bh(&priv->mac_lock);\n+\n+\treturn val;\n+}\n+\n+static int mac_set_mtu(struct device *dev, u32 mtu)\n+{\n+\tstruct gswip_mac *priv = dev_get_drvdata(dev);\n+\n+\tif (mtu > LGM_MAX_MTU)\n+\t\treturn -EINVAL;\n+\n+\tspin_lock_bh(&priv->mac_lock);\n+\tsw_mac_set_mtu(priv, mtu);\n+\txgmac_config_pkt(priv, mtu);\n+\tspin_unlock_bh(&priv->mac_lock);\n+\n+\treturn 0;\n+}\n+\n+static int mac_init(struct device *dev)\n+{\n+\tstruct gswip_mac *priv = dev_get_drvdata(dev);\n+\n+\txgmac_set_mac_address(priv, priv->mac_addr);\n+\tmac_set_mtu(dev, priv->mtu);\n+\txgmac_config_packet_filter(priv, PROMISC);\n+\txgmac_config_packet_filter(priv, PASS_ALL_MULTICAST);\n+\tmac_set_mii_interface(dev, GSW_PORT_HW_GMII);\n+\tmac_set_flowctrl(dev, FC_RXTX);\n+\tmac_set_linksts(priv, LINK_UP);\n+\tmac_set_duplex(priv, GSW_DUPLEX_FULL);\n+\txgmac_set_mac_lpitx(priv, LPITX_EN);\n+\tmac_set_physpeed(priv, SPEED_XGMAC_10G);\n+\t/* Enable XMAC Tx/Rx */\n+\txgmac_enable(priv);\n+\txgmac_pause_frame_filter(priv, 1);\n+\tsw_set_eee_cap(priv, ANEG_EEE_CAP_OFF);\n+\tsw_set_mac_rxfcs_op(priv, MAC_OP_CFG_RX_FCS_M3);\n+\txgmac_mdio_set_clause(priv, MDIO_CLAUSE22, (priv->mac_idx - MAC2));\n+\txgmac_mdio_register(priv);\n+\n+\treturn 0;\n+}\n+\n+static const struct gsw_mac_ops lgm_mac_ops = {\n+\t.init\t\t= mac_init,\n+\t.set_mtu\t= mac_set_mtu,\n+\t.get_mtu\t= mac_get_mtu,\n+\t.set_mii_if\t= mac_set_mii_interface,\n+\t.get_mii_if\t= mac_get_mii_interface,\n+\t.set_flowctrl\t= mac_set_flowctrl,\n+\t.get_link_sts\t= mac_get_linksts,\n+\t.get_duplex\t= mac_get_duplex,\n+\t.get_speed\t= mac_get_speed,\n+};\n+\n+static const struct gsw_adap_ops lgm_adap_ops = {\n+\t.sw_core_enable = sw_core_enable,\n+};\n+\n+void mac_init_ops(struct device *dev)\n+{\n+\tstruct gswip_mac *priv = dev_get_drvdata(dev);\n+\n+\tpriv->mac_ops = &lgm_mac_ops;\n+\tpriv->adap_ops = &lgm_adap_ops;\n+}\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/mac_common.h b/drivers/net/ethernet/intel/gwdpa/gswip/mac_common.h\nnew file mode 100644\nindex 000000000000..581997a615d6\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/mac_common.h\n@@ -0,0 +1,238 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2016-2019 Intel Corporation. */\n+\n+#ifndef _MAC_COMMON_H\n+#define _MAC_COMMON_H\n+\n+#include <linux/io.h>\n+#include <linux/kernel.h>\n+#include <linux/platform_device.h>\n+#include <linux/spinlock.h>\n+\n+#include \"gswip.h\"\n+#include \"gswip_reg.h\"\n+#include \"gswip_dev.h\"\n+\n+#define LGM_MAX_MTU\t10000\n+#define LPITX_EN\t1\n+#define SPEED_LSB\tGENMASK(1, 0)\n+#define SPEED_MSB\tBIT(2)\n+#define MDIO_CLAUSE22\t1\n+#define MDIO_CLAUSE45\t0\n+\n+/* MAC Index */\n+enum mac_index {\n+\tPMAC0 = 0,\n+\tPMAC1,\n+\tMAC2,\n+\tMAC3,\n+\tMAC4,\n+\tMAC5,\n+\tMAC6,\n+\tMAC7,\n+\tMAC8,\n+\tMAC9,\n+\tMAC10,\n+\tPMAC2,\n+\tMAC_LAST,\n+};\n+\n+enum packet_flilter_mode {\n+\tPROMISC = 0,\n+\tPASS_ALL_MULTICAST,\n+\tPKT_FR_DEF,\n+};\n+\n+enum mii_interface {\n+\tLMAC_MII = 0,\n+\tLMAC_GMII,\n+\tXGMAC_GMII,\n+\tXGMAC_XGMII,\n+};\n+\n+enum speed_interface {\n+\tSPEED_10M = 0,\n+\tSPEED_100M,\n+\tSPEED_1G,\n+\tSPEED_10G,\n+\tSPEED_2G5,\n+\tSPEED_5G,\n+\tSPEED_FLEX,\n+\tSPEED_AUTO\n+};\n+\n+enum gsw_fcon {\n+\tFCONRX = 0,\n+\tFCONTX,\n+\tFDUP,\n+};\n+\n+enum xgmac_fcon_on_off {\n+\tXGMAC_FC_EN = 0,\n+\tXGMAC_FC_DIS,\n+};\n+\n+enum gsw_portduplex_mode {\n+\tGSW_DUPLEX_AUTO = 0,\n+\tGSW_DUPLEX_HALF,\n+\tGSW_DUPLEX_FULL,\n+};\n+\n+struct xgmac_hw_features {\n+\t/* HW version */\n+\tu32 version;\n+\n+\t/* HW Feature0 Register: core */\n+\tu32 gmii;\t/* 1000 Mbps support */\n+\tu32 vlhash;\t/* VLAN Hash Filter */\n+\tu32 sma;\t/* SMA(MDIO) Interface */\n+\tu32 rwk;\t/* PMT remote wake-up packet */\n+\tu32 mgk;\t/* PMT magic packet */\n+\tu32 mmc;\t/* RMON module */\n+\tu32 aoe;\t/* ARP Offload */\n+\tu32 ts;\t\t/* IEEE 1588-2008 Advanced Timestamp */\n+\tu32 eee;\t/* Energy Efficient Ethernet */\n+\tu32 tx_coe;\t/* Tx Checksum Offload */\n+\tu32 rx_coe;\t/* Rx Checksum Offload */\n+\tu32 addn_mac;\t/* Additional MAC Addresses */\n+\tu32 ts_src;\t/* Timestamp Source */\n+\tu32 sa_vlan_ins;/* Source Address or VLAN Insertion */\n+\tu32 vxn;\t/* VxLAN/NVGRE Support */\n+\tu32 ediffc;\t/* Different Descriptor Cache */\n+\tu32 edma;\t/* Enhanced DMA */\n+\n+\t/* HW Feature1 Register: DMA and MTL */\n+\tu32 rx_fifo_size;\t/* MTL Receive FIFO Size */\n+\tu32 tx_fifo_size;\t/* MTL Transmit FIFO Size */\n+\tu32 osten;\t\t/* One-Step Timestamping Enable */\n+\tu32 ptoen;\t\t/* PTP Offload Enable */\n+\tu32 adv_ts_hi;\t\t/* Advance Timestamping High Word */\n+\tu32 dma_width;\t\t/* DMA width */\n+\tu32 dcb;\t\t/* DCB Feature */\n+\tu32 sph;\t\t/* Split Header Feature */\n+\tu32 tso;\t\t/* TCP Segmentation Offload */\n+\tu32 dma_debug;\t\t/* DMA Debug Registers */\n+\tu32 rss;\t\t/* Receive Side Scaling */\n+\tu32 tc_cnt;\t\t/* Number of Traffic Classes */\n+\tu32 hash_table_size;\t/* Hash Table Size */\n+\tu32 l3l4_filter_num;\t/* Number of L3-L4 Filters */\n+\n+\t/* HW Feature2 Register: Channels(DMA) and Queues(MTL) */\n+\tu32 rx_q_cnt;\t\t/* Number of MTL Receive Queues */\n+\tu32 tx_q_cnt;\t\t/* Number of MTL Transmit Queues */\n+\tu32 rx_ch_cnt;\t\t/* Number of DMA Receive Channels */\n+\tu32 tx_ch_cnt;\t\t/* Number of DMA Transmit Channels */\n+\tu32 pps_out_num;\t/* Number of PPS outputs */\n+\tu32 aux_snap_num;\t/* Number of Aux snapshot inputs */\n+};\n+\n+struct gswip_mac {\n+\tvoid __iomem *sw;\t/* adaption layer */\n+\tvoid __iomem *lmac;\t/* legacy mac */\n+\n+\t/* XGMAC registers for indirect accessing */\n+\tu32 xgmac_ctrl_reg;\n+\tu32 xgmac_data0_reg;\n+\tu32 xgmac_data1_reg;\n+\n+\tu32 sw_irq;\n+\tstruct clk *ptp_clk;\n+\tstruct clk *sw_clk;\n+\n+\tstruct device *dev;\n+\tstruct device *parent;\n+\n+\tspinlock_t mac_lock;\t/* MAC spin lock*/\n+\tspinlock_t irw_lock;\t/* lock for Indirect read/write */\n+\tspinlock_t sw_lock;\t/* adaption lock */\n+\n+\t/* Phy status */\n+\tu32 phy_speed;\n+\tconst char *phy_mode;\n+\n+\tu32 ver;\n+\t/* Index to point XGMAC 2/3/4/.. */\n+\tu32 mac_idx;\n+\tu32 mac_max;\n+\tu32 ptp_clk_rate;\n+\n+\tstruct xgmac_hw_features hw_feat;\n+\tconst struct gsw_mac_ops *mac_ops;\n+\n+\tconst struct gsw_adap_ops *adap_ops;\n+\tu32 core_en_cnt;\n+\tstruct mii_bus *mii;\n+\n+\tu8 mac_addr[6];\n+\tu32 mtu;\n+\tbool promisc_mode;\n+\tbool all_mcast_mode;\n+\tu32 pause_time;\n+};\n+\n+/*  GSWIP-O Top Register write */\n+static inline void sw_write(struct gswip_mac *priv, u32 reg, u32 val)\n+{\n+\twritel(val, priv->sw + reg);\n+}\n+\n+/* GSWIP-O Top Register read */\n+static inline int sw_read(struct gswip_mac *priv, u32 reg)\n+{\n+\treturn readl(priv->sw + reg);\n+}\n+\n+/* Legacy MAC Register read */\n+static inline void lmac_write(struct gswip_mac *priv, u32 reg, u32 val)\n+{\n+\twritel(val, priv->lmac + reg);\n+}\n+\n+/* Legacy MAC Register write */\n+static inline int lmac_read(struct gswip_mac *priv, u32 reg)\n+{\n+\treturn readl(priv->lmac + reg);\n+}\n+\n+/* prototype */\n+void mac_init_ops(struct device *dev);\n+void xgmac_init_priv(struct gswip_mac *priv);\n+void xgmac_get_hw_features(struct gswip_mac *priv);\n+void xgmac_set_mac_address(struct gswip_mac *priv, u8 *mac_addr);\n+void xgmac_config_pkt(struct gswip_mac *priv, u32 mtu);\n+void xgmac_config_packet_filter(struct gswip_mac *priv, u32 mode);\n+void xgmac_tx_flow_ctl(struct gswip_mac *priv, u32 pause_time, u32 mode);\n+void xgmac_rx_flow_ctl(struct gswip_mac *priv, u32 mode);\n+int xgmac_set_mac_lpitx(struct gswip_mac *priv, u32 val);\n+int xgmac_enable(struct gswip_mac *priv);\n+int xgmac_disable(struct gswip_mac *priv);\n+int xgmac_pause_frame_filter(struct gswip_mac *priv, u32 val);\n+int xgmac_set_extcfg(struct gswip_mac *priv, u32 val);\n+int xgmac_set_xgmii_speed(struct gswip_mac *priv);\n+int xgmac_set_gmii_2500_speed(struct gswip_mac *priv);\n+int xgmac_set_xgmii_2500_speed(struct gswip_mac *priv);\n+int xgmac_set_gmii_speed(struct gswip_mac *priv);\n+int xgmac_mdio_set_clause(struct gswip_mac *priv, u32 clause, u32 phy_id);\n+int xgmac_mdio_register(struct gswip_mac *priv);\n+\n+int sw_mac_set_mtu(struct gswip_mac *priv, u32 mtu);\n+u32 sw_mac_get_mtu(struct gswip_mac *priv);\n+u32 sw_get_speed(struct gswip_mac *priv);\n+int sw_set_flowctrl(struct gswip_mac *priv, u8 val, u32 mode);\n+int sw_get_linkstatus(struct gswip_mac *priv);\n+int sw_set_linkstatus(struct gswip_mac *priv, u8 linkst);\n+int sw_get_duplex_mode(struct gswip_mac *priv);\n+int sw_set_duplex_mode(struct gswip_mac *priv, u32 val);\n+int sw_set_speed(struct gswip_mac *priv, u8 speed);\n+int sw_set_2G5_intf(struct gswip_mac *priv, u32 macif);\n+int sw_set_1g_intf(struct gswip_mac *priv, u32 macif);\n+int sw_set_fe_intf(struct gswip_mac *priv, u32 macif);\n+int sw_set_eee_cap(struct gswip_mac *priv, u32 val);\n+int sw_set_mac_rxfcs_op(struct gswip_mac *priv, u32 val);\n+\n+int lmac_set_flowcon_mode(struct gswip_mac *priv, u32 val);\n+int lmac_set_duplex_mode(struct gswip_mac *priv, u32 val);\n+int lmac_set_intf_mode(struct gswip_mac *priv, u32 val);\n+\n+int sw_core_enable(struct device *dev, u32 val);\n+#endif\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/mac_dev.c b/drivers/net/ethernet/intel/gwdpa/gswip/mac_dev.c\nnew file mode 100644\nindex 000000000000..028c580cdf8e\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/mac_dev.c\n@@ -0,0 +1,186 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2016-2019 Intel Corporation.\n+ *\n+ * GSWIP MAC controller driver.\n+ */\n+\n+#include <linux/clk.h>\n+#include <linux/err.h>\n+#include <linux/interrupt.h>\n+#include <linux/irq.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of_platform.h>\n+#include <linux/phy.h>\n+#include <linux/platform_device.h>\n+#include <linux/spinlock.h>\n+\n+#include \"mac_common.h\"\n+\n+#define\tMAX_MAC\t9\n+\n+static const char *link_status_to_str(int link)\n+{\n+\tswitch (link) {\n+\tcase 0:\n+\t\treturn \"DOWN\";\n+\tcase 1:\n+\t\treturn \"UP\";\n+\tdefault:\n+\t\treturn \"UNKNOWN\";\n+\t}\n+}\n+\n+static void gswss_update_interrupt(struct gswip_mac *priv, u32 mask, u32 set)\n+{\n+\tu32 val;\n+\n+\tval = (sw_read(priv, GSWIPSS_IER0) & ~mask) | set;\n+\tsw_write(priv, GSWIPSS_IER0, val);\n+}\n+\n+static void lmac_update_interrupt(struct gswip_mac *priv, u32 mask, u32 set)\n+{\n+\tu32 val;\n+\n+\tval = (lmac_read(priv, LMAC_IER) & ~mask) | set;\n+\tlmac_write(priv, LMAC_IER, val);\n+}\n+\n+static void gswss_clear_interrupt_all(struct gswip_mac *priv)\n+{\n+\tunsigned long xgmac_status, lmac_status;\n+\tu32 pos;\n+\n+\txgmac_status = sw_read(priv, GSWIPSS_ISR0);\n+\tlmac_status = lmac_read(priv, LMAC_ISR);\n+\n+\tpos = GSWIPSS_I_XGMAC2;\n+\tfor_each_set_bit_from(pos, &xgmac_status, priv->mac_max)\n+\t\tgswss_update_interrupt(priv, BIT(pos), 0);\n+\n+\tpos = LMAC_I_MAC2;\n+\tfor_each_set_bit_from(pos, &lmac_status, priv->mac_max)\n+\t\tlmac_update_interrupt(priv, BIT(pos), 0);\n+}\n+\n+static irqreturn_t mac_interrupt(int irq, void *data)\n+{\n+\tstruct gswip_mac *priv = data;\n+\n+\t/* clear all interrupts */\n+\tgswss_clear_interrupt_all(priv);\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+/* All MAC instances have one interrupt line and need to register only once. */\n+static int mac_irq_init(struct gswip_mac *priv)\n+{\n+\treturn devm_request_irq(priv->dev, priv->sw_irq, mac_interrupt, 0,\n+\t\t\t\t\"gswip_mac\", priv);\n+}\n+\n+static int get_mac_index(struct device_node *node, u32 *idx)\n+{\n+\tif (!strstr(node->full_name, \"@\"))\n+\t\treturn -EINVAL;\n+\n+\treturn kstrtou32(node->full_name + strlen(node->name) + 1, 0, idx);\n+}\n+\n+static int mac_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tint linksts, duplex, speed;\n+\tstruct gswip_pdata *pdata;\n+\tstruct device_node *node;\n+\tstruct gswip_mac *priv;\n+\tint ret;\n+\n+\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tnode = dev->of_node;\n+\tpdata = dev_get_platdata(dev->parent);\n+\n+\t/* get the platform data */\n+\tpriv->dev = &pdev->dev;\n+\tpriv->parent = dev->parent;\n+\tpriv->sw = pdata->sw;\n+\tpriv->lmac = pdata->lmac;\n+\tpriv->sw_irq = pdata->sw_irq;\n+\tpriv->ptp_clk = pdata->ptp_clk;\n+\tpriv->sw_clk = pdata->sw_clk;\n+\n+\t/* Initialize spin lock */\n+\tspin_lock_init(&priv->mac_lock);\n+\tspin_lock_init(&priv->irw_lock);\n+\tspin_lock_init(&priv->sw_lock);\n+\n+\tpriv->mac_max =\tMAX_MAC;\n+\tret = get_mac_index(node, &priv->mac_idx);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* check the mac index range */\n+\tif (priv->mac_idx < 0 || priv->mac_idx > priv->mac_max) {\n+\t\tdev_err(dev, \"Mac index Error!!\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpriv->ptp_clk_rate = clk_get_rate(priv->ptp_clk);\n+\n+\tret = of_property_read_string(node, \"phy-mode\", &priv->phy_mode);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = of_property_read_u32(node, \"speed\", &priv->phy_speed);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Request IRQ on first MAC instance */\n+\tif (!pdata->intr_flag) {\n+\t\tret = mac_irq_init(priv);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tpdata->intr_flag = true;\n+\t}\n+\n+\tdev_set_drvdata(dev, priv);\n+\txgmac_init_priv(priv);\n+\txgmac_get_hw_features(priv);\n+\tmac_init_ops(dev);\n+\n+\t/* Initialize MAC */\n+\tpriv->mac_ops->init(dev);\n+\n+\tlinksts = priv->mac_ops->get_link_sts(dev);\n+\tduplex = priv->mac_ops->get_duplex(dev);\n+\tspeed = priv->mac_ops->get_speed(dev);\n+\n+\tpriv->adap_ops->sw_core_enable(dev, 1);\n+\n+\tdev_info(dev, \"Init done - Rev:%x Mac_id:%d Speed=%s Link=%s Duplex=%s\\n\",\n+\t\t priv->ver, priv->mac_idx, phy_speed_to_str(speed),\n+\t\t link_status_to_str(linksts), phy_duplex_to_str(duplex));\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id gswip_mac_match[] = {\n+\t{ .compatible = \"gswip-mac\" },\n+\t{}\n+};\n+MODULE_DEVICE_TABLE(of, gswip_mac_match);\n+\n+static struct platform_driver gswip_mac_driver = {\n+\t.probe = mac_probe,\n+\t.driver = {\n+\t\t.name = \"gswip-mac\",\n+\t\t.of_match_table = gswip_mac_match,\n+\t},\n+};\n+\n+module_platform_driver(gswip_mac_driver);\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/xgmac.c b/drivers/net/ethernet/intel/gwdpa/gswip/xgmac.c\nnew file mode 100644\nindex 000000000000..e3f9d9680579\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/xgmac.c\n@@ -0,0 +1,643 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (c) 2016-2019 Intel Corporation. */\n+\n+#include <linux/bitfield.h>\n+#include <linux/device.h>\n+#include <linux/of_mdio.h>\n+#include <linux/phy.h>\n+\n+#include \"mac_common.h\"\n+#include \"xgmac.h\"\n+\n+/**\n+ * xgmac_reg_rw - XGMAC register indirect read and write access.\n+ * @priv: mac private data.\n+ * @reg: register offset.\n+ * @val:\n+ *\tread - pointer variable to read the value into.\n+ *\twrite - pointer variable to the write value.\n+ * @rd_wr: boolean value, true/false.\n+ *\tfalse - read.\n+ *\ttrue - write.\n+ */\n+static inline void xgmac_reg_rw(struct gswip_mac *priv, u16 reg, u32 *val,\n+\t\t\t\tbool rd_wr)\n+{\n+\tvoid __iomem *xgmac_ctrl_reg  = priv->sw + priv->xgmac_ctrl_reg;\n+\tvoid __iomem *xgmac_data0_reg = priv->sw + priv->xgmac_data0_reg;\n+\tvoid __iomem *xgmac_data1_reg = priv->sw + priv->xgmac_data1_reg;\n+\tu32 access = XGMAC_REGACC_CTRL_ADDR_BAS;\n+\tu32 retries = 2000;\n+\n+\tspin_lock_bh(&priv->irw_lock);\n+\taccess &= ~XGMAC_REGACC_CTRL_OPMOD_WR;\n+\tif (rd_wr) {\n+\t\twritel(FIELD_GET(MASK_HIGH, *val), xgmac_data1_reg);\n+\t\twritel(FIELD_GET(MASK_LOW, *val), xgmac_data0_reg);\n+\t\taccess |= XGMAC_REGACC_CTRL_OPMOD_WR;\n+\t}\n+\n+\twritel(access | reg, xgmac_ctrl_reg);\n+\n+\tdo {\n+\t\tif (!(readl(xgmac_ctrl_reg) & XGMAC_REGACC_CTRL_ADDR_BAS))\n+\t\t\tbreak;\n+\t\tcpu_relax();\n+\t} while (--retries);\n+\tif (!retries)\n+\t\tdev_warn(priv->dev, \"Xgmac register %s failed for Offset %x\\n\",\n+\t\t\t rd_wr ? \"write\" : \"read\", reg);\n+\n+\tif (!rd_wr)\n+\t\t*val = FIELD_PREP(MASK_HIGH, readl(xgmac_data1_reg)) |\n+\t\t       readl(xgmac_data0_reg);\n+\tspin_unlock_bh(&priv->irw_lock);\n+}\n+\n+void xgmac_get_hw_features(struct gswip_mac *priv)\n+{\n+\tstruct xgmac_hw_features *hw_feat = &priv->hw_feat;\n+\tu32 mac_hfr0, mac_hfr1, mac_hfr2;\n+\n+\txgmac_reg_rw(priv, MAC_HW_F0, &mac_hfr0, false);\n+\txgmac_reg_rw(priv, MAC_HW_F1, &mac_hfr1, false);\n+\txgmac_reg_rw(priv, MAC_HW_F2, &mac_hfr2, false);\n+\txgmac_reg_rw(priv, MAC_VER, &hw_feat->version, false);\n+\n+\tpriv->ver = FIELD_GET(MAC_VER_USERVER, hw_feat->version);\n+\n+\t/* Hardware feature0 regiter*/\n+\thw_feat->gmii = FIELD_GET(MAC_HW_F0_GMIISEL, mac_hfr0);\n+\thw_feat->vlhash = FIELD_GET(MAC_HW_F0_VLHASH, mac_hfr0);\n+\thw_feat->sma = FIELD_GET(MAC_HW_F0_SMASEL, mac_hfr0);\n+\thw_feat->rwk = FIELD_GET(MAC_HW_F0_RWKSEL, mac_hfr0);\n+\thw_feat->mgk = FIELD_GET(MAC_HW_F0_MGKSEL, mac_hfr0);\n+\thw_feat->mmc = FIELD_GET(MAC_HW_F0_MMCSEL, mac_hfr0);\n+\thw_feat->aoe = FIELD_GET(MAC_HW_F0_ARPOFFSEL, mac_hfr0);\n+\thw_feat->ts = FIELD_GET(MAC_HW_F0_TSSEL, mac_hfr0);\n+\thw_feat->eee = FIELD_GET(MAC_HW_F0_EEESEL, mac_hfr0);\n+\thw_feat->tx_coe = FIELD_GET(MAC_HW_F0_TXCOESEL, mac_hfr0);\n+\thw_feat->rx_coe = FIELD_GET(MAC_HW_F0_RXCOESEL, mac_hfr0);\n+\thw_feat->addn_mac = FIELD_GET(MAC_HW_F0_ADDMACADRSEL, mac_hfr0);\n+\thw_feat->ts_src = FIELD_GET(MAC_HW_F0_TSSTSSEL, mac_hfr0);\n+\thw_feat->sa_vlan_ins = FIELD_GET(MAC_HW_F0_SAVLANINS, mac_hfr0);\n+\thw_feat->vxn = FIELD_GET(MAC_HW_F0_VXN, mac_hfr0);\n+\thw_feat->ediffc = FIELD_GET(MAC_HW_F0_EDIFFC, mac_hfr0);\n+\thw_feat->edma = FIELD_GET(MAC_HW_F0_EDMA, mac_hfr0);\n+\n+\t/* Hardware feature1 register*/\n+\thw_feat->rx_fifo_size = FIELD_GET(MAC_HW_F1_RXFIFOSIZE, mac_hfr1);\n+\thw_feat->tx_fifo_size = FIELD_GET(MAC_HW_F1_TXFIFOSIZE, mac_hfr1);\n+\thw_feat->osten = FIELD_GET(MAC_HW_F1_OSTEN, mac_hfr1);\n+\thw_feat->ptoen = FIELD_GET(MAC_HW_F1_PTOEN, mac_hfr1);\n+\thw_feat->adv_ts_hi = FIELD_GET(MAC_HW_F1_ADVTHWORD, mac_hfr1);\n+\thw_feat->dma_width = FIELD_GET(MAC_HW_F1_ADDR64, mac_hfr1);\n+\thw_feat->dcb = FIELD_GET(MAC_HW_F1_DCBEN, mac_hfr1);\n+\thw_feat->sph = FIELD_GET(MAC_HW_F1_SPHEN, mac_hfr1);\n+\thw_feat->tso = FIELD_GET(MAC_HW_F1_TSOEN, mac_hfr1);\n+\thw_feat->dma_debug = FIELD_GET(MAC_HW_F1_DBGMEMA, mac_hfr1);\n+\thw_feat->rss = FIELD_GET(MAC_HW_F1_RSSEN, mac_hfr1);\n+\thw_feat->tc_cnt = FIELD_GET(MAC_HW_F1_NUMTC, mac_hfr1);\n+\thw_feat->hash_table_size = FIELD_GET(MAC_HW_F1_HASHTBLSZ, mac_hfr1);\n+\thw_feat->l3l4_filter_num = FIELD_GET(MAC_HW_F1_L3L4FNUM, mac_hfr1);\n+\n+\t/* Hardware feature2 register*/\n+\thw_feat->rx_q_cnt = FIELD_GET(MAC_HW_F2_RXCHCNT, mac_hfr2);\n+\thw_feat->tx_q_cnt = FIELD_GET(MAC_HW_F2_TXQCNT, mac_hfr2);\n+\thw_feat->rx_ch_cnt = FIELD_GET(MAC_HW_F2_RXCHCNT, mac_hfr2);\n+\thw_feat->tx_ch_cnt = FIELD_GET(MAC_HW_F2_TXCHCNT, mac_hfr2);\n+\thw_feat->pps_out_num = FIELD_GET(MAC_HW_F2_PPSOUTNUM, mac_hfr2);\n+\thw_feat->aux_snap_num = FIELD_GET(MAC_HW_F2_AUXSNAPNUM, mac_hfr2);\n+\n+\t/* TC and Queue are zero based so increment to get the actual number */\n+\thw_feat->tc_cnt++;\n+\thw_feat->rx_q_cnt++;\n+\thw_feat->tx_q_cnt++;\n+}\n+\n+void xgmac_init_priv(struct gswip_mac *priv)\n+{\n+\tu8 mac_addr[6] = {0x00, 0x00, 0x94, 0x00, 0x00, 0x08};\n+\n+\tpriv->mac_idx += MAC2;\n+\n+\tpriv->xgmac_ctrl_reg = XGMAC_CTRL_REG(priv->mac_idx);\n+\tpriv->xgmac_data1_reg = XGMAC_DATA1_REG(priv->mac_idx);\n+\tpriv->xgmac_data0_reg = XGMAC_DATA0_REG(priv->mac_idx);\n+\n+\t/* Temp mac addr, Later eth driver will update */\n+\tmac_addr[5] = priv->mac_idx;\n+\tmemcpy(priv->mac_addr, mac_addr, 6);\n+\n+\tpriv->mtu = LGM_MAX_MTU;\n+\tpriv->promisc_mode = true;\n+\tpriv->all_mcast_mode = true;\n+}\n+\n+void xgmac_set_mac_address(struct gswip_mac *priv, u8 *mac_addr)\n+{\n+\tu32 mac_addr_hi, mac_addr_low;\n+\tu32 val;\n+\n+\tmac_addr_hi = (mac_addr[5] << 8) | (mac_addr[4] << 0);\n+\tmac_addr_low = (mac_addr[3] << 24) | (mac_addr[2] << 16) |\n+\t\t\t(mac_addr[1] <<  8) | (mac_addr[0] <<  0);\n+\n+\txgmac_reg_rw(priv, MAC_MACA0HR, &mac_addr_hi, true);\n+\n+\txgmac_reg_rw(priv, MAC_MACA0LR, &val, false);\n+\tif (val != mac_addr_low)\n+\t\txgmac_reg_rw(priv, MAC_MACA0LR, &mac_addr_low, true);\n+}\n+\n+inline void xgmac_prep_pkt_jumbo(u32 mtu, u32 *mac_rcr, u32 *mac_tcr)\n+{\n+\tif (mtu < XGMAC_MAX_GPSL) {\t/* upto 9018 configuration */\n+\t\t*mac_rcr |= MAC_RX_CFG_JE;\n+\t\t*mac_rcr &= ~MAC_RX_CFG_WD & ~MAC_RX_CFG_GPSLCE;\n+\t\t*mac_tcr &= ~MAC_TX_CFG_JD;\n+\n+\t} else {\t\t\t/* upto 16K configuration */\n+\t\t*mac_rcr &= ~MAC_RX_CFG_JE;\n+\t\t*mac_rcr |= MAC_RX_CFG_WD | MAC_RX_CFG_GPSLCE |\n+\t\t\t    FIELD_PREP(MAC_RX_CFG_GPSL,\n+\t\t\t\t       XGMAC_MAX_SUPPORTED_MTU);\n+\t\t*mac_tcr |= MAC_TX_CFG_JD;\n+\t}\n+}\n+\n+inline void xgmac_prep_pkt_standard(u32 *mac_rcr, u32 *mac_tcr)\n+{\n+\t*mac_rcr &= ~MAC_RX_CFG_JE & ~MAC_RX_CFG_WD & ~MAC_RX_CFG_GPSLCE;\n+\t*mac_tcr &= ~MAC_TX_CFG_JD;\n+}\n+\n+void xgmac_config_pkt(struct gswip_mac *priv, u32 mtu)\n+{\n+\tu32 mac_rcr, mac_tcr;\n+\n+\txgmac_reg_rw(priv, MAC_RX_CFG, &mac_rcr, false);\n+\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, false);\n+\n+\tif (mtu > XGMAC_MAX_STD_PACKET)\n+\t\txgmac_prep_pkt_jumbo(mtu, &mac_rcr, &mac_tcr);\n+\telse\n+\t\txgmac_prep_pkt_standard(&mac_rcr, &mac_tcr);\n+\n+\txgmac_reg_rw(priv, MAC_RX_CFG, &mac_rcr, true);\n+\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, true);\n+}\n+\n+void xgmac_config_packet_filter(struct gswip_mac *priv, u32 mode)\n+{\n+\tu32 reg_val;\n+\n+\txgmac_reg_rw(priv, MAC_PKT_FR, &reg_val, false);\n+\n+\tswitch (mode) {\n+\tcase PROMISC:\n+\t\treg_val &= ~MAC_PKT_FR_PR;\n+\t\treg_val |= FIELD_PREP(MAC_PKT_FR_PR, priv->promisc_mode);\n+\t\tbreak;\n+\n+\tcase PASS_ALL_MULTICAST:\n+\t\treg_val &= ~MAC_PKT_FR_PM;\n+\t\treg_val |= FIELD_PREP(MAC_PKT_FR_PM, priv->all_mcast_mode);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\treg_val &= ~MAC_PKT_FR_PR & ~MAC_PKT_FR_PM;\n+\t\treg_val |= FIELD_PREP(MAC_PKT_FR_PR, priv->promisc_mode) |\n+\t\t\t   FIELD_PREP(MAC_PKT_FR_PM, priv->all_mcast_mode);\n+\t}\n+\n+\txgmac_reg_rw(priv, MAC_PKT_FR, &reg_val, true);\n+}\n+\n+void xgmac_tx_flow_ctl(struct gswip_mac *priv, u32 pause_time, u32 mode)\n+{\n+\tu32 reg_val = 0;\n+\n+\txgmac_reg_rw(priv, MAC_TX_FCR, &reg_val, false);\n+\n+\tswitch (mode) {\n+\tcase XGMAC_FC_EN:\n+\t\t/* enable tx flow control */\n+\t\treg_val |= MAC_TX_FCR_TFE;\n+\n+\t\t/* Set pause time */\n+\t\treg_val &= ~MAC_TX_FCR_PT;\n+\t\treg_val |= FIELD_PREP(MAC_TX_FCR_PT, pause_time);\n+\t\tbreak;\n+\n+\tcase XGMAC_FC_DIS:\n+\t\treg_val &= ~MAC_TX_FCR_TFE;\n+\t\tbreak;\n+\t}\n+\n+\txgmac_reg_rw(priv, MAC_TX_FCR, &reg_val, true);\n+}\n+\n+void xgmac_rx_flow_ctl(struct gswip_mac *priv, u32 mode)\n+{\n+\tu32 reg_val = 0;\n+\n+\txgmac_reg_rw(priv, MAC_RX_FCR, &reg_val, false);\n+\n+\tswitch (mode) {\n+\tcase XGMAC_FC_EN:\n+\t\t/* rx fc enable */\n+\t\treg_val |= MAC_RX_FCR_RFE;\n+\t\treg_val &= ~MAC_RX_FCR_PFCE;\n+\t\tbreak;\n+\n+\tcase XGMAC_FC_DIS:\n+\t\treg_val &= ~MAC_RX_FCR_RFE;\n+\t\tbreak;\n+\t}\n+\n+\txgmac_reg_rw(priv, MAC_RX_FCR, &reg_val, true);\n+}\n+\n+int xgmac_set_mac_lpitx(struct gswip_mac *priv, u32 val)\n+{\n+\tu32 lpiate;\n+\n+\txgmac_reg_rw(priv, MAC_LPI_CSR, &lpiate, false);\n+\n+\tif (FIELD_GET(MAC_LPI_CSR_LPIATE, lpiate) != val) {\n+\t\tlpiate &= ~MAC_LPI_CSR_LPIATE;\n+\t\tlpiate |= FIELD_PREP(MAC_LPI_CSR_LPIATE, val);\n+\t}\n+\n+\tif (FIELD_GET(MAC_LPI_CSR_LPITXA, lpiate) != val) {\n+\t\tlpiate &= ~MAC_LPI_CSR_LPITXA;\n+\t\tlpiate |= FIELD_PREP(MAC_LPI_CSR_LPITXA, val);\n+\t}\n+\n+\txgmac_reg_rw(priv, MAC_LPI_CSR, &lpiate, true);\n+\n+\treturn 0;\n+}\n+\n+int xgmac_enable(struct gswip_mac *priv)\n+{\n+\tu32 mac_tcr, mac_rcr, mac_pfr;\n+\n+\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, false);\n+\txgmac_reg_rw(priv, MAC_RX_CFG, &mac_rcr, false);\n+\txgmac_reg_rw(priv, MAC_PKT_FR, &mac_pfr, false);\n+\n+\t/* Enable MAC Tx */\n+\tif (!FIELD_GET(MAC_TX_CFG_TE, mac_tcr)) {\n+\t\tmac_tcr |= MAC_TX_CFG_TE;\n+\t\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, true);\n+\t}\n+\n+\t/* Enable MAC Rx */\n+\tif (!FIELD_GET(MAC_RX_CFG_RE, mac_rcr)) {\n+\t\tmac_rcr |= MAC_RX_CFG_RE;\n+\t\txgmac_reg_rw(priv, MAC_RX_CFG, &mac_rcr, true);\n+\t}\n+\n+\t/* Enable MAC Filter Rx All */\n+\tif (!FIELD_GET(MAC_PKT_FR_RA, mac_pfr)) {\n+\t\tmac_pfr |= MAC_PKT_FR_RA;\n+\t\txgmac_reg_rw(priv, MAC_PKT_FR, &mac_pfr, true);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int xgmac_disable(struct gswip_mac *priv)\n+{\n+\tu32 mac_tcr, mac_rcr, mac_pfr;\n+\n+\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, false);\n+\txgmac_reg_rw(priv, MAC_RX_CFG, &mac_rcr, false);\n+\txgmac_reg_rw(priv, MAC_PKT_FR, &mac_pfr, false);\n+\n+\t/* Disable MAC Tx */\n+\tif (FIELD_GET(MAC_TX_CFG_TE, mac_tcr) != 0) {\n+\t\tmac_tcr &= ~MAC_TX_CFG_TE;\n+\t\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, true);\n+\t}\n+\n+\t/* Disable MAC Rx */\n+\tif (FIELD_GET(MAC_RX_CFG_RE, mac_rcr) != 0) {\n+\t\tmac_rcr &= ~MAC_RX_CFG_RE;\n+\t\txgmac_reg_rw(priv, MAC_RX_CFG, &mac_rcr, true);\n+\t}\n+\n+\t/* Disable MAC Filter Rx All */\n+\tif (FIELD_GET(MAC_PKT_FR_RA, mac_pfr) != 0) {\n+\t\tmac_pfr &= ~MAC_PKT_FR_RA;\n+\t\txgmac_reg_rw(priv, MAC_PKT_FR, &mac_pfr, true);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int xgmac_pause_frame_filter(struct gswip_mac *priv, u32 val)\n+{\n+\tu32 mac_pfr;\n+\n+\txgmac_reg_rw(priv, MAC_PKT_FR, &mac_pfr, false);\n+\n+\tif (FIELD_GET(MAC_PKT_FR_PCF, mac_pfr) != val) {\n+\t\t/* Pause filtering */\n+\t\tmac_pfr &= ~MAC_PKT_FR_PCF;\n+\t\tmac_pfr |= FIELD_PREP(MAC_PKT_FR_PCF, val);\n+\t}\n+\n+\t/* The Receiver module passes only those packets to the application\n+\t * that pass the SA or DA address filter.\n+\t */\n+\tif (FIELD_GET(MAC_PKT_FR_RA, mac_pfr) == 1)\n+\t\tmac_pfr &= ~MAC_PKT_FR_RA;\n+\n+\txgmac_reg_rw(priv, MAC_PKT_FR, &mac_pfr, true);\n+\n+\treturn 0;\n+}\n+\n+int xgmac_set_extcfg(struct gswip_mac *priv, u32 val)\n+{\n+\tu32 mac_extcfg;\n+\n+\txgmac_reg_rw(priv, MAC_EXTCFG, &mac_extcfg, false);\n+\n+\tif (FIELD_GET(MAC_EXTCFG_SBDIOEN, mac_extcfg) != val) {\n+\t\tmac_extcfg &= ~MAC_EXTCFG_SBDIOEN;\n+\t\tmac_extcfg |= FIELD_PREP(MAC_EXTCFG_SBDIOEN, val);\n+\t\txgmac_reg_rw(priv, MAC_EXTCFG, &mac_extcfg, true);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int xgmac_set_xgmii_speed(struct gswip_mac *priv)\n+{\n+\tu32 mac_tcr;\n+\n+\txgmac_disable(priv);\n+\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, false);\n+\n+\tif (FIELD_GET(MAC_TX_CFG_USS, mac_tcr) != 0)\n+\t\tmac_tcr &= ~MAC_TX_CFG_USS;\n+\n+\tif (FIELD_GET(MAC_TX_CFG_SS, mac_tcr) != 0)\n+\t\tmac_tcr &= ~MAC_TX_CFG_SS;\n+\n+\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, true);\n+\txgmac_enable(priv);\n+\n+\treturn 0;\n+}\n+\n+int xgmac_set_gmii_2500_speed(struct gswip_mac *priv)\n+{\n+\tu32 mac_tcr;\n+\n+\txgmac_disable(priv);\n+\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, false);\n+\n+\tif (FIELD_GET(MAC_TX_CFG_USS, mac_tcr) != 0)\n+\t\tmac_tcr &= ~MAC_TX_CFG_USS;\n+\n+\tif (FIELD_GET(MAC_TX_CFG_SS, mac_tcr) != 0x2) {\n+\t\tmac_tcr &= ~MAC_TX_CFG_SS;\n+\t\tmac_tcr |= FIELD_PREP(MAC_TX_CFG_SS, 0x2);\n+\t}\n+\n+\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, true);\n+\txgmac_enable(priv);\n+\n+\treturn 0;\n+}\n+\n+int xgmac_set_xgmii_2500_speed(struct gswip_mac *priv)\n+{\n+\tu32 mac_tcr;\n+\n+\txgmac_disable(priv);\n+\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, false);\n+\n+\tif (FIELD_GET(MAC_TX_CFG_USS, mac_tcr) != 1)\n+\t\tmac_tcr |= MAC_TX_CFG_USS;\n+\n+\tif (FIELD_GET(MAC_TX_CFG_SS, mac_tcr) != 0x2) {\n+\t\tmac_tcr &= ~MAC_TX_CFG_SS;\n+\t\tmac_tcr |= FIELD_PREP(MAC_TX_CFG_SS, 0x2);\n+\t}\n+\n+\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, true);\n+\txgmac_enable(priv);\n+\n+\treturn 0;\n+}\n+\n+int xgmac_set_gmii_speed(struct gswip_mac *priv)\n+{\n+\tu32 mac_tcr;\n+\n+\txgmac_disable(priv);\n+\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, false);\n+\n+\tif (FIELD_GET(MAC_TX_CFG_USS, mac_tcr) != 0)\n+\t\tmac_tcr &= MAC_TX_CFG_USS;\n+\n+\tif (FIELD_GET(MAC_TX_CFG_SS, mac_tcr) != 0x3) {\n+\t\tmac_tcr &= ~MAC_TX_CFG_SS;\n+\t\tmac_tcr |= FIELD_PREP(MAC_TX_CFG_SS, 0x3);\n+\t}\n+\n+\txgmac_reg_rw(priv, MAC_TX_CFG, &mac_tcr, true);\n+\txgmac_enable(priv);\n+\n+\treturn 0;\n+}\n+\n+int xgmac_mdio_set_clause(struct gswip_mac *priv, u32 clause, u32 phy_id)\n+{\n+\tu32 mdio_c22p = 0;\n+\n+\txgmac_reg_rw(priv, MDIO_C22P, &mdio_c22p, false);\n+\n+\tif (clause == MDIO_CLAUSE22)\n+\t\tmdio_c22p |= MDIO_C22P_PORT(phy_id);\n+\telse\n+\t\tmdio_c22p &= ~MDIO_C22P_PORT(phy_id);\n+\n+\t/* Select port 0, 1, 2 and 3 as Clause 22/45 ports */\n+\txgmac_reg_rw(priv, MDIO_C22P, &mdio_c22p, true);\n+\n+\treturn 0;\n+}\n+\n+static int xgmac_mdio_single_wr(struct gswip_mac *priv, u32 dev_adr,\n+\t\t\t\tu32 phy_id, u32 phy_reg, u32 phy_reg_data)\n+{\n+\tu32 mdio_sccdr, mdio_scar;\n+\tu32 retries = 100;\n+\n+\t/* wait for any previous MDIO read/write operation to complete */\n+\t/* Poll */\n+\tdo {\n+\t\txgmac_reg_rw(priv, MDIO_SCCDR, &mdio_sccdr, false);\n+\t\tif (!FIELD_GET(MDIO_SCCDR_BUSY, mdio_sccdr))\n+\t\t\tbreak;\n+\t\tcpu_relax();\n+\t} while (--retries);\n+\tif (!retries) {\n+\t\tdev_err(priv->dev, \"Xgmac MDIO rd/wr operation failed\\n\");\n+\t\treturn -ETIMEDOUT;\n+\t}\n+\n+\txgmac_reg_rw(priv, MDIO_SCAR, &mdio_scar, false);\n+\tmdio_scar &= ~MDIO_SCAR_DA & ~MDIO_SCAR_PA & ~MDIO_SCAR_RA;\n+\tmdio_scar |= FIELD_PREP(MDIO_SCAR_DA, dev_adr);\n+\tmdio_scar |= FIELD_PREP(MDIO_SCAR_PA, phy_id);\n+\tmdio_scar |= FIELD_PREP(MDIO_SCAR_RA, phy_reg);\n+\txgmac_reg_rw(priv, MDIO_SCAR, &mdio_scar, true);\n+\n+\txgmac_reg_rw(priv, MDIO_SCCDR, &mdio_sccdr, false);\n+\tmdio_sccdr &= ~MDIO_SCCDR_SDATA & ~MDIO_SCCDR_CMD;\n+\tmdio_sccdr |= FIELD_PREP(MDIO_SCCDR_SDATA, phy_reg_data);\n+\tmdio_sccdr |= MDIO_SCCDR_BUSY;\n+\tmdio_sccdr &= ~MDIO_SCCDR_SADDR;\n+\tmdio_sccdr |= FIELD_PREP(MDIO_SCCDR_CMD, 1);\n+\txgmac_reg_rw(priv, MDIO_SCCDR, &mdio_sccdr, true);\n+\n+\tretries = 100;\n+\t/* wait for MDIO read operation to complete */\n+\t/* Poll */\n+\tdo {\n+\t\txgmac_reg_rw(priv, MDIO_SCCDR, &mdio_sccdr, false);\n+\t\tif (!FIELD_GET(MDIO_SCCDR_BUSY, mdio_sccdr))\n+\t\t\tbreak;\n+\t\tcpu_relax();\n+\t} while (--retries);\n+\tif (!retries) {\n+\t\tdev_err(priv->dev, \"Xgmac MDIO rd/wr operation failed\\n\");\n+\t\treturn -ETIMEDOUT;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int xgmac_mdio_single_rd(struct gswip_mac *priv, u32 dev_adr,\n+\t\t\t\tu32 phy_id, u32 phy_reg)\n+{\n+\tu32 mdio_sccdr, mdio_scar;\n+\tu32 retries = 100;\n+\tint phy_reg_data;\n+\n+\t/* wait for any previous MDIO read/write operation to complete */\n+\t/* Poll */\n+\tdo {\n+\t\txgmac_reg_rw(priv, MDIO_SCCDR, &mdio_sccdr, false);\n+\t\tif (!FIELD_GET(MDIO_SCCDR_BUSY, mdio_sccdr))\n+\t\t\tbreak;\n+\t\tcpu_relax();\n+\t} while (--retries);\n+\tif (!retries) {\n+\t\tdev_err(priv->dev, \"Xgmac MDIO rd/wr operation failed\\n\");\n+\t\treturn -ETIMEDOUT;\n+\t}\n+\n+\t/* initiate the MDIO read operation by updating desired bits\n+\t * PA - phy address/id (0 - 31)\n+\t * RA - phy register offset\n+\t */\n+\n+\txgmac_reg_rw(priv, MDIO_SCAR, &mdio_scar, false);\n+\tmdio_scar &= ~MDIO_SCAR_DA & ~MDIO_SCAR_PA & ~MDIO_SCAR_RA;\n+\tmdio_scar |= FIELD_PREP(MDIO_SCAR_DA, dev_adr);\n+\tmdio_scar |= FIELD_PREP(MDIO_SCAR_PA, phy_id);\n+\tmdio_scar |= FIELD_PREP(MDIO_SCAR_RA, phy_reg);\n+\txgmac_reg_rw(priv, MDIO_SCAR, &mdio_scar, true);\n+\n+\txgmac_reg_rw(priv, MDIO_SCCDR, &mdio_sccdr, false);\n+\tmdio_sccdr &= ~MDIO_SCCDR_CMD & ~MDIO_SCCDR_SDATA;\n+\tmdio_sccdr |= MDIO_SCCDR_BUSY;\n+\tmdio_sccdr &= ~MDIO_SCCDR_SADDR;\n+\tmdio_sccdr |= FIELD_PREP(MDIO_SCCDR_CMD, 3);\n+\tmdio_sccdr |= FIELD_PREP(MDIO_SCCDR_SDATA, 0);\n+\txgmac_reg_rw(priv, MDIO_SCCDR, &mdio_sccdr, true);\n+\n+\tretries = 100;\n+\t/* wait for MDIO read operation to complete */\n+\t/* Poll */\n+\tdo {\n+\t\txgmac_reg_rw(priv, MDIO_SCCDR, &mdio_sccdr, false);\n+\t\tif (!FIELD_GET(MDIO_SCCDR_BUSY, mdio_sccdr))\n+\t\t\tbreak;\n+\t\tcpu_relax();\n+\t} while (--retries);\n+\tif (!retries) {\n+\t\tdev_err(priv->dev, \"Xgmac MDIO rd/wr operation failed\\n\");\n+\t\treturn -ETIMEDOUT;\n+\t}\n+\n+\t/* read the data */\n+\txgmac_reg_rw(priv, MDIO_SCCDR, &mdio_sccdr, false);\n+\tphy_reg_data = FIELD_GET(MDIO_SCCDR_SDATA, mdio_sccdr);\n+\n+\treturn phy_reg_data;\n+}\n+\n+static int xgmac_mdio_read(struct mii_bus *bus, int phyadr, int phyreg)\n+{\n+\tstruct gswip_mac *priv = bus->priv;\n+\n+\treturn xgmac_mdio_single_rd(priv, 0, phyadr, phyreg);\n+}\n+\n+static int xgmac_mdio_write(struct mii_bus *bus, int phyadr, int phyreg,\n+\t\t\t    u16 phydata)\n+{\n+\tstruct gswip_mac *priv = bus->priv;\n+\n+\treturn xgmac_mdio_single_wr(priv, 0, phyadr, phyreg, phydata);\n+}\n+\n+int xgmac_mdio_register(struct gswip_mac *priv)\n+{\n+\tstruct device_node *mdio_np;\n+\tstruct mii_bus *bus;\n+\tint ret;\n+\n+\tmdio_np = of_get_child_by_name(priv->dev->of_node, \"mdio\");\n+\tif (!mdio_np)\n+\t\treturn -ENOLINK;\n+\n+\tbus = mdiobus_alloc();\n+\tif (!bus)\n+\t\treturn -ENOMEM;\n+\n+\tbus->name = \"xgmac_phy\";\n+\tbus->read = xgmac_mdio_read;\n+\tbus->write = xgmac_mdio_write;\n+\tbus->reset = NULL;\n+\tsnprintf(bus->id, MII_BUS_ID_SIZE, \"%s-%x\", bus->name, priv->mac_idx);\n+\tbus->priv = priv;\n+\tbus->parent = priv->dev;\n+\n+\t/* At this moment gphy is not yet up (firmware not yet loaded), so we\n+\t * avoid auto mdio scan.\n+\t */\n+\tbus->phy_mask = 0xFFFFFFFF;\n+\n+\tret = of_mdiobus_register(bus, mdio_np);\n+\tif (ret) {\n+\t\tmdiobus_free(bus);\n+\t\treturn ret;\n+\t}\n+\n+\tpriv->mii = bus;\n+\tdev_info(priv->dev, \"XGMAC %d: MDIO register Successful\\n\",\n+\t\t priv->mac_idx);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/ethernet/intel/gwdpa/gswip/xgmac.h b/drivers/net/ethernet/intel/gwdpa/gswip/xgmac.h\nnew file mode 100644\nindex 000000000000..0d1be931fcf3\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/gwdpa/gswip/xgmac.h\n@@ -0,0 +1,236 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/* Copyright (c) 2016-2019 Intel Corporation. */\n+/* Xgmac registers indirect access */\n+\n+#ifndef _XGMAC_H\n+#define _XGMAC_H\n+\n+#include <linux/bits.h>\n+\n+/* MAC register offsets */\n+#define MAC_TX_CFG\t\t\t0x0000\n+#define MAC_TX_CFG_TE\t\t\tBIT(0)\n+#define MAC_TX_CFG_DDIC\t\t\tBIT(1)\n+#define MAC_TX_CFG_ISM\t\t\tBIT(3)\n+#define MAC_TX_CFG_ISR\t\t\tGENMASK(7, 4)\n+#define MAC_TX_CFG_IPG\t\t\tGENMASK(10, 8)\n+#define MAC_TX_CFG_IFP\t\t\tBIT(11)\n+#define MAC_TX_CFG_JD\t\t\tBIT(16)\n+#define MAC_TX_CFG_SARC\t\t\tGENMASK(22, 20)\n+#define MAC_TX_CFG_VNE\t\t\tBIT(24)\n+#define MAC_TX_CFG_VNM\t\t\tBIT(25)\n+#define MAC_TX_CFG_G9991EN\t\tBIT(28)\n+#define MAC_TX_CFG_SS\t\t\tGENMASK(30, 29)\n+#define MAC_TX_CFG_USS\t\t\tBIT(31)\n+\n+#define MAC_RX_CFG\t\t\t0x0004\n+#define MAC_RX_CFG_RE\t\t\tBIT(0)\n+#define MAC_RX_CFG_ACS\t\t\tBIT(1)\n+#define MAC_RX_CFG_CST\t\t\tBIT(2)\n+#define MAC_RX_CFG_DCRCC\t\tBIT(3)\n+#define MAC_RX_CFG_SPEN\t\t\tBIT(4)\n+#define MAC_RX_CFG_USP\t\t\tBIT(5)\n+#define MAC_RX_CFG_GPSLCE\t\tBIT(6)\n+#define MAC_RX_CFG_WD\t\t\tBIT(7)\n+#define MAC_RX_CFG_JE\t\t\tBIT(8)\n+#define MAC_RX_CFG_IPC\t\t\tBIT(9)\n+#define MAC_RX_CFG_LM\t\t\tBIT(10)\n+#define MAC_RX_CFG_S2KP\t\t\tBIT(11)\n+#define MAC_RX_CFG_HDSMS\t\tGENMASK(14, 12)\n+#define MAC_RX_CFG_GPSL\t\t\tGENMASK(29, 16)\n+#define MAC_RX_CFG_ELEN\t\t\tBIT(30)\n+#define MAC_RX_CFG_ARPEN\t\tBIT(31)\n+\n+#define MAC_PKT_FR\t\t\t0x0008\n+#define MAC_PKT_FR_PR\t\t\tBIT(0)\n+#define MAC_PKT_FR_HUC\t\t\tBIT(1)\n+#define MAC_PKT_FR_HMC\t\t\tBIT(2)\n+#define MAC_PKT_FR_DAIF\t\t\tBIT(3)\n+#define MAC_PKT_FR_PM\t\t\tBIT(4)\n+#define MAC_PKT_FR_DBF\t\t\tBIT(5)\n+#define MAC_PKT_FR_PCF\t\t\tGENMASK(7, 6)\n+#define MAC_PKT_FR_SAIF\t\t\tBIT(8)\n+#define MAC_PKT_FR_SAF\t\t\tBIT(9)\n+#define MAC_PKT_FR_HPF\t\t\tBIT(10)\n+#define MAC_PKT_FR_VTFE\t\t\tBIT(16)\n+#define MAC_PKT_FR_IPFE\t\t\tBIT(20)\n+#define MAC_PKT_FR_DNTU\t\t\tBIT(21)\n+#define MAC_PKT_FR_VUCC\t\t\tBIT(22)\n+#define MAC_PKT_FR_RA\t\t\tBIT(31)\n+#define MAC_TX_FCR\t\t\t0x0070\n+#define MAC_TX_FCR_FCB\t\t\tBIT(0)\n+#define MAC_TX_FCR_TFE\t\t\tBIT(1)\n+#define MAC_TX_FCR_PLT\t\t\tGENMASK(6, 4)\n+#define MAC_TX_FCR_DZPQ\t\t\tBIT(7)\n+#define MAC_TX_FCR_PT\t\t\tGENMASK(31, 16)\n+\n+#define MAC_TX_FCR1\t\t\t0x0074\n+#define MAC_TX_FCR2\t\t\t0x0078\n+#define MAC_TX_FCR3\t\t\t0x007C\n+#define MAC_TX_FCR4\t\t\t0x0080\n+#define MAC_TX_FCR5\t\t\t0x0084\n+#define MAC_TX_FCR6\t\t\t0x0088\n+#define MAC_TX_FCR7\t\t\t0x008C\n+#define MAC_RX_FCR\t\t\t0x0090\n+#define MAC_RX_FCR_RFE\t\t\tBIT(0)\n+#define MAC_RX_FCR_UP\t\t\tBIT(1)\n+#define MAC_RX_FCR_PFCE\t\t\tBIT(8)\n+\n+#define MAC_ISR\t\t\t\t0x00b0\n+#define MAC_IER\t\t\t\t0x00b4\n+#define MAC_RXTX_STS\t\t\t0x00b8\n+#define MAC_PMT_CSR\t\t\t0x00c0\n+#define MAC_RWK_PFR\t\t\t0x00c4\n+#define MAC_LPI_CSR\t\t\t0x00d0\n+#define MAC_LPI_CSR_TLPIEN\t\tBIT(0)\n+#define MAC_LPI_CSR_TLPIEX\t\tBIT(1)\n+#define MAC_LPI_CSR_RLPIEN\t\tBIT(2)\n+#define MAC_LPI_CSR_RLPIEX\t\tBIT(3)\n+#define MAC_LPI_CSR_TLPIST\t\tBIT(8)\n+#define MAC_LPI_CSR_RLPIST\t\tBIT(9)\n+#define MAC_LPI_CSR_RXRSTP\t\tBIT(10)\n+#define MAC_LPI_CSR_TXRSTP\t\tBIT(11)\n+#define MAC_LPI_CSR_LPITXEN\t\tBIT(16)\n+#define MAC_LPI_CSR_PLS\t\t\tBIT(17)\n+#define MAC_LPI_CSR_PLSDIS\t\tBIT(18)\n+#define MAC_LPI_CSR_LPITXA\t\tBIT(19)\n+#define MAC_LPI_CSR_LPIATE\t\tBIT(20)\n+#define MAC_LPI_CSR_TXCGE\t\tBIT(21)\n+\n+#define MAC_LPI_TCR\t\t\t0x00d4\n+#define MAC_VER\t\t\t\t0x0110\n+#define MAC_VER_USERVER\t\t\tGENMASK(23, 16)\n+\n+#define MAC_HW_F0\t\t\t0x011c\n+#define MAC_HW_F0_GMIISEL\t\tBIT(1)\n+#define MAC_HW_F0_VLHASH\t\tBIT(4)\n+#define MAC_HW_F0_SMASEL\t\tBIT(5)\n+#define MAC_HW_F0_RWKSEL\t\tBIT(6)\n+#define MAC_HW_F0_MGKSEL\t\tBIT(7)\n+#define MAC_HW_F0_MMCSEL\t\tBIT(8)\n+#define MAC_HW_F0_ARPOFFSEL\t\tBIT(9)\n+#define MAC_HW_F0_TSSEL\t\t\tBIT(12)\n+#define MAC_HW_F0_EEESEL\t\tBIT(13)\n+#define MAC_HW_F0_TXCOESEL\t\tBIT(14)\n+#define MAC_HW_F0_RXCOESEL\t\tBIT(16)\n+#define MAC_HW_F0_ADDMACADRSEL\t\tGENMASK(22, 18)\n+#define MAC_HW_F0_TSSTSSEL\t\tGENMASK(26, 25)\n+#define MAC_HW_F0_SAVLANINS\t\tBIT(27)\n+#define MAC_HW_F0_VXN\t\t\tBIT(29)\n+#define MAC_HW_F0_EDIFFC\t\tBIT(30)\n+#define MAC_HW_F0_EDMA\t\t\tBIT(31)\n+\n+#define MAC_HW_F1\t\t\t0x0120\n+#define MAC_HW_F1_RXFIFOSIZE\t\tGENMASK(4, 0)\n+#define MAC_HW_F1_TXFIFOSIZE\t\tGENMASK(10, 6)\n+#define MAC_HW_F1_OSTEN\t\t\tBIT(11)\n+#define MAC_HW_F1_PTOEN\t\t\tBIT(12)\n+#define MAC_HW_F1_ADVTHWORD\t\tBIT(13)\n+#define MAC_HW_F1_ADDR64\t\tGENMASK(15, 14)\n+#define MAC_HW_F1_DCBEN\t\t\tBIT(16)\n+#define MAC_HW_F1_SPHEN\t\t\tBIT(17)\n+#define MAC_HW_F1_TSOEN\t\t\tBIT(18)\n+#define MAC_HW_F1_DBGMEMA\t\tBIT(19)\n+#define MAC_HW_F1_RSSEN\t\t\tBIT(20)\n+#define MAC_HW_F1_NUMTC\t\t\tGENMASK(23, 21)\n+#define MAC_HW_F1_HASHTBLSZ\t\tGENMASK(25, 24)\n+#define MAC_HW_F1_L3L4FNUM\t\tGENMASK(30, 27)\n+\n+#define MAC_HW_F2\t\t\t0x0124\n+#define MAC_HW_F2_RXQCNT\t\tGENMASK(3, 0)\n+#define MAC_HW_F2_TXQCNT\t\tGENMASK(9, 6)\n+#define MAC_HW_F2_RXCHCNT\t\tGENMASK(15, 12)\n+#define MAC_HW_F2_TXCHCNT\t\tGENMASK(21, 18)\n+#define MAC_HW_F2_PPSOUTNUM\t\tGENMASK(26, 24)\n+#define MAC_HW_F2_AUXSNAPNUM\t\tGENMASK(30, 28)\n+\n+#define MAC_EXTCFG\t\t\t0x0140\n+#define MAC_EXTCFG_SBDIOEN\t\tBIT(8)\n+\n+#define MDIO_SCAR\t\t\t0x200\n+#define MDIO_SCAR_RA\t\t\tGENMASK(15, 0)\n+#define MDIO_SCAR_PA\t\t\tGENMASK(20, 16)\n+#define MDIO_SCAR_DA\t\t\tGENMASK(25, 21)\n+\n+#define MDIO_SCCDR\t\t\t0x204\n+#define MDIO_SCCDR_SDATA\t\tGENMASK(15, 0)\n+#define MDIO_SCCDR_CMD\t\t\tGENMASK(17, 16)\n+#define MDIO_SCCDR_SADDR\t\tBIT(18)\n+#define MDIO_SCCDR_CR\t\t\tGENMASK(21, 19)\n+#define MDIO_SCCDR_BUSY\t\t\tBIT(22)\n+\n+#define MDIO_C22P\t\t\t0x220\n+#define MDIO_C22P_PORT(idx)\t\tBIT(idx)\n+\n+#define MAC_MACA0HR\t\t\t0x0300\n+#define MAC_MACA0LR\t\t\t0x0304\n+#define MAC_MACA1HR\t\t\t0x0308\n+#define MAC_MACA1LR\t\t\t0x030c\n+\n+#define MMC_CR\t\t\t\t0x0800\n+\n+#define MMC_TXOCTETCOUNT_GB_LO\t\t0x0814\n+#define MMC_TXFRAMECOUNT_GB_LO\t\t0x081c\n+#define MMC_TXBROADCASTFRAMES_G_LO\t0x0824\n+#define MMC_TXMULTICASTFRAMES_G_LO\t0x082c\n+#define MMC_TXUNICASTFRAMES_GB_LO\t0x0864\n+#define MMC_TXMULTICASTFRAMES_GB_LO\t0x086c\n+#define MMC_TXBROADCASTFRAMES_GB_LO\t0x0874\n+#define MMC_TXUNDERFLOWERROR_LO\t\t0x087c\n+#define MMC_TXOCTETCOUNT_G_LO\t\t0x0884\n+#define MMC_TXFRAMECOUNT_G_LO\t\t0x088c\n+#define MMC_TXPAUSEFRAMES_LO\t\t0x0894\n+#define MMC_TXVLANFRAMES_G_LO\t\t0x089c\n+\n+#define MMC_RXFRAMECOUNT_GB_LO\t\t0x0900\n+#define MMC_RXOCTETCOUNT_GB_LO\t\t0x0908\n+#define MMC_RXOCTETCOUNT_G_LO\t\t0x0910\n+#define MMC_RXBROADCASTFRAMES_G_LO\t0x0918\n+#define MMC_RXMULTICASTFRAMES_G_LO\t0x0920\n+#define MMC_RXCRCERROR_LO\t\t0x0928\n+#define MMC_RXRUNTERROR\t\t\t0x0930\n+#define MMC_RXJABBERERROR\t\t0x0934\n+#define MMC_RXUNDERSIZE_G\t\t0x0938\n+#define MMC_RXOVERSIZE_G\t\t0x093c\n+#define MMC_RXUNICASTFRAMES_G_LO\t0x0970\n+#define MMC_RXLENGTHERROR_LO\t\t0x0978\n+#define MMC_RXOUTOFRANGETYPE_LO\t\t0x0980\n+#define MMC_RXPAUSEFRAMES_LO\t\t0x0988\n+#define MMC_RXFIFOOVERFLOW_LO\t\t0x0990\n+#define MMC_RXVLANFRAMES_GB_LO\t\t0x0998\n+#define MMC_RXWATCHDOGERROR\t\t0x09a0\n+\n+#define MAC_TSTAMP_CR\t\t\t0x0d00\n+#define MAC_SUBSEC_INCR\t\t\t0x0d04\n+#define MAC_SYS_TIME_SEC\t\t0x0d08\n+#define MAC_SYS_TIME_NSEC\t\t0x0d0c\n+#define MAC_SYS_TIME_SEC_UPD\t\t0x0d10\n+#define MAC_SYS_TIME_NSEC_UPD\t\t0x0d14\n+#define MAC_TSTAMP_ADDNDR\t\t0x0d18\n+#define MAC_TSTAMP_STSR\t\t\t0x0d20\n+#define MAC_TXTSTAMP_NSECR\t\t0x0d30\n+#define MAC_TXTSTAMP_SECR\t\t0x0d34\n+#define MAC_TXTSTAMP_STS\t\t0x0d38\n+#define MAC_AUX_CTRL\t\t\t0x0d40\n+#define MAC_AUX_NSEC\t\t\t0x0d48\n+#define MAC_AUX_SEC\t\t\t0x0d4c\n+#define MAC_RX_PCH_CRC_CNT\t\t0x0d2c\n+\n+#define XGMAC_Q_INC\t\t\t0x100\n+#define XGMAC_CTRL_REG(idx)\t\t\t\t\t\\\n+\t(XGMAC_REGACC_CTRL + ((idx) - MAC2) * XGMAC_Q_INC)\n+#define XGMAC_DATA0_REG(idx)\t\t\t\t\t\\\n+\t(XGMAC_REGACC_DATA0 + ((idx) - MAC2) * XGMAC_Q_INC)\n+#define XGMAC_DATA1_REG(idx)\t\t\t\t\t\\\n+\t(XGMAC_REGACC_DATA1 + ((idx) - MAC2) * XGMAC_Q_INC)\n+\n+#define MASK_LOW\t\t\tGENMASK(15, 0)\n+#define MASK_HIGH\t\t\tGENMASK(31, 16)\n+\n+/* gaint packet size limit */\n+#define XGMAC_MAX_GPSL\t\t\t9000\n+#define XGMAC_MAX_SUPPORTED_MTU\t\t16380\n+\n+#define XGMAC_MAX_STD_PACKET\t\t1518\n+\n+#endif\n",
    "prefixes": [
        "next-queue",
        "v3"
    ]
}