Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1253347/?format=api
{ "id": 1253347, "url": "http://patchwork.ozlabs.org/api/patches/1253347/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200312015818.1007882-3-jacob.e.keller@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20200312015818.1007882-3-jacob.e.keller@intel.com>", "list_archive_url": null, "date": "2020-03-12T01:58:11", "name": "[v3,2/9] ice: create function to read a section of the NVM and Shadow RAM", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "8856690ed23532da1dfbc68875f824e1ab75d46a", "submitter": { "id": 9784, "url": "http://patchwork.ozlabs.org/api/people/9784/?format=api", "name": "Jacob Keller", "email": "jacob.e.keller@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200312015818.1007882-3-jacob.e.keller@intel.com/mbox/", "series": [ { "id": 163869, "url": "http://patchwork.ozlabs.org/api/series/163869/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=163869", "date": "2020-03-12T01:58:10", "name": "ice devlink support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/163869/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1253347/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1253347/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=osuosl.org (client-ip=140.211.166.138;\n\thelo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 48dBnT0R2Dz9sPK\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 12 Mar 2020 12:58:37 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 9922186837;\n\tThu, 12 Mar 2020 01:58:35 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id OHIMvD0VoyDZ; Thu, 12 Mar 2020 01:58:30 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 8C20B88AB4;\n\tThu, 12 Mar 2020 01:58:29 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 9E5E31BF473\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 12 Mar 2020 01:58:24 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 968B88854C\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 12 Mar 2020 01:58:24 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id OHQYvvRuHyoG for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 12 Mar 2020 01:58:22 +0000 (UTC)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id 19A0E88541\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 12 Mar 2020 01:58:22 +0000 (UTC)", "from orsmga008.jf.intel.com ([10.7.209.65])\n\tby fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t11 Mar 2020 18:58:21 -0700", "from jekeller-desk.amr.corp.intel.com ([10.166.241.33])\n\tby orsmga008.jf.intel.com with ESMTP; 11 Mar 2020 18:58:21 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,543,1574150400\"; d=\"scan'208\";a=\"236656304\"", "From": "Jacob Keller <jacob.e.keller@intel.com>", "To": "Intel Wired LAN <intel-wired-lan@lists.osuosl.org>", "Date": "Wed, 11 Mar 2020 18:58:11 -0700", "Message-Id": "<20200312015818.1007882-3-jacob.e.keller@intel.com>", "X-Mailer": "git-send-email 2.24.1", "In-Reply-To": "<20200312015818.1007882-1-jacob.e.keller@intel.com>", "References": "<20200312015818.1007882-1-jacob.e.keller@intel.com>", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH v3 2/9] ice: create function to read a\n\tsection of the NVM and Shadow RAM", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "Jakub Kicinski <kuba@kernel.org>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "The NVM contents are read via firmware by using the ice_aq_read_nvm\nfunction. This function has a couple of limits:\n\n1) The AdminQ commands can only take buffers sized up to 4Kb. Thus, any\n larger read must be split into multiple reads.\n2) when reading from the Shadow RAM, reads must not cross sector\n boundaries. The sectors are also 4Kb in size.\n\nImplement the ice_read_flat_nvm function to read portions of the NVM by\nflat offset. That is, to read using offsets from the start of the NVM\nrather than from a specific module.\n\nThis function will be able to read both from the NVM and from the Shadow\nRAM. For simplicity NVM reads will always be broken up to not cross 4Kb\npage boundaries, even though this is not required unless reading from\nthe Shadow RAM.\n\nUse this new function as the implementation of ice_read_sr_word_aq.\n\nThe ice_read_sr_buf_aq function is not modified here. This is because\na following change will remove the only caller of that function in favor\nof directly using ice_read_flat_nvm. Thus, there is little benefit to\nchanging it now only to remove it momentarily. At the same time, the\nice_read_sr_aq function will also be removed.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nReviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com>\n---\n .../net/ethernet/intel/ice/ice_adminq_cmd.h | 2 +\n drivers/net/ethernet/intel/ice/ice_nvm.c | 87 +++++++++++++++++--\n drivers/net/ethernet/intel/ice/ice_nvm.h | 3 +\n 3 files changed, 85 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\nindex 801e4fd40b03..f7d4befcf283 100644\n--- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n@@ -1251,6 +1251,8 @@ struct ice_aqc_nvm {\n \t__le32 addr_low;\n };\n \n+#define ICE_AQC_NVM_START_POINT\t\t\t0\n+\n /* NVM Checksum Command (direct, 0x0706) */\n struct ice_aqc_nvm_checksum {\n \tu8 flags;\ndiff --git a/drivers/net/ethernet/intel/ice/ice_nvm.c b/drivers/net/ethernet/intel/ice/ice_nvm.c\nindex 5597ec50a662..97aaf75379ae 100644\n--- a/drivers/net/ethernet/intel/ice/ice_nvm.c\n+++ b/drivers/net/ethernet/intel/ice/ice_nvm.c\n@@ -11,13 +11,15 @@\n * @length: length of the section to be read (in bytes from the offset)\n * @data: command buffer (size [bytes] = length)\n * @last_command: tells if this is the last command in a series\n+ * @read_shadow_ram: tell if this is a shadow RAM read\n * @cd: pointer to command details structure or NULL\n *\n * Read the NVM using the admin queue commands (0x0701)\n */\n static enum ice_status\n ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,\n-\t\tvoid *data, bool last_command, struct ice_sq_cd *cd)\n+\t\tvoid *data, bool last_command, bool read_shadow_ram,\n+\t\tstruct ice_sq_cd *cd)\n {\n \tstruct ice_aq_desc desc;\n \tstruct ice_aqc_nvm *cmd;\n@@ -30,6 +32,9 @@ ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,\n \n \tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);\n \n+\tif (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)\n+\t\tcmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;\n+\n \t/* If this is the last command in a series, set the proper flag. */\n \tif (last_command)\n \t\tcmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;\n@@ -41,6 +46,68 @@ ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,\n \treturn ice_aq_send_cmd(hw, &desc, data, length, cd);\n }\n \n+/**\n+ * ice_read_flat_nvm - Read portion of NVM by flat offset\n+ * @hw: pointer to the HW struct\n+ * @offset: offset from beginning of NVM\n+ * @length: (in) number of bytes to read; (out) number of bytes actually read\n+ * @data: buffer to return data in (sized to fit the specified length)\n+ * @read_shadow_ram: if true, read from shadow RAM instead of NVM\n+ *\n+ * Reads a portion of the NVM, as a flat memory space. This function correctly\n+ * breaks read requests across Shadow RAM sectors and ensures that no single\n+ * read request exceeds the maximum 4Kb read for a single AdminQ command.\n+ *\n+ * Returns a status code on failure. Note that the data pointer may be\n+ * partially updated if some reads succeed before a failure.\n+ */\n+enum ice_status\n+ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,\n+\t\t bool read_shadow_ram)\n+{\n+\tenum ice_status status;\n+\tu32 inlen = *length;\n+\tu32 bytes_read = 0;\n+\tbool last_cmd;\n+\n+\t*length = 0;\n+\n+\t/* Verify the length of the read if this is for the Shadow RAM */\n+\tif (read_shadow_ram && ((offset + inlen) > (hw->nvm.sr_words * 2u))) {\n+\t\tice_debug(hw, ICE_DBG_NVM,\n+\t\t\t \"NVM error: requested offset is beyond Shadow RAM limit\\n\");\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tdo {\n+\t\tu32 read_size, sector_offset;\n+\n+\t\t/* ice_aq_read_nvm cannot read more than 4Kb at a time.\n+\t\t * Additionally, a read from the Shadow RAM may not cross over\n+\t\t * a sector boundary. Conveniently, the sector size is also\n+\t\t * 4Kb.\n+\t\t */\n+\t\tsector_offset = offset % ICE_AQ_MAX_BUF_LEN;\n+\t\tread_size = min_t(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,\n+\t\t\t\t inlen - bytes_read);\n+\n+\t\tlast_cmd = !(bytes_read + read_size < inlen);\n+\n+\t\tstatus = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,\n+\t\t\t\t\t offset, read_size,\n+\t\t\t\t\t data + bytes_read, last_cmd,\n+\t\t\t\t\t read_shadow_ram, NULL);\n+\t\tif (status)\n+\t\t\tbreak;\n+\n+\t\tbytes_read += read_size;\n+\t\toffset += read_size;\n+\t} while (!last_cmd);\n+\n+\t*length = bytes_read;\n+\treturn status;\n+}\n+\n /**\n * ice_check_sr_access_params - verify params for Shadow RAM R/W operations.\n * @hw: pointer to the HW structure\n@@ -100,7 +167,7 @@ ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, __le16 *data,\n \t */\n \tif (!status)\n \t\tstatus = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data,\n-\t\t\t\t\t last_command, NULL);\n+\t\t\t\t\t last_command, true, NULL);\n \n \treturn status;\n }\n@@ -111,19 +178,25 @@ ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, __le16 *data,\n * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n * @data: word read from the Shadow RAM\n *\n- * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_aq method.\n+ * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.\n */\n static enum ice_status\n ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)\n {\n+\tu32 bytes = sizeof(u16);\n \tenum ice_status status;\n \t__le16 data_local;\n \n-\tstatus = ice_read_sr_aq(hw, offset, 1, &data_local, true);\n-\tif (!status)\n-\t\t*data = le16_to_cpu(data_local);\n+\t/* Note that ice_read_flat_nvm takes into account the 4Kb AdminQ and\n+\t * Shadow RAM sector restrictions necessary when reading from the NVM.\n+\t */\n+\tstatus = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,\n+\t\t\t\t (u8 *)&data_local, true);\n+\tif (status)\n+\t\treturn status;\n \n-\treturn status;\n+\t*data = le16_to_cpu(data_local);\n+\treturn 0;\n }\n \n /**\ndiff --git a/drivers/net/ethernet/intel/ice/ice_nvm.h b/drivers/net/ethernet/intel/ice/ice_nvm.h\nindex a9fa011c22c6..4245ef988edf 100644\n--- a/drivers/net/ethernet/intel/ice/ice_nvm.h\n+++ b/drivers/net/ethernet/intel/ice/ice_nvm.h\n@@ -4,5 +4,8 @@\n #ifndef _ICE_NVM_H_\n #define _ICE_NVM_H_\n \n+enum ice_status\n+ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,\n+\t\t bool read_shadow_ram);\n enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);\n #endif /* _ICE_NVM_H_ */\n", "prefixes": [ "v3", "2/9" ] }