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GET /api/patches/1225077/?format=api
{ "id": 1225077, "url": "http://patchwork.ozlabs.org/api/patches/1225077/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200117153919.50321-4-anthony.l.nguyen@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20200117153919.50321-4-anthony.l.nguyen@intel.com>", "list_archive_url": null, "date": "2020-01-17T15:39:15", "name": "[S36,4/8] ice: Enable writing filtering tables", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "4d8870ecd97af51e426753af553998a864a44373", "submitter": { "id": 68875, "url": "http://patchwork.ozlabs.org/api/people/68875/?format=api", "name": "Tony Nguyen", "email": "anthony.l.nguyen@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20200117153919.50321-4-anthony.l.nguyen@intel.com/mbox/", "series": [ { "id": 153932, "url": "http://patchwork.ozlabs.org/api/series/153932/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=153932", "date": "2020-01-17T15:39:19", "name": "[S36,1/8] ice: Enable writing hardware filtering tables", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/153932/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1225077/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1225077/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=osuosl.org (client-ip=140.211.166.136;\n\thelo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 47zyzm51yFz9s1x\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 18 Jan 2020 11:12:20 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 307762264A;\n\tSat, 18 Jan 2020 00:12:19 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id VECS3UBAWTbt; Sat, 18 Jan 2020 00:12:10 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 0F7482262B;\n\tSat, 18 Jan 2020 00:12:07 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id DF5AD1BF846\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tSat, 18 Jan 2020 00:12:03 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id D7BD72261A\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tSat, 18 Jan 2020 00:12:03 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id e7azizeVkgW7 for <intel-wired-lan@lists.osuosl.org>;\n\tSat, 18 Jan 2020 00:11:57 +0000 (UTC)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby silver.osuosl.org (Postfix) with ESMTPS id 0E95E221B1\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tSat, 18 Jan 2020 00:11:57 +0000 (UTC)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t17 Jan 2020 16:11:56 -0800", "from unknown (HELO localhost.jf.intel.com) ([10.166.244.174])\n\tby orsmga005.jf.intel.com with ESMTP; 17 Jan 2020 16:11:55 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,332,1574150400\"; d=\"scan'208\";a=\"398818586\"", "From": "Tony Nguyen <anthony.l.nguyen@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Fri, 17 Jan 2020 07:39:15 -0800", "Message-Id": "<20200117153919.50321-4-anthony.l.nguyen@intel.com>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20200117153919.50321-1-anthony.l.nguyen@intel.com>", "References": "<20200117153919.50321-1-anthony.l.nguyen@intel.com>", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH S36 4/8] ice: Enable writing filtering\n\ttables", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Write the hardware tables based on the populated software structures.\n\nSigned-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>\nSigned-off-by: Henry Tieman <henry.w.tieman@intel.com>\n---\n .../net/ethernet/intel/ice/ice_adminq_cmd.h | 1 +\n .../net/ethernet/intel/ice/ice_flex_pipe.c | 604 ++++++++++++++++++\n .../net/ethernet/intel/ice/ice_flex_type.h | 46 ++\n 3 files changed, 651 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\nindex f5d5d38a7cc6..2722789fa703 100644\n--- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h\n@@ -1889,6 +1889,7 @@ enum ice_adminq_opc {\n \n \t/* package commands */\n \tice_aqc_opc_download_pkg\t\t\t= 0x0C40,\n+\tice_aqc_opc_update_pkg\t\t\t\t= 0x0C42,\n \tice_aqc_opc_get_pkg_info_list\t\t\t= 0x0C43,\n \n \t/* debug commands */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_flex_pipe.c b/drivers/net/ethernet/intel/ice/ice_flex_pipe.c\nindex 8c93c303a4a5..6dca611b408a 100644\n--- a/drivers/net/ethernet/intel/ice/ice_flex_pipe.c\n+++ b/drivers/net/ethernet/intel/ice/ice_flex_pipe.c\n@@ -5,6 +5,86 @@\n #include \"ice_flex_pipe.h\"\n #include \"ice_flow.h\"\n \n+static const u32 ice_sect_lkup[ICE_BLK_COUNT][ICE_SECT_COUNT] = {\n+\t/* SWITCH */\n+\t{\n+\t\tICE_SID_XLT0_SW,\n+\t\tICE_SID_XLT_KEY_BUILDER_SW,\n+\t\tICE_SID_XLT1_SW,\n+\t\tICE_SID_XLT2_SW,\n+\t\tICE_SID_PROFID_TCAM_SW,\n+\t\tICE_SID_PROFID_REDIR_SW,\n+\t\tICE_SID_FLD_VEC_SW,\n+\t\tICE_SID_CDID_KEY_BUILDER_SW,\n+\t\tICE_SID_CDID_REDIR_SW\n+\t},\n+\n+\t/* ACL */\n+\t{\n+\t\tICE_SID_XLT0_ACL,\n+\t\tICE_SID_XLT_KEY_BUILDER_ACL,\n+\t\tICE_SID_XLT1_ACL,\n+\t\tICE_SID_XLT2_ACL,\n+\t\tICE_SID_PROFID_TCAM_ACL,\n+\t\tICE_SID_PROFID_REDIR_ACL,\n+\t\tICE_SID_FLD_VEC_ACL,\n+\t\tICE_SID_CDID_KEY_BUILDER_ACL,\n+\t\tICE_SID_CDID_REDIR_ACL\n+\t},\n+\n+\t/* FD */\n+\t{\n+\t\tICE_SID_XLT0_FD,\n+\t\tICE_SID_XLT_KEY_BUILDER_FD,\n+\t\tICE_SID_XLT1_FD,\n+\t\tICE_SID_XLT2_FD,\n+\t\tICE_SID_PROFID_TCAM_FD,\n+\t\tICE_SID_PROFID_REDIR_FD,\n+\t\tICE_SID_FLD_VEC_FD,\n+\t\tICE_SID_CDID_KEY_BUILDER_FD,\n+\t\tICE_SID_CDID_REDIR_FD\n+\t},\n+\n+\t/* RSS */\n+\t{\n+\t\tICE_SID_XLT0_RSS,\n+\t\tICE_SID_XLT_KEY_BUILDER_RSS,\n+\t\tICE_SID_XLT1_RSS,\n+\t\tICE_SID_XLT2_RSS,\n+\t\tICE_SID_PROFID_TCAM_RSS,\n+\t\tICE_SID_PROFID_REDIR_RSS,\n+\t\tICE_SID_FLD_VEC_RSS,\n+\t\tICE_SID_CDID_KEY_BUILDER_RSS,\n+\t\tICE_SID_CDID_REDIR_RSS\n+\t},\n+\n+\t/* PE */\n+\t{\n+\t\tICE_SID_XLT0_PE,\n+\t\tICE_SID_XLT_KEY_BUILDER_PE,\n+\t\tICE_SID_XLT1_PE,\n+\t\tICE_SID_XLT2_PE,\n+\t\tICE_SID_PROFID_TCAM_PE,\n+\t\tICE_SID_PROFID_REDIR_PE,\n+\t\tICE_SID_FLD_VEC_PE,\n+\t\tICE_SID_CDID_KEY_BUILDER_PE,\n+\t\tICE_SID_CDID_REDIR_PE\n+\t}\n+};\n+\n+/**\n+ * ice_sect_id - returns section ID\n+ * @blk: block type\n+ * @sect: section type\n+ *\n+ * This helper function returns the proper section ID given a block type and a\n+ * section type.\n+ */\n+static u32 ice_sect_id(enum ice_block blk, enum ice_sect sect)\n+{\n+\treturn ice_sect_lkup[blk][sect];\n+}\n+\n /**\n * ice_pkg_val_buf\n * @buf: pointer to the ice buffer\n@@ -375,6 +455,31 @@ static void ice_release_global_cfg_lock(struct ice_hw *hw)\n \tice_release_res(hw, ICE_GLOBAL_CFG_LOCK_RES_ID);\n }\n \n+/**\n+ * ice_acquire_change_lock\n+ * @hw: pointer to the HW structure\n+ * @access: access type (read or write)\n+ *\n+ * This function will request ownership of the change lock.\n+ */\n+static enum ice_status\n+ice_acquire_change_lock(struct ice_hw *hw, enum ice_aq_res_access_type access)\n+{\n+\treturn ice_acquire_res(hw, ICE_CHANGE_LOCK_RES_ID, access,\n+\t\t\t ICE_CHANGE_LOCK_TIMEOUT);\n+}\n+\n+/**\n+ * ice_release_change_lock\n+ * @hw: pointer to the HW structure\n+ *\n+ * This function will release the change lock using the proper Admin Command.\n+ */\n+static void ice_release_change_lock(struct ice_hw *hw)\n+{\n+\tice_release_res(hw, ICE_CHANGE_LOCK_RES_ID);\n+}\n+\n /**\n * ice_aq_download_pkg\n * @hw: pointer to the hardware structure\n@@ -423,6 +528,54 @@ ice_aq_download_pkg(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf,\n \treturn status;\n }\n \n+/**\n+ * ice_aq_update_pkg\n+ * @hw: pointer to the hardware structure\n+ * @pkg_buf: the package cmd buffer\n+ * @buf_size: the size of the package cmd buffer\n+ * @last_buf: last buffer indicator\n+ * @error_offset: returns error offset\n+ * @error_info: returns error information\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Update Package (0x0C42)\n+ */\n+static enum ice_status\n+ice_aq_update_pkg(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf, u16 buf_size,\n+\t\t bool last_buf, u32 *error_offset, u32 *error_info,\n+\t\t struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_download_pkg *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tif (error_offset)\n+\t\t*error_offset = 0;\n+\tif (error_info)\n+\t\t*error_info = 0;\n+\n+\tcmd = &desc.params.download_pkg;\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_update_pkg);\n+\tdesc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);\n+\n+\tif (last_buf)\n+\t\tcmd->flags |= ICE_AQC_DOWNLOAD_PKG_LAST_BUF;\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, pkg_buf, buf_size, cd);\n+\tif (status == ICE_ERR_AQ_ERROR) {\n+\t\t/* Read error from buffer only when the FW returned an error */\n+\t\tstruct ice_aqc_download_pkg_resp *resp;\n+\n+\t\tresp = (struct ice_aqc_download_pkg_resp *)pkg_buf;\n+\t\tif (error_offset)\n+\t\t\t*error_offset = le32_to_cpu(resp->error_offset);\n+\t\tif (error_info)\n+\t\t\t*error_info = le32_to_cpu(resp->error_info);\n+\t}\n+\n+\treturn status;\n+}\n+\n /**\n * ice_find_seg_in_pkg\n * @hw: pointer to the hardware structure\n@@ -457,6 +610,44 @@ ice_find_seg_in_pkg(struct ice_hw *hw, u32 seg_type,\n \treturn NULL;\n }\n \n+/**\n+ * ice_update_pkg\n+ * @hw: pointer to the hardware structure\n+ * @bufs: pointer to an array of buffers\n+ * @count: the number of buffers in the array\n+ *\n+ * Obtains change lock and updates package.\n+ */\n+static enum ice_status\n+ice_update_pkg(struct ice_hw *hw, struct ice_buf *bufs, u32 count)\n+{\n+\tenum ice_status status;\n+\tu32 offset, info, i;\n+\n+\tstatus = ice_acquire_change_lock(hw, ICE_RES_WRITE);\n+\tif (status)\n+\t\treturn status;\n+\n+\tfor (i = 0; i < count; i++) {\n+\t\tstruct ice_buf_hdr *bh = (struct ice_buf_hdr *)(bufs + i);\n+\t\tbool last = ((i + 1) == count);\n+\n+\t\tstatus = ice_aq_update_pkg(hw, bh, le16_to_cpu(bh->data_end),\n+\t\t\t\t\t last, &offset, &info, NULL);\n+\n+\t\tif (status) {\n+\t\t\tice_debug(hw, ICE_DBG_PKG,\n+\t\t\t\t \"Update pkg failed: err %d off %d inf %d\\n\",\n+\t\t\t\t status, offset, info);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tice_release_change_lock(hw);\n+\n+\treturn status;\n+}\n+\n /**\n * ice_dwnld_cfg_bufs\n * @hw: pointer to the hardware structure\n@@ -938,6 +1129,169 @@ enum ice_status ice_copy_and_init_pkg(struct ice_hw *hw, const u8 *buf, u32 len)\n \treturn status;\n }\n \n+/**\n+ * ice_pkg_buf_alloc\n+ * @hw: pointer to the HW structure\n+ *\n+ * Allocates a package buffer and returns a pointer to the buffer header.\n+ * Note: all package contents must be in Little Endian form.\n+ */\n+static struct ice_buf_build *ice_pkg_buf_alloc(struct ice_hw *hw)\n+{\n+\tstruct ice_buf_build *bld;\n+\tstruct ice_buf_hdr *buf;\n+\n+\tbld = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*bld), GFP_KERNEL);\n+\tif (!bld)\n+\t\treturn NULL;\n+\n+\tbuf = (struct ice_buf_hdr *)bld;\n+\tbuf->data_end = cpu_to_le16(offsetof(struct ice_buf_hdr,\n+\t\t\t\t\t section_entry));\n+\treturn bld;\n+}\n+\n+/**\n+ * ice_pkg_buf_free\n+ * @hw: pointer to the HW structure\n+ * @bld: pointer to pkg build (allocated by ice_pkg_buf_alloc())\n+ *\n+ * Frees a package buffer\n+ */\n+static void ice_pkg_buf_free(struct ice_hw *hw, struct ice_buf_build *bld)\n+{\n+\tdevm_kfree(ice_hw_to_dev(hw), bld);\n+}\n+\n+/**\n+ * ice_pkg_buf_reserve_section\n+ * @bld: pointer to pkg build (allocated by ice_pkg_buf_alloc())\n+ * @count: the number of sections to reserve\n+ *\n+ * Reserves one or more section table entries in a package buffer. This routine\n+ * can be called multiple times as long as they are made before calling\n+ * ice_pkg_buf_alloc_section(). Once ice_pkg_buf_alloc_section()\n+ * is called once, the number of sections that can be allocated will not be able\n+ * to be increased; not using all reserved sections is fine, but this will\n+ * result in some wasted space in the buffer.\n+ * Note: all package contents must be in Little Endian form.\n+ */\n+static enum ice_status\n+ice_pkg_buf_reserve_section(struct ice_buf_build *bld, u16 count)\n+{\n+\tstruct ice_buf_hdr *buf;\n+\tu16 section_count;\n+\tu16 data_end;\n+\n+\tif (!bld)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tbuf = (struct ice_buf_hdr *)&bld->buf;\n+\n+\t/* already an active section, can't increase table size */\n+\tsection_count = le16_to_cpu(buf->section_count);\n+\tif (section_count > 0)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tif (bld->reserved_section_table_entries + count > ICE_MAX_S_COUNT)\n+\t\treturn ICE_ERR_CFG;\n+\tbld->reserved_section_table_entries += count;\n+\n+\tdata_end = le16_to_cpu(buf->data_end) +\n+\t\t (count * sizeof(buf->section_entry[0]));\n+\tbuf->data_end = cpu_to_le16(data_end);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_pkg_buf_alloc_section\n+ * @bld: pointer to pkg build (allocated by ice_pkg_buf_alloc())\n+ * @type: the section type value\n+ * @size: the size of the section to reserve (in bytes)\n+ *\n+ * Reserves memory in the buffer for a section's content and updates the\n+ * buffers' status accordingly. This routine returns a pointer to the first\n+ * byte of the section start within the buffer, which is used to fill in the\n+ * section contents.\n+ * Note: all package contents must be in Little Endian form.\n+ */\n+static void *\n+ice_pkg_buf_alloc_section(struct ice_buf_build *bld, u32 type, u16 size)\n+{\n+\tstruct ice_buf_hdr *buf;\n+\tu16 sect_count;\n+\tu16 data_end;\n+\n+\tif (!bld || !type || !size)\n+\t\treturn NULL;\n+\n+\tbuf = (struct ice_buf_hdr *)&bld->buf;\n+\n+\t/* check for enough space left in buffer */\n+\tdata_end = le16_to_cpu(buf->data_end);\n+\n+\t/* section start must align on 4 byte boundary */\n+\tdata_end = ALIGN(data_end, 4);\n+\n+\tif ((data_end + size) > ICE_MAX_S_DATA_END)\n+\t\treturn NULL;\n+\n+\t/* check for more available section table entries */\n+\tsect_count = le16_to_cpu(buf->section_count);\n+\tif (sect_count < bld->reserved_section_table_entries) {\n+\t\tvoid *section_ptr = ((u8 *)buf) + data_end;\n+\n+\t\tbuf->section_entry[sect_count].offset = cpu_to_le16(data_end);\n+\t\tbuf->section_entry[sect_count].size = cpu_to_le16(size);\n+\t\tbuf->section_entry[sect_count].type = cpu_to_le32(type);\n+\n+\t\tdata_end += size;\n+\t\tbuf->data_end = cpu_to_le16(data_end);\n+\n+\t\tbuf->section_count = cpu_to_le16(sect_count + 1);\n+\t\treturn section_ptr;\n+\t}\n+\n+\t/* no free section table entries */\n+\treturn NULL;\n+}\n+\n+/**\n+ * ice_pkg_buf_get_active_sections\n+ * @bld: pointer to pkg build (allocated by ice_pkg_buf_alloc())\n+ *\n+ * Returns the number of active sections. Before using the package buffer\n+ * in an update package command, the caller should make sure that there is at\n+ * least one active section - otherwise, the buffer is not legal and should\n+ * not be used.\n+ * Note: all package contents must be in Little Endian form.\n+ */\n+static u16 ice_pkg_buf_get_active_sections(struct ice_buf_build *bld)\n+{\n+\tstruct ice_buf_hdr *buf;\n+\n+\tif (!bld)\n+\t\treturn 0;\n+\n+\tbuf = (struct ice_buf_hdr *)&bld->buf;\n+\treturn le16_to_cpu(buf->section_count);\n+}\n+\n+/**\n+ * ice_pkg_buf\n+ * @bld: pointer to pkg build (allocated by ice_pkg_buf_alloc())\n+ *\n+ * Return a pointer to the buffer's header\n+ */\n+static struct ice_buf *ice_pkg_buf(struct ice_buf_build *bld)\n+{\n+\tif (!bld)\n+\t\treturn NULL;\n+\n+\treturn &bld->buf;\n+}\n+\n /* PTG Management */\n \n /**\n@@ -2207,6 +2561,252 @@ ice_has_prof_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig, u64 hdl)\n \treturn false;\n }\n \n+/**\n+ * ice_prof_bld_es - build profile ID extraction sequence changes\n+ * @hw: pointer to the HW struct\n+ * @blk: hardware block\n+ * @bld: the update package buffer build to add to\n+ * @chgs: the list of changes to make in hardware\n+ */\n+static enum ice_status\n+ice_prof_bld_es(struct ice_hw *hw, enum ice_block blk,\n+\t\tstruct ice_buf_build *bld, struct list_head *chgs)\n+{\n+\tu16 vec_size = hw->blk[blk].es.fvw * sizeof(struct ice_fv_word);\n+\tstruct ice_chs_chg *tmp;\n+\n+\tlist_for_each_entry(tmp, chgs, list_entry)\n+\t\tif (tmp->type == ICE_PTG_ES_ADD && tmp->add_prof) {\n+\t\t\tu16 off = tmp->prof_id * hw->blk[blk].es.fvw;\n+\t\t\tstruct ice_pkg_es *p;\n+\t\t\tu32 id;\n+\n+\t\t\tid = ice_sect_id(blk, ICE_VEC_TBL);\n+\t\t\tp = (struct ice_pkg_es *)\n+\t\t\t\tice_pkg_buf_alloc_section(bld, id, sizeof(*p) +\n+\t\t\t\t\t\t\t vec_size -\n+\t\t\t\t\t\t\t sizeof(p->es[0]));\n+\n+\t\t\tif (!p)\n+\t\t\t\treturn ICE_ERR_MAX_LIMIT;\n+\n+\t\t\tp->count = cpu_to_le16(1);\n+\t\t\tp->offset = cpu_to_le16(tmp->prof_id);\n+\n+\t\t\tmemcpy(p->es, &hw->blk[blk].es.t[off], vec_size);\n+\t\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_prof_bld_tcam - build profile ID TCAM changes\n+ * @hw: pointer to the HW struct\n+ * @blk: hardware block\n+ * @bld: the update package buffer build to add to\n+ * @chgs: the list of changes to make in hardware\n+ */\n+static enum ice_status\n+ice_prof_bld_tcam(struct ice_hw *hw, enum ice_block blk,\n+\t\t struct ice_buf_build *bld, struct list_head *chgs)\n+{\n+\tstruct ice_chs_chg *tmp;\n+\n+\tlist_for_each_entry(tmp, chgs, list_entry)\n+\t\tif (tmp->type == ICE_TCAM_ADD && tmp->add_tcam_idx) {\n+\t\t\tstruct ice_prof_id_section *p;\n+\t\t\tu32 id;\n+\n+\t\t\tid = ice_sect_id(blk, ICE_PROF_TCAM);\n+\t\t\tp = (struct ice_prof_id_section *)\n+\t\t\t\tice_pkg_buf_alloc_section(bld, id, sizeof(*p));\n+\n+\t\t\tif (!p)\n+\t\t\t\treturn ICE_ERR_MAX_LIMIT;\n+\n+\t\t\tp->count = cpu_to_le16(1);\n+\t\t\tp->entry[0].addr = cpu_to_le16(tmp->tcam_idx);\n+\t\t\tp->entry[0].prof_id = tmp->prof_id;\n+\n+\t\t\tmemcpy(p->entry[0].key,\n+\t\t\t &hw->blk[blk].prof.t[tmp->tcam_idx].key,\n+\t\t\t sizeof(hw->blk[blk].prof.t->key));\n+\t\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_prof_bld_xlt1 - build XLT1 changes\n+ * @blk: hardware block\n+ * @bld: the update package buffer build to add to\n+ * @chgs: the list of changes to make in hardware\n+ */\n+static enum ice_status\n+ice_prof_bld_xlt1(enum ice_block blk, struct ice_buf_build *bld,\n+\t\t struct list_head *chgs)\n+{\n+\tstruct ice_chs_chg *tmp;\n+\n+\tlist_for_each_entry(tmp, chgs, list_entry)\n+\t\tif (tmp->type == ICE_PTG_ES_ADD && tmp->add_ptg) {\n+\t\t\tstruct ice_xlt1_section *p;\n+\t\t\tu32 id;\n+\n+\t\t\tid = ice_sect_id(blk, ICE_XLT1);\n+\t\t\tp = (struct ice_xlt1_section *)\n+\t\t\t\tice_pkg_buf_alloc_section(bld, id, sizeof(*p));\n+\n+\t\t\tif (!p)\n+\t\t\t\treturn ICE_ERR_MAX_LIMIT;\n+\n+\t\t\tp->count = cpu_to_le16(1);\n+\t\t\tp->offset = cpu_to_le16(tmp->ptype);\n+\t\t\tp->value[0] = tmp->ptg;\n+\t\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_prof_bld_xlt2 - build XLT2 changes\n+ * @blk: hardware block\n+ * @bld: the update package buffer build to add to\n+ * @chgs: the list of changes to make in hardware\n+ */\n+static enum ice_status\n+ice_prof_bld_xlt2(enum ice_block blk, struct ice_buf_build *bld,\n+\t\t struct list_head *chgs)\n+{\n+\tstruct ice_chs_chg *tmp;\n+\n+\tlist_for_each_entry(tmp, chgs, list_entry) {\n+\t\tstruct ice_xlt2_section *p;\n+\t\tu32 id;\n+\n+\t\tswitch (tmp->type) {\n+\t\tcase ICE_VSIG_ADD:\n+\t\tcase ICE_VSI_MOVE:\n+\t\tcase ICE_VSIG_REM:\n+\t\t\tid = ice_sect_id(blk, ICE_XLT2);\n+\t\t\tp = (struct ice_xlt2_section *)\n+\t\t\t\tice_pkg_buf_alloc_section(bld, id, sizeof(*p));\n+\n+\t\t\tif (!p)\n+\t\t\t\treturn ICE_ERR_MAX_LIMIT;\n+\n+\t\t\tp->count = cpu_to_le16(1);\n+\t\t\tp->offset = cpu_to_le16(tmp->vsi);\n+\t\t\tp->value[0] = cpu_to_le16(tmp->vsig);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_upd_prof_hw - update hardware using the change list\n+ * @hw: pointer to the HW struct\n+ * @blk: hardware block\n+ * @chgs: the list of changes to make in hardware\n+ */\n+static enum ice_status\n+ice_upd_prof_hw(struct ice_hw *hw, enum ice_block blk,\n+\t\tstruct list_head *chgs)\n+{\n+\tstruct ice_buf_build *b;\n+\tstruct ice_chs_chg *tmp;\n+\tenum ice_status status;\n+\tu16 pkg_sects;\n+\tu16 xlt1 = 0;\n+\tu16 xlt2 = 0;\n+\tu16 tcam = 0;\n+\tu16 es = 0;\n+\tu16 sects;\n+\n+\t/* count number of sections we need */\n+\tlist_for_each_entry(tmp, chgs, list_entry) {\n+\t\tswitch (tmp->type) {\n+\t\tcase ICE_PTG_ES_ADD:\n+\t\t\tif (tmp->add_ptg)\n+\t\t\t\txlt1++;\n+\t\t\tif (tmp->add_prof)\n+\t\t\t\tes++;\n+\t\t\tbreak;\n+\t\tcase ICE_TCAM_ADD:\n+\t\t\ttcam++;\n+\t\t\tbreak;\n+\t\tcase ICE_VSIG_ADD:\n+\t\tcase ICE_VSI_MOVE:\n+\t\tcase ICE_VSIG_REM:\n+\t\t\txlt2++;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tsects = xlt1 + xlt2 + tcam + es;\n+\n+\tif (!sects)\n+\t\treturn 0;\n+\n+\t/* Build update package buffer */\n+\tb = ice_pkg_buf_alloc(hw);\n+\tif (!b)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tstatus = ice_pkg_buf_reserve_section(b, sects);\n+\tif (status)\n+\t\tgoto error_tmp;\n+\n+\t/* Preserve order of table update: ES, TCAM, PTG, VSIG */\n+\tif (es) {\n+\t\tstatus = ice_prof_bld_es(hw, blk, b, chgs);\n+\t\tif (status)\n+\t\t\tgoto error_tmp;\n+\t}\n+\n+\tif (tcam) {\n+\t\tstatus = ice_prof_bld_tcam(hw, blk, b, chgs);\n+\t\tif (status)\n+\t\t\tgoto error_tmp;\n+\t}\n+\n+\tif (xlt1) {\n+\t\tstatus = ice_prof_bld_xlt1(blk, b, chgs);\n+\t\tif (status)\n+\t\t\tgoto error_tmp;\n+\t}\n+\n+\tif (xlt2) {\n+\t\tstatus = ice_prof_bld_xlt2(blk, b, chgs);\n+\t\tif (status)\n+\t\t\tgoto error_tmp;\n+\t}\n+\n+\t/* After package buffer build check if the section count in buffer is\n+\t * non-zero and matches the number of sections detected for package\n+\t * update.\n+\t */\n+\tpkg_sects = ice_pkg_buf_get_active_sections(b);\n+\tif (!pkg_sects || pkg_sects != sects) {\n+\t\tstatus = ICE_ERR_INVAL_SIZE;\n+\t\tgoto error_tmp;\n+\t}\n+\n+\t/* update package */\n+\tstatus = ice_update_pkg(hw, ice_pkg_buf(b), 1);\n+\tif (status == ICE_ERR_AQ_ERROR)\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Unable to update HW profile\\n\");\n+\n+error_tmp:\n+\tice_pkg_buf_free(hw, b);\n+\treturn status;\n+}\n+\n /**\n * ice_add_prof - add profile\n * @hw: pointer to the HW struct\n@@ -3097,6 +3697,10 @@ ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl)\n \t\t}\n \t}\n \n+\t/* update hardware */\n+\tif (!status)\n+\t\tstatus = ice_upd_prof_hw(hw, blk, &chg);\n+\n err_ice_add_prof_id_flow:\n \tlist_for_each_entry_safe(del, tmp, &chg, list_entry) {\n \t\tlist_del(&del->list_entry);\ndiff --git a/drivers/net/ethernet/intel/ice/ice_flex_type.h b/drivers/net/ethernet/intel/ice/ice_flex_type.h\nindex 9d95d51bc760..0fb3fe3ff3ea 100644\n--- a/drivers/net/ethernet/intel/ice/ice_flex_type.h\n+++ b/drivers/net/ethernet/intel/ice/ice_flex_type.h\n@@ -108,37 +108,57 @@ struct ice_buf_hdr {\n \tsizeof(struct ice_buf_hdr) - (hd_sz)) / (ent_sz))\n \n /* ice package section IDs */\n+#define ICE_SID_XLT0_SW\t\t\t10\n+#define ICE_SID_XLT_KEY_BUILDER_SW\t11\n #define ICE_SID_XLT1_SW\t\t\t12\n #define ICE_SID_XLT2_SW\t\t\t13\n #define ICE_SID_PROFID_TCAM_SW\t\t14\n #define ICE_SID_PROFID_REDIR_SW\t\t15\n #define ICE_SID_FLD_VEC_SW\t\t16\n+#define ICE_SID_CDID_KEY_BUILDER_SW\t17\n+#define ICE_SID_CDID_REDIR_SW\t\t18\n \n+#define ICE_SID_XLT0_ACL\t\t20\n+#define ICE_SID_XLT_KEY_BUILDER_ACL\t21\n #define ICE_SID_XLT1_ACL\t\t22\n #define ICE_SID_XLT2_ACL\t\t23\n #define ICE_SID_PROFID_TCAM_ACL\t\t24\n #define ICE_SID_PROFID_REDIR_ACL\t25\n #define ICE_SID_FLD_VEC_ACL\t\t26\n+#define ICE_SID_CDID_KEY_BUILDER_ACL\t27\n+#define ICE_SID_CDID_REDIR_ACL\t\t28\n \n+#define ICE_SID_XLT0_FD\t\t\t30\n+#define ICE_SID_XLT_KEY_BUILDER_FD\t31\n #define ICE_SID_XLT1_FD\t\t\t32\n #define ICE_SID_XLT2_FD\t\t\t33\n #define ICE_SID_PROFID_TCAM_FD\t\t34\n #define ICE_SID_PROFID_REDIR_FD\t\t35\n #define ICE_SID_FLD_VEC_FD\t\t36\n+#define ICE_SID_CDID_KEY_BUILDER_FD\t37\n+#define ICE_SID_CDID_REDIR_FD\t\t38\n \n+#define ICE_SID_XLT0_RSS\t\t40\n+#define ICE_SID_XLT_KEY_BUILDER_RSS\t41\n #define ICE_SID_XLT1_RSS\t\t42\n #define ICE_SID_XLT2_RSS\t\t43\n #define ICE_SID_PROFID_TCAM_RSS\t\t44\n #define ICE_SID_PROFID_REDIR_RSS\t45\n #define ICE_SID_FLD_VEC_RSS\t\t46\n+#define ICE_SID_CDID_KEY_BUILDER_RSS\t47\n+#define ICE_SID_CDID_REDIR_RSS\t\t48\n \n #define ICE_SID_RXPARSER_BOOST_TCAM\t56\n \n+#define ICE_SID_XLT0_PE\t\t\t80\n+#define ICE_SID_XLT_KEY_BUILDER_PE\t81\n #define ICE_SID_XLT1_PE\t\t\t82\n #define ICE_SID_XLT2_PE\t\t\t83\n #define ICE_SID_PROFID_TCAM_PE\t\t84\n #define ICE_SID_PROFID_REDIR_PE\t\t85\n #define ICE_SID_FLD_VEC_PE\t\t86\n+#define ICE_SID_CDID_KEY_BUILDER_PE\t87\n+#define ICE_SID_CDID_REDIR_PE\t\t88\n \n /* Label Metadata section IDs */\n #define ICE_SID_LBL_FIRST\t\t0x80000010\n@@ -155,6 +175,19 @@ enum ice_block {\n \tICE_BLK_COUNT\n };\n \n+enum ice_sect {\n+\tICE_XLT0 = 0,\n+\tICE_XLT_KB,\n+\tICE_XLT1,\n+\tICE_XLT2,\n+\tICE_PROF_TCAM,\n+\tICE_PROF_REDIR,\n+\tICE_VEC_TBL,\n+\tICE_CDID_KB,\n+\tICE_CDID_REDIR,\n+\tICE_SECT_COUNT\n+};\n+\n /* package labels */\n struct ice_label {\n \t__le16 value;\n@@ -237,6 +270,13 @@ struct ice_prof_redir_section {\n \tu8 redir_value[1];\n };\n \n+/* package buffer building */\n+\n+struct ice_buf_build {\n+\tstruct ice_buf buf;\n+\tu16 reserved_section_table_entries;\n+};\n+\n struct ice_pkg_enum {\n \tstruct ice_buf_table *buf_table;\n \tu32 buf_idx;\n@@ -251,6 +291,12 @@ struct ice_pkg_enum {\n \tvoid *(*handler)(u32 sect_type, void *section, u32 index, u32 *offset);\n };\n \n+struct ice_pkg_es {\n+\t__le16 count;\n+\t__le16 offset;\n+\tstruct ice_fv_word es[1];\n+};\n+\n struct ice_es {\n \tu32 sid;\n \tu16 count;\n", "prefixes": [ "S36", "4/8" ] }