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GET /api/patches/1213101/?format=api
{ "id": 1213101, "url": "http://patchwork.ozlabs.org/api/patches/1213101/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/6e025830ece2c16c02f0492f51f5705d21381264.1576745635.git.matti.vaittinen@fi.rohmeurope.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<6e025830ece2c16c02f0492f51f5705d21381264.1576745635.git.matti.vaittinen@fi.rohmeurope.com>", "list_archive_url": null, "date": "2019-12-19T09:53:53", "name": "[v7,10/12] gpio: bd71828: Initial support for ROHM BD71828 PMIC GPIOs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f2d54b0687649f87e3e60f721de81d879ffba56a", "submitter": { "id": 74146, "url": "http://patchwork.ozlabs.org/api/people/74146/?format=api", "name": "Matti Vaittinen", "email": "matti.vaittinen@fi.rohmeurope.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/6e025830ece2c16c02f0492f51f5705d21381264.1576745635.git.matti.vaittinen@fi.rohmeurope.com/mbox/", "series": [ { "id": 149534, "url": "http://patchwork.ozlabs.org/api/series/149534/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=149534", "date": "2019-12-19T09:44:08", "name": "Support ROHM BD71828 PMIC", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/149534/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1213101/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1213101/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org; spf=none (no SPF record)\n\tsmtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67;\n\thelo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=fi.rohmeurope.com" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 47dnK04S2tz9sPn\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 19 Dec 2019 20:54:12 +1100 (AEDT)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1726730AbfLSJyF (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tThu, 19 Dec 2019 04:54:05 -0500", "from mail-lj1-f195.google.com ([209.85.208.195]:45514 \"EHLO\n\tmail-lj1-f195.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1726599AbfLSJyF (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Thu, 19 Dec 2019 04:54:05 -0500", "by mail-lj1-f195.google.com with SMTP id j26so5492780ljc.12;\n\tThu, 19 Dec 2019 01:54:02 -0800 (PST)", "from localhost.localdomain\n\t(dyt4gctb359myxd0pkwmt-4.rev.dnainternet.fi.\n\t[2001:14bb:430:5140:37cf:5409:8fcc:4495])\n\tby smtp.gmail.com with ESMTPSA id\n\tw19sm2326219lfl.55.2019.12.19.01.53.59\n\t(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n\tThu, 19 Dec 2019 01:54:00 -0800 (PST)" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=8MRgRjdUo7TxZhFhpwUs1F4Xq7bP5CbQW3oy2437g+0=;\n\tb=abGlU/towqUDfJXxsqooFjhhXxlmZkrB5QKtTzCoFPF0BHgVjsxFQ4MlTCz6k4mwh4\n\trAspbFRqOZnIRVtoCpeC+sJF4PEYlM32FG041zGoKVGxFRnv2xROow818OZrJ1ve5Q+B\n\t9MzQOBjdVZ5pjNU3lboAUfA/zbDsXXvhDqF1XG+WZ5IGNk0Rjf5+IJWoOvZou84fk1Dg\n\tUo1Br9EX6UzjYbcSsfqPkMWerxtRyk0JdPngDKhHju7Kn4yFD2mmenuASr8D2TcPEW67\n\tibg3iVIDehf2im7brTJOijjEiwFr+EIhs5ZM9yFulr+Gd4fURcxLEURKdfadFA9RALGx\n\tw+gA==", "X-Gm-Message-State": "APjAAAWxBbNm30GvlbHtYwE3et2uFT1+wiq2muxGqW6cnPMG3nJmpKOm\n\tnYbac76nyFyZj9tsp7HdZ+Q=", "X-Google-Smtp-Source": "APXvYqwIEGdSQ0oJvIFz2XxjCDKbERJaQW/UjcF3cWdHrZu9BTGN8wM2OPJQKlUzIh2RJ+T6fbQukg==", "X-Received": "by 2002:a2e:8646:: with SMTP id i6mr5277483ljj.122.1576749241229;\n\tThu, 19 Dec 2019 01:54:01 -0800 (PST)", "Date": "Thu, 19 Dec 2019 11:53:53 +0200", "From": "Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>", "To": "matti.vaittinen@fi.rohmeurope.com, mazziesaccount@gmail.com", "Cc": "Jacek Anaszewski <jacek.anaszewski@gmail.com>,\n\tPavel Machek <pavel@ucw.cz>, Dan Murphy <dmurphy@ti.com>,\n\tRob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,\n\tLee Jones <lee.jones@linaro.org>,\n\tMichael Turquette <mturquette@baylibre.com>,\n\tStephen Boyd <sboyd@kernel.org>,\n\tLinus Walleij <linus.walleij@linaro.org>,\n\tBartosz Golaszewski <bgolaszewski@baylibre.com>,\n\tLiam Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>,\n\tAlessandro Zummo <a.zummo@towertech.it>,\n\tAlexandre Belloni <alexandre.belloni@bootlin.com>,\n\tlinux-leds@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org", "Subject": "[PATCH v7 10/12] gpio: bd71828: Initial support for ROHM BD71828\n\tPMIC GPIOs", "Message-ID": "<6e025830ece2c16c02f0492f51f5705d21381264.1576745635.git.matti.vaittinen@fi.rohmeurope.com>", "References": "<cover.1576745635.git.matti.vaittinen@fi.rohmeurope.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=us-ascii", "Content-Disposition": "inline", "In-Reply-To": "<cover.1576745635.git.matti.vaittinen@fi.rohmeurope.com>", "User-Agent": "Mutt/1.12.1 (2019-06-15)", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "ROHM BD71828 PMIC contains 4 pins which can be configured by OTP\nto be used for general purposes. First 3 can be used as outputs\nand 4.th pin can be used as input. Allow them to be controlled\nvia GPIO framework.\n\nThe driver assumes all of the pins are configured as GPIOs and\ntrusts that the reserved pins in other OTP configurations are\nexcluded from control using \"gpio-reserved-ranges\" device tree\nproperty (or left untouched by GPIO users).\n\nTypical use for 4.th pin (input) is to use it as HALL sensor\ninput so that this pin state is toggled when HALL sensor detects\nLID position change (from close to open or open to close). PMIC\nHW implements some extra logic which allows PMIC to power-up the\nsystem when this pin is toggled. Please see the data sheet for\ndetails of GPIO options which can be selected by OTP settings.\n\nSigned-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>\nReviewed-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>\nReviewed-by: Linus Walleij <linus.walleij@linaro.org>\n---\n\nNo changes since v6\n\n drivers/gpio/Kconfig | 12 +++\n drivers/gpio/Makefile | 1 +\n drivers/gpio/gpio-bd71828.c | 159 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 172 insertions(+)\n create mode 100644 drivers/gpio/gpio-bd71828.c", "diff": "diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig\nindex 8adffd42f8cb..68adc1b94dda 100644\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -1021,6 +1021,18 @@ config GPIO_BD70528\n \t This driver can also be built as a module. If so, the module\n \t will be called gpio-bd70528.\n \n+config GPIO_BD71828\n+\ttristate \"ROHM BD71828 GPIO support\"\n+\tdepends on MFD_ROHM_BD71828\n+\thelp\n+\t Support for GPIOs on ROHM BD71828 PMIC. There are three GPIOs\n+\t available on the ROHM PMIC in total. The GPIOs are limited to\n+\t outputs only and pins must be configured to GPIO outputs by\n+\t OTP. Enable this only if you want to use these pins as outputs.\n+\n+\t This driver can also be built as a module. If so, the module\n+\t will be called gpio-bd71828.\n+\n config GPIO_BD9571MWV\n \ttristate \"ROHM BD9571 GPIO support\"\n \tdepends on MFD_BD9571MWV\ndiff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile\nindex 34eb8b2b12dd..8629b81b5c17 100644\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -37,6 +37,7 @@ obj-$(CONFIG_GPIO_ATH79)\t\t+= gpio-ath79.o\n obj-$(CONFIG_GPIO_BCM_KONA)\t\t+= gpio-bcm-kona.o\n obj-$(CONFIG_GPIO_BCM_XGS_IPROC)\t+= gpio-xgs-iproc.o\n obj-$(CONFIG_GPIO_BD70528)\t\t+= gpio-bd70528.o\n+obj-$(CONFIG_GPIO_BD71828)\t\t+= gpio-bd71828.o\n obj-$(CONFIG_GPIO_BD9571MWV)\t\t+= gpio-bd9571mwv.o\n obj-$(CONFIG_GPIO_BRCMSTB)\t\t+= gpio-brcmstb.o\n obj-$(CONFIG_GPIO_BT8XX)\t\t+= gpio-bt8xx.o\ndiff --git a/drivers/gpio/gpio-bd71828.c b/drivers/gpio/gpio-bd71828.c\nnew file mode 100644\nindex 000000000000..04aade9e0a4d\n--- /dev/null\n+++ b/drivers/gpio/gpio-bd71828.c\n@@ -0,0 +1,159 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Copyright (C) 2018 ROHM Semiconductors\n+\n+#include <linux/gpio/driver.h>\n+#include <linux/mfd/rohm-bd71828.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+\n+#define GPIO_OUT_REG(off) (BD71828_REG_GPIO_CTRL1 + (off))\n+#define HALL_GPIO_OFFSET 3\n+\n+/*\n+ * These defines can be removed when\n+ * \"gpio: Add definition for GPIO direction\"\n+ * (9208b1e77d6e8e9776f34f46ef4079ecac9c3c25 in GPIO tree) gets merged,\n+ */\n+#ifndef GPIO_LINE_DIRECTION_IN\n+\t#define GPIO_LINE_DIRECTION_IN 1\n+\t#define GPIO_LINE_DIRECTION_OUT 0\n+#endif\n+\n+struct bd71828_gpio {\n+\tstruct rohm_regmap_dev chip;\n+\tstruct gpio_chip gpio;\n+};\n+\n+static void bd71828_gpio_set(struct gpio_chip *chip, unsigned int offset,\n+\t\t\t int value)\n+{\n+\tint ret;\n+\tstruct bd71828_gpio *bdgpio = gpiochip_get_data(chip);\n+\tu8 val = (value) ? BD71828_GPIO_OUT_HI : BD71828_GPIO_OUT_LO;\n+\n+\t/*\n+\t * The HALL input pin can only be used as input. If this is the pin\n+\t * we are dealing with - then we are done\n+\t */\n+\tif (offset == HALL_GPIO_OFFSET)\n+\t\treturn;\n+\n+\tret = regmap_update_bits(bdgpio->chip.regmap, GPIO_OUT_REG(offset),\n+\t\t\t\t BD71828_GPIO_OUT_MASK, val);\n+\tif (ret)\n+\t\tdev_err(bdgpio->chip.dev, \"Could not set gpio to %d\\n\", value);\n+}\n+\n+static int bd71828_gpio_get(struct gpio_chip *chip, unsigned int offset)\n+{\n+\tint ret;\n+\tunsigned int val;\n+\tstruct bd71828_gpio *bdgpio = gpiochip_get_data(chip);\n+\n+\tif (offset == HALL_GPIO_OFFSET)\n+\t\tret = regmap_read(bdgpio->chip.regmap, BD71828_REG_IO_STAT,\n+\t\t\t\t &val);\n+\telse\n+\t\tret = regmap_read(bdgpio->chip.regmap, GPIO_OUT_REG(offset),\n+\t\t\t\t &val);\n+\tif (!ret)\n+\t\tret = (val & BD71828_GPIO_OUT_MASK);\n+\n+\treturn ret;\n+}\n+\n+static int bd71828_gpio_set_config(struct gpio_chip *chip, unsigned int offset,\n+\t\t\t\t unsigned long config)\n+{\n+\tstruct bd71828_gpio *bdgpio = gpiochip_get_data(chip);\n+\n+\tif (offset == HALL_GPIO_OFFSET)\n+\t\treturn -ENOTSUPP;\n+\n+\tswitch (pinconf_to_config_param(config)) {\n+\tcase PIN_CONFIG_DRIVE_OPEN_DRAIN:\n+\t\treturn regmap_update_bits(bdgpio->chip.regmap,\n+\t\t\t\t\t GPIO_OUT_REG(offset),\n+\t\t\t\t\t BD71828_GPIO_DRIVE_MASK,\n+\t\t\t\t\t BD71828_GPIO_OPEN_DRAIN);\n+\tcase PIN_CONFIG_DRIVE_PUSH_PULL:\n+\t\treturn regmap_update_bits(bdgpio->chip.regmap,\n+\t\t\t\t\t GPIO_OUT_REG(offset),\n+\t\t\t\t\t BD71828_GPIO_DRIVE_MASK,\n+\t\t\t\t\t BD71828_GPIO_PUSH_PULL);\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\treturn -ENOTSUPP;\n+}\n+\n+static int bd71828_get_direction(struct gpio_chip *chip, unsigned int offset)\n+{\n+\t/*\n+\t * Pin usage is selected by OTP data. We can't read it runtime. Hence\n+\t * we trust that if the pin is not excluded by \"gpio-reserved-ranges\"\n+\t * the OTP configuration is set to OUT. (Other pins but HALL input pin\n+\t * on BD71828 can't really be used for general purpose input - input\n+\t * states are used for specific cases like regulator control or\n+\t * PMIC_ON_REQ.\n+\t */\n+\tif (offset == HALL_GPIO_OFFSET)\n+\t\treturn GPIO_LINE_DIRECTION_IN;\n+\n+\treturn GPIO_LINE_DIRECTION_OUT;\n+}\n+\n+static int bd71828_probe(struct platform_device *pdev)\n+{\n+\tstruct bd71828_gpio *bdgpio;\n+\tstruct rohm_regmap_dev *bd71828;\n+\n+\tbd71828 = dev_get_drvdata(pdev->dev.parent);\n+\tif (!bd71828) {\n+\t\tdev_err(&pdev->dev, \"No MFD driver data\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tbdgpio = devm_kzalloc(&pdev->dev, sizeof(*bdgpio),\n+\t\t\t GFP_KERNEL);\n+\tif (!bdgpio)\n+\t\treturn -ENOMEM;\n+\n+\tbdgpio->chip.dev = &pdev->dev;\n+\tbdgpio->gpio.parent = pdev->dev.parent;\n+\tbdgpio->gpio.label = \"bd71828-gpio\";\n+\tbdgpio->gpio.owner = THIS_MODULE;\n+\tbdgpio->gpio.get_direction = bd71828_get_direction;\n+\tbdgpio->gpio.set_config = bd71828_gpio_set_config;\n+\tbdgpio->gpio.can_sleep = true;\n+\tbdgpio->gpio.get = bd71828_gpio_get;\n+\tbdgpio->gpio.set = bd71828_gpio_set;\n+\tbdgpio->gpio.base = -1;\n+\n+\t/*\n+\t * See if we need some implementation to mark some PINs as\n+\t * not controllable based on DT info or if core can handle\n+\t * \"gpio-reserved-ranges\" and exclude them from control\n+\t */\n+\tbdgpio->gpio.ngpio = 4;\n+\tbdgpio->gpio.of_node = pdev->dev.parent->of_node;\n+\tbdgpio->chip.regmap = bd71828->regmap;\n+\n+\treturn devm_gpiochip_add_data(&pdev->dev, &bdgpio->gpio,\n+\t\t\t\t bdgpio);\n+}\n+\n+static struct platform_driver bd71828_gpio = {\n+\t.driver = {\n+\t\t.name = \"bd71828-gpio\"\n+\t},\n+\t.probe = bd71828_probe,\n+};\n+\n+module_platform_driver(bd71828_gpio);\n+\n+MODULE_AUTHOR(\"Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>\");\n+MODULE_DESCRIPTION(\"BD71828 voltage regulator driver\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS(\"platform:bd71828-gpio\");\n", "prefixes": [ "v7", "10/12" ] }