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GET /api/patches/1206963/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 1206963,
    "url": "http://patchwork.ozlabs.org/api/patches/1206963/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/2d546d6bb15ff8b4b75af2220e20db4e634f4145.1575914275.git.landen.chao@mediatek.com/",
    "project": {
        "id": 7,
        "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api",
        "name": "Linux network development",
        "link_name": "netdev",
        "list_id": "netdev.vger.kernel.org",
        "list_email": "netdev@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<2d546d6bb15ff8b4b75af2220e20db4e634f4145.1575914275.git.landen.chao@mediatek.com>",
    "list_archive_url": null,
    "date": "2019-12-10T08:14:38",
    "name": "[net-next,2/6] net: dsa: mt7530: Extend device data ready for adding a new hardware",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": false,
    "hash": "089c0c19f48e1954f55aabb24fdb19ad0dd2122f",
    "submitter": {
        "id": 78098,
        "url": "http://patchwork.ozlabs.org/api/people/78098/?format=api",
        "name": "Landen Chao",
        "email": "landen.chao@mediatek.com"
    },
    "delegate": {
        "id": 34,
        "url": "http://patchwork.ozlabs.org/api/users/34/?format=api",
        "username": "davem",
        "first_name": "David",
        "last_name": "Miller",
        "email": "davem@davemloft.net"
    },
    "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/2d546d6bb15ff8b4b75af2220e20db4e634f4145.1575914275.git.landen.chao@mediatek.com/mbox/",
    "series": [
        {
            "id": 147499,
            "url": "http://patchwork.ozlabs.org/api/series/147499/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=147499",
            "date": "2019-12-10T08:14:36",
            "name": "net-next: dsa: mt7530: add support for MT7531",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/147499/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1206963/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1206963/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<netdev-owner@vger.kernel.org>",
        "X-Original-To": "patchwork-incoming-netdev@ozlabs.org",
        "Delivered-To": "patchwork-incoming-netdev@ozlabs.org",
        "Authentication-Results": [
            "ozlabs.org; spf=none (no SPF record)\n\tsmtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67;\n\thelo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)",
            "ozlabs.org; dmarc=pass (p=none dis=none)\n\theader.from=mediatek.com",
            "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=mediatek.com header.i=@mediatek.com\n\theader.b=\"UJ5NATux\"; dkim-atps=neutral"
        ],
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 47XCY92tBkz9sR7\n\tfor <patchwork-incoming-netdev@ozlabs.org>;\n\tTue, 10 Dec 2019 19:15:25 +1100 (AEDT)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1727003AbfLJIO4 (ORCPT\n\t<rfc822;patchwork-incoming-netdev@ozlabs.org>);\n\tTue, 10 Dec 2019 03:14:56 -0500",
            "from mailgw02.mediatek.com ([210.61.82.184]:45567 \"EHLO\n\tmailgw02.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by\n\tvger.kernel.org with ESMTP id S1726071AbfLJIOy (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Tue, 10 Dec 2019 03:14:54 -0500",
            "from mtkcas09.mediatek.inc [(172.21.101.178)] by\n\tmailgw02.mediatek.com (envelope-from <landen.chao@mediatek.com>)\n\t(Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS)\n\twith ESMTP id 1965641267; Tue, 10 Dec 2019 16:14:46 +0800",
            "from mtkcas08.mediatek.inc (172.21.101.126) by\n\tmtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server\n\t(TLS) id 15.0.1395.4; Tue, 10 Dec 2019 16:14:31 +0800",
            "from mtksdccf07.mediatek.inc (172.21.84.99) by\n\tmtkcas08.mediatek.inc\n\t(172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via\n\tFrontend Transport; Tue, 10 Dec 2019 16:14:26 +0800"
        ],
        "X-UUID": [
            "a18674d7b33c423e9e67b7440f4771cf-20191210",
            "a18674d7b33c423e9e67b7440f4771cf-20191210"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=mediatek.com; s=dk; \n\th=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From;\n\tbh=c2C/fEHYw/8uqadmiP2m2xa2hsUpAd52urXVJTPlYck=; \n\tb=UJ5NATuxMtqHln5i6BTpWiLnxGKgWvp4DpRsKVO2xdnz2cJaT4XL8F/T5fK3CTF4nAai0EKPAcqp+rr8eCLq7uURJv5e5h+ZIzKLSAB4zgnchXesQLo0uFS8vs5w2yp49j6bez1z3v/uN+1+Lpq0uYid9awCqzvbnovrooEysu4=;",
        "From": "Landen Chao <landen.chao@mediatek.com>",
        "To": "<andrew@lunn.ch>, <f.fainelli@gmail.com>,\n\t<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,\n\t<robh+dt@kernel.org>, <mark.rutland@arm.com>",
        "CC": "<devicetree@vger.kernel.org>, <netdev@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>,\n\t<linux-mediatek@lists.infradead.org>, <davem@davemloft.net>,\n\t<sean.wang@mediatek.com>, <opensource@vdorst.com>,\n\t<frank-w@public-files.de>, Landen Chao <landen.chao@mediatek.com>",
        "Subject": "[PATCH net-next 2/6] net: dsa: mt7530: Extend device data ready for\n\tadding a new hardware",
        "Date": "Tue, 10 Dec 2019 16:14:38 +0800",
        "Message-ID": "<2d546d6bb15ff8b4b75af2220e20db4e634f4145.1575914275.git.landen.chao@mediatek.com>",
        "X-Mailer": "git-send-email 2.18.0",
        "In-Reply-To": "<cover.1575914275.git.landen.chao@mediatek.com>",
        "References": "<cover.1575914275.git.landen.chao@mediatek.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-MTK": "N",
        "Content-Transfer-Encoding": "base64",
        "Sender": "netdev-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<netdev.vger.kernel.org>",
        "X-Mailing-List": "netdev@vger.kernel.org"
    },
    "content": "Add a structure holding required operations for each device such as device\ninitialization, PHY port read or write, a checker whether PHY interface is\nsupported on a certain port, MAC port setup for either bus pad or a\nspecific PHY interface.\n\nThe patch is done for ready adding a new hardware MT7531.\n\nSigned-off-by: Landen Chao <landen.chao@mediatek.com>\nSigned-off-by: Sean Wang <sean.wang@mediatek.com>\n---\n drivers/net/dsa/mt7530.c | 231 +++++++++++++++++++++++++++++----------\n drivers/net/dsa/mt7530.h |  29 ++++-\n 2 files changed, 203 insertions(+), 57 deletions(-)",
    "diff": "diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c\r\nindex ed1ec10ec62b..9a648d1f5d09 100644\r\n--- a/drivers/net/dsa/mt7530.c\r\n+++ b/drivers/net/dsa/mt7530.c\r\n@@ -425,7 +425,7 @@ mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,\r\n }\r\n \r\n static int\r\n-mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)\r\n+mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t mode)\r\n {\r\n \tstruct mt7530_priv *priv = ds->priv;\r\n \tu32 ncpo1, ssc_delta, trgint, i, xtal;\r\n@@ -1380,13 +1380,111 @@ mt7530_setup(struct dsa_switch *ds)\r\n \treturn 0;\r\n }\r\n \r\n-static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,\r\n+static bool mt7530_phy_supported(struct dsa_switch *ds, int port,\r\n+\t\t\t\t const struct phylink_link_state *state)\r\n+{\r\n+\tstruct mt7530_priv *priv = ds->priv;\r\n+\r\n+\tswitch (port) {\r\n+\tcase 0: /* Internal phy */\r\n+\tcase 1:\r\n+\tcase 2:\r\n+\tcase 3:\r\n+\tcase 4:\r\n+\t\tif (state->interface != PHY_INTERFACE_MODE_GMII)\r\n+\t\t\tgoto unsupported;\r\n+\t\tbreak;\r\n+\tcase 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */\r\n+\t\tif (!phy_interface_mode_is_rgmii(state->interface) &&\r\n+\t\t    state->interface != PHY_INTERFACE_MODE_MII &&\r\n+\t\t    state->interface != PHY_INTERFACE_MODE_GMII)\r\n+\t\t\tgoto unsupported;\r\n+\t\tbreak;\r\n+\tcase 6: /* 1st cpu port */\r\n+\t\tif (state->interface != PHY_INTERFACE_MODE_RGMII &&\r\n+\t\t    state->interface != PHY_INTERFACE_MODE_TRGMII)\r\n+\t\t\tgoto unsupported;\r\n+\t\tbreak;\r\n+\tdefault:\r\n+\t\tdev_err(priv->dev, \"%s: unsupported port: %i\\n\", __func__,\r\n+\t\t\tport);\r\n+\t\tgoto unsupported;\r\n+\t}\r\n+\r\n+\treturn true;\r\n+\r\n+unsupported:\r\n+\treturn false;\r\n+}\r\n+\r\n+static bool mt753x_phy_supported(struct dsa_switch *ds, int port,\r\n+\t\t\t\t const struct phylink_link_state *state)\r\n+{\r\n+\tstruct mt7530_priv *priv = ds->priv;\r\n+\r\n+\treturn priv->info->phy_supported(ds, port, state);\r\n+}\r\n+\r\n+static int\r\n+mt7530_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)\r\n+{\r\n+\tstruct mt7530_priv *priv = ds->priv;\r\n+\r\n+\t/* Setup TX circuit incluing relevant PAD and driving */\r\n+\tmt7530_pad_clk_setup(ds, state->interface);\r\n+\r\n+\tif (priv->id == ID_MT7530) {\r\n+\t\t/* Setup RX circuit, relevant PAD and driving on the\r\n+\t\t * host which must be placed after the setup on the\r\n+\t\t * device side is all finished.\r\n+\t\t */\r\n+\t\tmt7623_pad_clk_setup(ds);\r\n+\t}\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int\r\n+mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)\r\n+{\r\n+\tstruct mt7530_priv *priv = ds->priv;\r\n+\r\n+\treturn priv->info->pad_setup(ds, state);\r\n+}\r\n+\r\n+static int\r\n+mt7530_mac_setup(struct dsa_switch *ds, int port, unsigned int mode,\r\n+\t\t const struct phylink_link_state *state)\r\n+{\r\n+\tstruct mt7530_priv *priv = ds->priv;\r\n+\r\n+\t/* Only need to setup port5. */\r\n+\tif (port != 5)\r\n+\t\treturn 0;\r\n+\r\n+\tmt7530_setup_port5(priv->ds, state->interface);\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static int mt753x_mac_setup(struct dsa_switch *ds, int port, unsigned int mode,\r\n+\t\t\t    const struct phylink_link_state *state)\r\n+{\r\n+\tstruct mt7530_priv *priv = ds->priv;\r\n+\r\n+\treturn priv->info->mac_setup(ds, port, mode, state);\r\n+}\r\n+\r\n+static void mt753x_phylink_mac_config(struct dsa_switch *ds, int port,\r\n \t\t\t\t      unsigned int mode,\r\n \t\t\t\t      const struct phylink_link_state *state)\r\n {\r\n \tstruct mt7530_priv *priv = ds->priv;\r\n \tu32 mcr_cur, mcr_new;\r\n \r\n+\tif (!mt753x_phy_supported(ds, port, state))\r\n+\t\treturn;\r\n+\r\n \tswitch (port) {\r\n \tcase 0: /* Internal phy */\r\n \tcase 1:\r\n@@ -1399,35 +1497,24 @@ static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,\r\n \tcase 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */\r\n \t\tif (priv->p5_interface == state->interface)\r\n \t\t\tbreak;\r\n-\t\tif (!phy_interface_mode_is_rgmii(state->interface) &&\r\n-\t\t    state->interface != PHY_INTERFACE_MODE_MII &&\r\n-\t\t    state->interface != PHY_INTERFACE_MODE_GMII)\r\n-\t\t\treturn;\r\n \r\n-\t\tmt7530_setup_port5(ds, state->interface);\r\n+\t\tif (mt753x_mac_setup(ds, port, mode, state) < 0)\r\n+\t\t\tgoto unsupported;\r\n+\r\n \t\tbreak;\r\n \tcase 6: /* 1st cpu port */\r\n \t\tif (priv->p6_interface == state->interface)\r\n \t\t\tbreak;\r\n \r\n-\t\tif (state->interface != PHY_INTERFACE_MODE_RGMII &&\r\n-\t\t    state->interface != PHY_INTERFACE_MODE_TRGMII)\r\n-\t\t\treturn;\r\n-\r\n-\t\t/* Setup TX circuit incluing relevant PAD and driving */\r\n-\t\tmt7530_pad_clk_setup(ds, state->interface);\r\n+\t\tmt753x_pad_setup(ds, state);\r\n \r\n-\t\tif (priv->id == ID_MT7530) {\r\n-\t\t\t/* Setup RX circuit, relevant PAD and driving on the\r\n-\t\t\t * host which must be placed after the setup on the\r\n-\t\t\t * device side is all finished.\r\n-\t\t\t */\r\n-\t\t\tmt7623_pad_clk_setup(ds);\r\n-\t\t}\r\n+\t\tif (mt753x_mac_setup(ds, port, mode, state) < 0)\r\n+\t\t\tgoto unsupported;\r\n \r\n \t\tpriv->p6_interface = state->interface;\r\n \t\tbreak;\r\n \tdefault:\r\n+unsupported:\r\n \t\tdev_err(ds->dev, \"%s: unsupported port: %i\\n\", __func__, port);\r\n \t\treturn;\r\n \t}\r\n@@ -1488,38 +1575,14 @@ static void mt7530_phylink_mac_link_up(struct dsa_switch *ds, int port,\r\n \tmt7530_port_set_status(priv, port, 1);\r\n }\r\n \r\n-static void mt7530_phylink_validate(struct dsa_switch *ds, int port,\r\n+static void mt753x_phylink_validate(struct dsa_switch *ds, int port,\r\n \t\t\t\t    unsigned long *supported,\r\n \t\t\t\t    struct phylink_link_state *state)\r\n {\r\n \t__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };\r\n \r\n-\tswitch (port) {\r\n-\tcase 0: /* Internal phy */\r\n-\tcase 1:\r\n-\tcase 2:\r\n-\tcase 3:\r\n-\tcase 4:\r\n-\t\tif (state->interface != PHY_INTERFACE_MODE_NA &&\r\n-\t\t    state->interface != PHY_INTERFACE_MODE_GMII)\r\n-\t\t\tgoto unsupported;\r\n-\t\tbreak;\r\n-\tcase 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */\r\n-\t\tif (state->interface != PHY_INTERFACE_MODE_NA &&\r\n-\t\t    !phy_interface_mode_is_rgmii(state->interface) &&\r\n-\t\t    state->interface != PHY_INTERFACE_MODE_MII &&\r\n-\t\t    state->interface != PHY_INTERFACE_MODE_GMII)\r\n-\t\t\tgoto unsupported;\r\n-\t\tbreak;\r\n-\tcase 6: /* 1st cpu port */\r\n-\t\tif (state->interface != PHY_INTERFACE_MODE_NA &&\r\n-\t\t    state->interface != PHY_INTERFACE_MODE_RGMII &&\r\n-\t\t    state->interface != PHY_INTERFACE_MODE_TRGMII)\r\n-\t\t\tgoto unsupported;\r\n-\t\tbreak;\r\n-\tdefault:\r\n-\t\tdev_err(ds->dev, \"%s: unsupported port: %i\\n\", __func__, port);\r\n-unsupported:\r\n+\tif (state->interface != PHY_INTERFACE_MODE_NA &&\r\n+\t    !mt753x_phy_supported(ds, port, state)) {\r\n \t\tlinkmode_zero(supported);\r\n \t\treturn;\r\n \t}\r\n@@ -1590,12 +1653,36 @@ mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,\r\n \treturn 1;\r\n }\r\n \r\n+static int\r\n+mt753x_setup(struct dsa_switch *ds)\r\n+{\r\n+\tstruct mt7530_priv *priv = ds->priv;\r\n+\r\n+\treturn priv->info->setup(ds);\r\n+}\r\n+\r\n+static int\r\n+mt753x_phy_read(struct dsa_switch *ds, int port, int regnum)\r\n+{\r\n+\tstruct mt7530_priv *priv = ds->priv;\r\n+\r\n+\treturn priv->info->phy_read(ds, port, regnum);\r\n+}\r\n+\r\n+static int\r\n+mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)\r\n+{\r\n+\tstruct mt7530_priv *priv = ds->priv;\r\n+\r\n+\treturn priv->info->phy_write(ds, port, regnum, val);\r\n+}\r\n+\r\n static const struct dsa_switch_ops mt7530_switch_ops = {\r\n \t.get_tag_protocol\t= mtk_get_tag_protocol,\r\n-\t.setup\t\t\t= mt7530_setup,\r\n+\t.setup\t\t\t= mt753x_setup,\r\n \t.get_strings\t\t= mt7530_get_strings,\r\n-\t.phy_read\t\t= mt7530_phy_read,\r\n-\t.phy_write\t\t= mt7530_phy_write,\r\n+\t.phy_read\t\t= mt753x_phy_read,\r\n+\t.phy_write\t\t= mt753x_phy_write,\r\n \t.get_ethtool_stats\t= mt7530_get_ethtool_stats,\r\n \t.get_sset_count\t\t= mt7530_get_sset_count,\r\n \t.port_enable\t\t= mt7530_port_enable,\r\n@@ -1610,16 +1697,37 @@ static const struct dsa_switch_ops mt7530_switch_ops = {\r\n \t.port_vlan_prepare\t= mt7530_port_vlan_prepare,\r\n \t.port_vlan_add\t\t= mt7530_port_vlan_add,\r\n \t.port_vlan_del\t\t= mt7530_port_vlan_del,\r\n-\t.phylink_validate\t= mt7530_phylink_validate,\r\n+\t.phylink_validate\t= mt753x_phylink_validate,\r\n \t.phylink_mac_link_state = mt7530_phylink_mac_link_state,\r\n-\t.phylink_mac_config\t= mt7530_phylink_mac_config,\r\n+\t.phylink_mac_config\t= mt753x_phylink_mac_config,\r\n \t.phylink_mac_link_down\t= mt7530_phylink_mac_link_down,\r\n \t.phylink_mac_link_up\t= mt7530_phylink_mac_link_up,\r\n };\r\n \r\n+static const struct mt753x_info mt753x_table[] = {\r\n+\t[ID_MT7621] = {\r\n+\t\t.id = ID_MT7621,\r\n+\t\t.setup = mt7530_setup,\r\n+\t\t.phy_read = mt7530_phy_read,\r\n+\t\t.phy_write = mt7530_phy_write,\r\n+\t\t.phy_supported = mt7530_phy_supported,\r\n+\t\t.pad_setup = mt7530_pad_setup,\r\n+\t\t.mac_setup = mt7530_mac_setup,\r\n+\t},\r\n+\t[ID_MT7530] = {\r\n+\t\t.id = ID_MT7530,\r\n+\t\t.setup = mt7530_setup,\r\n+\t\t.phy_read = mt7530_phy_read,\r\n+\t\t.phy_write = mt7530_phy_write,\r\n+\t\t.phy_supported = mt7530_phy_supported,\r\n+\t\t.pad_setup = mt7530_pad_setup,\r\n+\t\t.mac_setup = mt7530_mac_setup,\r\n+\t},\r\n+};\r\n+\r\n static const struct of_device_id mt7530_of_match[] = {\r\n-\t{ .compatible = \"mediatek,mt7621\", .data = (void *)ID_MT7621, },\r\n-\t{ .compatible = \"mediatek,mt7530\", .data = (void *)ID_MT7530, },\r\n+\t{ .compatible = \"mediatek,mt7621\", .data = &mt753x_table[ID_MT7621], },\r\n+\t{ .compatible = \"mediatek,mt7530\", .data = &mt753x_table[ID_MT7530], },\r\n \t{ /* sentinel */ },\r\n };\r\n MODULE_DEVICE_TABLE(of, mt7530_of_match);\r\n@@ -1660,8 +1768,19 @@ mt7530_probe(struct mdio_device *mdiodev)\r\n \t/* Get the hardware identifier from the devicetree node.\r\n \t * We will need it for some of the clock and regulator setup.\r\n \t */\r\n-\tpriv->id = (unsigned int)(unsigned long)\r\n-\t\tof_device_get_match_data(&mdiodev->dev);\r\n+\tpriv->info = of_device_get_match_data(&mdiodev->dev);\r\n+\tif (!priv->info)\r\n+\t\treturn -EINVAL;\r\n+\r\n+\t/* Sanity check if these required device operstaions are filled\r\n+\t * properly.\r\n+\t */\r\n+\tif (!priv->info->setup || !priv->info->phy_read ||\r\n+\t    !priv->info->phy_write || !priv->info->phy_supported ||\r\n+\t    !priv->info->pad_setup || !priv->info->mac_setup)\r\n+\t\treturn -EINVAL;\r\n+\r\n+\tpriv->id = priv->info->id;\r\n \r\n \tif (priv->id == ID_MT7530) {\r\n \t\tpriv->core_pwr = devm_regulator_get(&mdiodev->dev, \"core\");\r\ndiff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h\r\nindex ccb9da8cad0d..aac86e4fc148 100644\r\n--- a/drivers/net/dsa/mt7530.h\r\n+++ b/drivers/net/dsa/mt7530.h\r\n@@ -11,7 +11,7 @@\r\n #define MT7530_NUM_FDB_RECORDS\t\t2048\r\n #define MT7530_ALL_MEMBERS\t\t0xff\r\n \r\n-enum {\r\n+enum mt753x_id {\r\n \tID_MT7530 = 0,\r\n \tID_MT7621 = 1,\r\n };\r\n@@ -428,6 +428,32 @@ static const char *p5_intf_modes(unsigned int p5_interface)\r\n \t}\r\n }\r\n \r\n+/* struct mt753x_info -\tThis is the main data structure for holding the specific\r\n+ *\t\t\tpart for each supported device\r\n+ * @setup:\t\tHolding the handler to a device initialization\r\n+ * @phy_read:\t\tHolding the way reading PHY port\r\n+ * @phy_write:\t\tHolding the way writing PHY port\r\n+ * @phy_supported:\tCheck if the PHY type is being supported on a certain\r\n+ *\t\t\tport\r\n+ * @pad_setup:\t\tHolding the way setting up the bus pad for a certain MAC\r\n+ *\t\t\tport\r\n+ * @mac_setup:\t\tHolding the way setting up the PHY attribute for a\r\n+ *\t\t\tcertain MAC port\r\n+ */\r\n+struct mt753x_info {\r\n+\tenum mt753x_id id;\r\n+\r\n+\tint (*setup)(struct dsa_switch *ds);\r\n+\tint (*phy_read)(struct dsa_switch *ds, int port, int regnum);\r\n+\tint (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val);\r\n+\tbool (*phy_supported)(struct dsa_switch *ds, int port,\r\n+\t\t\t      const struct phylink_link_state *state);\r\n+\tint (*pad_setup)(struct dsa_switch *ds,\r\n+\t\t\t const struct phylink_link_state *state);\r\n+\tint (*mac_setup)(struct dsa_switch *ds, int port, unsigned int mode,\r\n+\t\t\t const struct phylink_link_state *state);\r\n+};\r\n+\r\n /* struct mt7530_priv -\tThis is the main data structure for holding the state\r\n  *\t\t\tof the driver\r\n  * @dev:\t\tThe device pointer\r\n@@ -455,6 +481,7 @@ struct mt7530_priv {\r\n \tstruct regulator\t*core_pwr;\r\n \tstruct regulator\t*io_pwr;\r\n \tstruct gpio_desc\t*reset;\r\n+\tconst struct mt753x_info *info;\r\n \tunsigned int\t\tid;\r\n \tbool\t\t\tmcm;\r\n \tphy_interface_t\t\tp6_interface;\r\n",
    "prefixes": [
        "net-next",
        "2/6"
    ]
}