Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1197471/?format=api
{ "id": 1197471, "url": "http://patchwork.ozlabs.org/api/patches/1197471/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20191119141211.25716-6-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20191119141211.25716-6-clg@kaod.org>", "list_archive_url": null, "date": "2019-11-19T14:11:59", "name": "[05/17] aspeed/i2c: Add trace events", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0395168e5adfe1bdc604e356df3d1857e535b3ed", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20191119141211.25716-6-clg@kaod.org/mbox/", "series": [ { "id": 143789, "url": "http://patchwork.ozlabs.org/api/series/143789/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=143789", "date": "2019-11-19T14:11:54", "name": "aspeed: extensions and fixes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/143789/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1197471/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1197471/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=nongnu.org (client-ip=209.51.188.17;\n\thelo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=kaod.org" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 47HSZc2yB2z9sRK\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 20 Nov 2019 01:17:28 +1100 (AEDT)", "from localhost ([::1]:45982 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1iX4Jo-0001dB-Pd\n\tfor incoming@patchwork.ozlabs.org; Tue, 19 Nov 2019 09:17:24 -0500", "from eggs.gnu.org ([2001:470:142:3::10]:41916)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <clg@kaod.org>) id 1iX4Fg-00062I-0B\n\tfor qemu-devel@nongnu.org; Tue, 19 Nov 2019 09:13:09 -0500", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <clg@kaod.org>) id 1iX4Fe-0005Ia-8l\n\tfor qemu-devel@nongnu.org; Tue, 19 Nov 2019 09:13:07 -0500", "from 10.mo3.mail-out.ovh.net ([87.98.165.232]:60009)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <clg@kaod.org>) id 1iX4Fe-0005Hj-2V\n\tfor qemu-devel@nongnu.org; Tue, 19 Nov 2019 09:13:06 -0500", "from player795.ha.ovh.net (unknown [10.108.54.59])\n\tby mo3.mail-out.ovh.net (Postfix) with ESMTP id 3581F22CCA3\n\tfor <qemu-devel@nongnu.org>; Tue, 19 Nov 2019 15:13:03 +0100 (CET)", "from kaod.org (deibp9eh1--blueice1n4.emea.ibm.com [195.212.29.166])\n\t(Authenticated sender: clg@kaod.org)\n\tby player795.ha.ovh.net (Postfix) with ESMTPSA id 9C17CC18A976;\n\tTue, 19 Nov 2019 14:12:54 +0000 (UTC)" ], "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "Peter Maydell <peter.maydell@linaro.org>", "Subject": "[PATCH 05/17] aspeed/i2c: Add trace events", "Date": "Tue, 19 Nov 2019 15:11:59 +0100", "Message-Id": "<20191119141211.25716-6-clg@kaod.org>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20191119141211.25716-1-clg@kaod.org>", "References": "<20191119141211.25716-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "X-Ovh-Tracer-Id": "17901527044910648081", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "gggruggvucftvghtrhhoucdtuddrgedufedrudegkedgiedvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdqfffguegfifdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucfkpheptddrtddrtddrtddpudelhedrvdduvddrvdelrdduieeinecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejleehrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepqhgvmhhuqdguvghvvghlsehnohhnghhnuhdrohhrghenucevlhhushhtvghrufhiiigvpedv", "Content-Transfer-Encoding": "quoted-printable", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "87.98.165.232", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>, Andrew Jeffery\n\t<andrew@aj.id.au>, qemu-devel@nongnu.org, qemu-arm@nongnu.org,\n\t=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@redhat.com>,\n\tJoel Stanley <joel@jms.id.au>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Signed-off-by: Cédric Le Goater <clg@kaod.org>\nReviewed-by: Joel Stanley <joel@jms.id.au>\nTested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>\nReviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n hw/i2c/aspeed_i2c.c | 93 ++++++++++++++++++++++++++++++++++++++-------\n hw/i2c/trace-events | 9 +++++\n 2 files changed, 89 insertions(+), 13 deletions(-)", "diff": "diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c\nindex 030d9c56be65..2da04a4bff30 100644\n--- a/hw/i2c/aspeed_i2c.c\n+++ b/hw/i2c/aspeed_i2c.c\n@@ -28,6 +28,7 @@\n #include \"hw/i2c/aspeed_i2c.h\"\n #include \"hw/irq.h\"\n #include \"hw/qdev-properties.h\"\n+#include \"trace.h\"\n \n /* I2C Global Register */\n \n@@ -158,6 +159,13 @@ static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus)\n {\n AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);\n \n+ trace_aspeed_i2c_bus_raise_interrupt(bus->intr_status,\n+ bus->intr_status & I2CD_INTR_TX_NAK ? \"nak|\" : \"\",\n+ bus->intr_status & I2CD_INTR_TX_ACK ? \"ack|\" : \"\",\n+ bus->intr_status & I2CD_INTR_RX_DONE ? \"done|\" : \"\",\n+ bus->intr_status & I2CD_INTR_NORMAL_STOP ? \"normal|\" : \"\",\n+ bus->intr_status & I2CD_INTR_ABNORMAL ? \"abnormal\" : \"\");\n+\n bus->intr_status &= bus->intr_ctrl;\n if (bus->intr_status) {\n bus->controller->intr_status |= 1 << bus->id;\n@@ -170,41 +178,57 @@ static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,\n {\n AspeedI2CBus *bus = opaque;\n AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);\n+ uint64_t value = -1;\n \n switch (offset) {\n case I2CD_FUN_CTRL_REG:\n- return bus->ctrl;\n+ value = bus->ctrl;\n+ break;\n case I2CD_AC_TIMING_REG1:\n- return bus->timing[0];\n+ value = bus->timing[0];\n+ break;\n case I2CD_AC_TIMING_REG2:\n- return bus->timing[1];\n+ value = bus->timing[1];\n+ break;\n case I2CD_INTR_CTRL_REG:\n- return bus->intr_ctrl;\n+ value = bus->intr_ctrl;\n+ break;\n case I2CD_INTR_STS_REG:\n- return bus->intr_status;\n+ value = bus->intr_status;\n+ break;\n case I2CD_POOL_CTRL_REG:\n- return bus->pool_ctrl;\n+ value = bus->pool_ctrl;\n+ break;\n case I2CD_BYTE_BUF_REG:\n- return bus->buf;\n+ value = bus->buf;\n+ break;\n case I2CD_CMD_REG:\n- return bus->cmd | (i2c_bus_busy(bus->bus) << 16);\n+ value = bus->cmd | (i2c_bus_busy(bus->bus) << 16);\n+ break;\n case I2CD_DMA_ADDR:\n if (!aic->has_dma) {\n qemu_log_mask(LOG_GUEST_ERROR, \"%s: No DMA support\\n\", __func__);\n- return -1;\n+ break;\n }\n- return bus->dma_addr;\n+ value = bus->dma_addr;\n+ break;\n case I2CD_DMA_LEN:\n if (!aic->has_dma) {\n qemu_log_mask(LOG_GUEST_ERROR, \"%s: No DMA support\\n\", __func__);\n- return -1;\n+ break;\n }\n- return bus->dma_len;\n+ value = bus->dma_len;\n+ break;\n+\n default:\n qemu_log_mask(LOG_GUEST_ERROR,\n \"%s: Bad offset 0x%\" HWADDR_PRIx \"\\n\", __func__, offset);\n- return -1;\n+ value = -1;\n+ break;\n }\n+\n+ trace_aspeed_i2c_bus_read(bus->id, offset, size, value);\n+ return value;\n }\n \n static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state)\n@@ -246,6 +270,9 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start)\n for (i = pool_start; i < I2CD_POOL_TX_COUNT(bus->pool_ctrl); i++) {\n uint8_t *pool_base = aic->bus_pool_base(bus);\n \n+ trace_aspeed_i2c_bus_send(\"BUF\", i + 1,\n+ I2CD_POOL_TX_COUNT(bus->pool_ctrl),\n+ pool_base[i]);\n ret = i2c_send(bus->bus, pool_base[i]);\n if (ret) {\n break;\n@@ -256,6 +283,7 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start)\n while (bus->dma_len) {\n uint8_t data;\n aspeed_i2c_dma_read(bus, &data);\n+ trace_aspeed_i2c_bus_send(\"DMA\", bus->dma_len, bus->dma_len, data);\n ret = i2c_send(bus->bus, data);\n if (ret) {\n break;\n@@ -263,6 +291,7 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start)\n }\n bus->cmd &= ~I2CD_TX_DMA_ENABLE;\n } else {\n+ trace_aspeed_i2c_bus_send(\"BYTE\", pool_start, 1, bus->buf);\n ret = i2c_send(bus->bus, bus->buf);\n }\n \n@@ -281,6 +310,9 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus)\n \n for (i = 0; i < I2CD_POOL_RX_SIZE(bus->pool_ctrl); i++) {\n pool_base[i] = i2c_recv(bus->bus);\n+ trace_aspeed_i2c_bus_recv(\"BUF\", i + 1,\n+ I2CD_POOL_RX_SIZE(bus->pool_ctrl),\n+ pool_base[i]);\n }\n \n /* Update RX count */\n@@ -294,6 +326,7 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus)\n MemTxResult result;\n \n data = i2c_recv(bus->bus);\n+ trace_aspeed_i2c_bus_recv(\"DMA\", bus->dma_len, bus->dma_len, data);\n result = address_space_write(&s->dram_as, bus->dma_addr,\n MEMTXATTRS_UNSPECIFIED, &data, 1);\n if (result != MEMTX_OK) {\n@@ -307,6 +340,7 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus)\n bus->cmd &= ~I2CD_RX_DMA_ENABLE;\n } else {\n data = i2c_recv(bus->bus);\n+ trace_aspeed_i2c_bus_recv(\"BYTE\", 1, 1, bus->buf);\n bus->buf = (data & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;\n }\n }\n@@ -364,6 +398,33 @@ static bool aspeed_i2c_check_sram(AspeedI2CBus *bus)\n return true;\n }\n \n+static void aspeed_i2c_bus_cmd_dump(AspeedI2CBus *bus)\n+{\n+ g_autofree char *cmd_flags;\n+ uint32_t count;\n+\n+ if (bus->cmd & (I2CD_RX_BUFF_ENABLE | I2CD_RX_BUFF_ENABLE)) {\n+ count = I2CD_POOL_TX_COUNT(bus->pool_ctrl);\n+ } else if (bus->cmd & (I2CD_RX_DMA_ENABLE | I2CD_RX_DMA_ENABLE)) {\n+ count = bus->dma_len;\n+ } else { /* BYTE mode */\n+ count = 1;\n+ }\n+\n+ cmd_flags = g_strdup_printf(\"%s%s%s%s%s%s%s%s%s\",\n+ bus->cmd & I2CD_M_START_CMD ? \"start|\" : \"\",\n+ bus->cmd & I2CD_RX_DMA_ENABLE ? \"rxdma|\" : \"\",\n+ bus->cmd & I2CD_TX_DMA_ENABLE ? \"txdma|\" : \"\",\n+ bus->cmd & I2CD_RX_BUFF_ENABLE ? \"rxbuf|\" : \"\",\n+ bus->cmd & I2CD_TX_BUFF_ENABLE ? \"txbuf|\" : \"\",\n+ bus->cmd & I2CD_M_TX_CMD ? \"tx|\" : \"\",\n+ bus->cmd & I2CD_M_RX_CMD ? \"rx|\" : \"\",\n+ bus->cmd & I2CD_M_S_RX_CMD_LAST ? \"last|\" : \"\",\n+ bus->cmd & I2CD_M_STOP_CMD ? \"stop\" : \"\");\n+\n+ trace_aspeed_i2c_bus_cmd(bus->cmd, cmd_flags, count, bus->intr_status);\n+}\n+\n /*\n * The state machine needs some refinement. It is only used to track\n * invalid STOP commands for the moment.\n@@ -379,6 +440,10 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)\n return;\n }\n \n+ if (trace_event_get_state_backends(TRACE_ASPEED_I2C_BUS_CMD)) {\n+ aspeed_i2c_bus_cmd_dump(bus);\n+ }\n+\n if (bus->cmd & I2CD_M_START_CMD) {\n uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?\n I2CD_MSTARTR : I2CD_MSTART;\n@@ -465,6 +530,8 @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,\n AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);\n bool handle_rx;\n \n+ trace_aspeed_i2c_bus_write(bus->id, offset, size, value);\n+\n switch (offset) {\n case I2CD_FUN_CTRL_REG:\n if (value & I2CD_SLAVE_EN) {\ndiff --git a/hw/i2c/trace-events b/hw/i2c/trace-events\nindex e1c810d5bd08..08db8fa68924 100644\n--- a/hw/i2c/trace-events\n+++ b/hw/i2c/trace-events\n@@ -5,3 +5,12 @@\n i2c_event(const char *event, uint8_t address) \"%s(addr:0x%02x)\"\n i2c_send(uint8_t address, uint8_t data) \"send(addr:0x%02x) data:0x%02x\"\n i2c_recv(uint8_t address, uint8_t data) \"recv(addr:0x%02x) data:0x%02x\"\n+\n+# aspeed_i2c.c\n+\n+aspeed_i2c_bus_cmd(uint32_t cmd, const char *cmd_flags, uint32_t count, uint32_t intr_status) \"handling cmd=0x%x %s count=%d intr=0x%x\"\n+aspeed_i2c_bus_raise_interrupt(uint32_t intr_status, const char *str1, const char *str2, const char *str3, const char *str4, const char *str5) \"handled intr=0x%x %s%s%s%s%s\"\n+aspeed_i2c_bus_read(uint32_t busid, uint64_t offset, unsigned size, uint64_t value) \"bus[%d]: To 0x%\" PRIx64 \" of size %u: 0x%\" PRIx64\n+aspeed_i2c_bus_write(uint32_t busid, uint64_t offset, unsigned size, uint64_t value) \"bus[%d]: To 0x%\" PRIx64 \" of size %u: 0x%\" PRIx64\n+aspeed_i2c_bus_send(const char *mode, int i, int count, uint8_t byte) \"%s send %d/%d 0x%02x\"\n+aspeed_i2c_bus_recv(const char *mode, int i, int count, uint8_t byte) \"%s recv %d/%d 0x%02x\"\n", "prefixes": [ "05/17" ] }