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GET /api/patches/1197467/?format=api
{ "id": 1197467, "url": "http://patchwork.ozlabs.org/api/patches/1197467/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20191119141211.25716-4-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20191119141211.25716-4-clg@kaod.org>", "list_archive_url": null, "date": "2019-11-19T14:11:57", "name": "[03/17] aspeed: Add a DRAM memory region at the SoC level", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "04ade9ff454d303dc9234b486c4925a4a13df0a3", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20191119141211.25716-4-clg@kaod.org/mbox/", "series": [ { "id": 143789, "url": "http://patchwork.ozlabs.org/api/series/143789/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=143789", "date": "2019-11-19T14:11:54", "name": "aspeed: extensions and fixes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/143789/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1197467/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1197467/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=nongnu.org (client-ip=209.51.188.17;\n\thelo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=kaod.org" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 47HSVW05vTz9sPf\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 20 Nov 2019 01:13:54 +1100 (AEDT)", "from localhost ([::1]:45924 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1iX4GN-00061G-Pk\n\tfor incoming@patchwork.ozlabs.org; Tue, 19 Nov 2019 09:13:51 -0500", "from eggs.gnu.org ([2001:470:142:3::10]:41842)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <clg@kaod.org>) id 1iX4FO-0005a1-Cr\n\tfor qemu-devel@nongnu.org; Tue, 19 Nov 2019 09:12:51 -0500", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <clg@kaod.org>) id 1iX4FN-0005BF-3z\n\tfor qemu-devel@nongnu.org; Tue, 19 Nov 2019 09:12:50 -0500", "from 9.mo5.mail-out.ovh.net ([178.32.96.204]:49825)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <clg@kaod.org>) id 1iX4FM-0005AW-UY\n\tfor qemu-devel@nongnu.org; Tue, 19 Nov 2019 09:12:49 -0500", "from player795.ha.ovh.net (unknown [10.109.159.62])\n\tby mo5.mail-out.ovh.net (Postfix) with ESMTP id 1282D25ABE0\n\tfor <qemu-devel@nongnu.org>; Tue, 19 Nov 2019 15:12:46 +0100 (CET)", "from kaod.org (deibp9eh1--blueice1n4.emea.ibm.com [195.212.29.166])\n\t(Authenticated sender: clg@kaod.org)\n\tby player795.ha.ovh.net (Postfix) with ESMTPSA id F1282C18A87B;\n\tTue, 19 Nov 2019 14:12:37 +0000 (UTC)" ], "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "Peter Maydell <peter.maydell@linaro.org>", "Subject": "[PATCH 03/17] aspeed: Add a DRAM memory region at the SoC level", "Date": "Tue, 19 Nov 2019 15:11:57 +0100", "Message-Id": "<20191119141211.25716-4-clg@kaod.org>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20191119141211.25716-1-clg@kaod.org>", "References": "<20191119141211.25716-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "X-Ovh-Tracer-Id": "17896741971556928273", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "gggruggvucftvghtrhhoucdtuddrgedufedrudegkedgiedvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdqfffguegfifdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucfkpheptddrtddrtddrtddpudelhedrvdduvddrvdelrdduieeinecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejleehrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepqhgvmhhuqdguvghvvghlsehnohhnghhnuhdrohhrghenucevlhhushhtvghrufhiiigvpedu", "Content-Transfer-Encoding": "quoted-printable", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "178.32.96.204", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>, Andrew Jeffery\n\t<andrew@aj.id.au>, qemu-devel@nongnu.org, qemu-arm@nongnu.org,\n\t=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>,\n\tJoel Stanley <joel@jms.id.au>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Currently, we link the DRAM memory region to the FMC model (for DMAs)\nthrough a property alias at the SoC level. The I2C model will need a\nsimilar region for DMA support, add a DRAM region property at the SoC\nlevel for both model to use.\n\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\nReviewed-by: Joel Stanley <joel@jms.id.au>\nTested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n include/hw/arm/aspeed_soc.h | 1 +\n hw/arm/aspeed_ast2600.c | 7 +++++--\n hw/arm/aspeed_soc.c | 9 +++++++--\n 3 files changed, 13 insertions(+), 4 deletions(-)", "diff": "diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h\nindex 495c08be1b84..e84380984f7b 100644\n--- a/include/hw/arm/aspeed_soc.h\n+++ b/include/hw/arm/aspeed_soc.h\n@@ -40,6 +40,7 @@ typedef struct AspeedSoCState {\n ARMCPU cpu[ASPEED_CPUS_NUM];\n uint32_t num_cpus;\n A15MPPrivState a7mpcore;\n+ MemoryRegion *dram_mr;\n MemoryRegion sram;\n AspeedVICState vic;\n AspeedRtcState rtc;\ndiff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c\nindex 931887ac681f..a403c2aae067 100644\n--- a/hw/arm/aspeed_ast2600.c\n+++ b/hw/arm/aspeed_ast2600.c\n@@ -158,8 +158,6 @@ static void aspeed_soc_ast2600_init(Object *obj)\n typename);\n object_property_add_alias(obj, \"num-cs\", OBJECT(&s->fmc), \"num-cs\",\n &error_abort);\n- object_property_add_alias(obj, \"dram\", OBJECT(&s->fmc), \"dram\",\n- &error_abort);\n \n for (i = 0; i < sc->spis_num; i++) {\n snprintf(typename, sizeof(typename), \"aspeed.spi%d-%s\", i + 1, socname);\n@@ -362,6 +360,11 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)\n }\n \n /* FMC, The number of CS is set at the board level */\n+ object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), \"dram\", &err);\n+ if (err) {\n+ error_propagate(errp, err);\n+ return;\n+ }\n object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],\n \"sdram-base\", &err);\n if (err) {\ndiff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c\nindex f4fe243458fd..dd1ee0e3336d 100644\n--- a/hw/arm/aspeed_soc.c\n+++ b/hw/arm/aspeed_soc.c\n@@ -175,8 +175,6 @@ static void aspeed_soc_init(Object *obj)\n typename);\n object_property_add_alias(obj, \"num-cs\", OBJECT(&s->fmc), \"num-cs\",\n &error_abort);\n- object_property_add_alias(obj, \"dram\", OBJECT(&s->fmc), \"dram\",\n- &error_abort);\n \n for (i = 0; i < sc->spis_num; i++) {\n snprintf(typename, sizeof(typename), \"aspeed.spi%d-%s\", i + 1, socname);\n@@ -323,6 +321,11 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)\n aspeed_soc_get_irq(s, ASPEED_I2C));\n \n /* FMC, The number of CS is set at the board level */\n+ object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), \"dram\", &err);\n+ if (err) {\n+ error_propagate(errp, err);\n+ return;\n+ }\n object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],\n \"sdram-base\", &err);\n if (err) {\n@@ -429,6 +432,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)\n }\n static Property aspeed_soc_properties[] = {\n DEFINE_PROP_UINT32(\"num-cpus\", AspeedSoCState, num_cpus, 0),\n+ DEFINE_PROP_LINK(\"dram\", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,\n+ MemoryRegion *),\n DEFINE_PROP_END_OF_LIST(),\n };\n \n", "prefixes": [ "03/17" ] }