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GET /api/patches/1197466/?format=api
{ "id": 1197466, "url": "http://patchwork.ozlabs.org/api/patches/1197466/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20191119141211.25716-3-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20191119141211.25716-3-clg@kaod.org>", "list_archive_url": null, "date": "2019-11-19T14:11:56", "name": "[02/17] aspeed/i2c: Check SRAM enablement on AST2500", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "acfb700f89c31e9d605a5d116346e12cd1a0aa08", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20191119141211.25716-3-clg@kaod.org/mbox/", "series": [ { "id": 143789, "url": "http://patchwork.ozlabs.org/api/series/143789/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=143789", "date": "2019-11-19T14:11:54", "name": "aspeed: extensions and fixes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/143789/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1197466/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1197466/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=nongnu.org (client-ip=209.51.188.17;\n\thelo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=kaod.org" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 47HSVJ1vHTz9sPf\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 20 Nov 2019 01:13:44 +1100 (AEDT)", "from localhost ([::1]:45922 helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1iX4GD-0005kQ-HA\n\tfor incoming@patchwork.ozlabs.org; Tue, 19 Nov 2019 09:13:41 -0500", "from eggs.gnu.org ([2001:470:142:3::10]:41804)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <clg@kaod.org>) id 1iX4FH-0005NC-5F\n\tfor qemu-devel@nongnu.org; Tue, 19 Nov 2019 09:12:44 -0500", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <clg@kaod.org>) id 1iX4FD-00057U-O1\n\tfor qemu-devel@nongnu.org; Tue, 19 Nov 2019 09:12:43 -0500", "from 4.mo1.mail-out.ovh.net ([46.105.76.26]:52013)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <clg@kaod.org>) id 1iX4FD-00056Y-HY\n\tfor qemu-devel@nongnu.org; Tue, 19 Nov 2019 09:12:39 -0500", "from player795.ha.ovh.net (unknown [10.109.146.131])\n\tby mo1.mail-out.ovh.net (Postfix) with ESMTP id DB7AA19BBDB\n\tfor <qemu-devel@nongnu.org>; Tue, 19 Nov 2019 15:12:37 +0100 (CET)", "from kaod.org (deibp9eh1--blueice1n4.emea.ibm.com [195.212.29.166])\n\t(Authenticated sender: clg@kaod.org)\n\tby player795.ha.ovh.net (Postfix) with ESMTPSA id BE331C18A7D0;\n\tTue, 19 Nov 2019 14:12:28 +0000 (UTC)" ], "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "Peter Maydell <peter.maydell@linaro.org>", "Subject": "[PATCH 02/17] aspeed/i2c: Check SRAM enablement on AST2500", "Date": "Tue, 19 Nov 2019 15:11:56 +0100", "Message-Id": "<20191119141211.25716-3-clg@kaod.org>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20191119141211.25716-1-clg@kaod.org>", "References": "<20191119141211.25716-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "X-Ovh-Tracer-Id": "17894208698231851793", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "gggruggvucftvghtrhhoucdtuddrgedufedrudegkedgiedvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdqfffguegfifdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucfkpheptddrtddrtddrtddpudelhedrvdduvddrvdelrdduieeinecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejleehrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepqhgvmhhuqdguvghvvghlsehnohhnghhnuhdrohhrghenucevlhhushhtvghrufhiiigvpedt", "Content-Transfer-Encoding": "quoted-printable", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "46.105.76.26", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>, Andrew Jeffery\n\t<andrew@aj.id.au>, qemu-devel@nongnu.org, qemu-arm@nongnu.org,\n\t=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>,\n\tJoel Stanley <joel@jms.id.au>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "The SRAM must be enabled before using the Buffer Pool mode or the DMA\nmode. This is not required on other SoCs.\n\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\nReviewed-by: Joel Stanley <joel@jms.id.au>\nTested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n include/hw/i2c/aspeed_i2c.h | 3 +++\n hw/i2c/aspeed_i2c.c | 37 +++++++++++++++++++++++++++++++++++++\n 2 files changed, 40 insertions(+)", "diff": "diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h\nindex 5313d07aa72f..7a555072dfbf 100644\n--- a/include/hw/i2c/aspeed_i2c.h\n+++ b/include/hw/i2c/aspeed_i2c.h\n@@ -61,6 +61,7 @@ typedef struct AspeedI2CState {\n qemu_irq irq;\n \n uint32_t intr_status;\n+ uint32_t ctrl_global;\n MemoryRegion pool_iomem;\n uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE];\n \n@@ -83,6 +84,8 @@ typedef struct AspeedI2CClass {\n uint64_t pool_size;\n hwaddr pool_base;\n uint8_t *(*bus_pool_base)(AspeedI2CBus *);\n+ bool check_sram;\n+\n } AspeedI2CClass;\n \n I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr);\ndiff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c\nindex e21f45d96868..c7929aa2850f 100644\n--- a/hw/i2c/aspeed_i2c.c\n+++ b/hw/i2c/aspeed_i2c.c\n@@ -31,6 +31,8 @@\n #define I2C_CTRL_STATUS 0x00 /* Device Interrupt Status */\n #define I2C_CTRL_ASSIGN 0x08 /* Device Interrupt Target\n Assignment */\n+#define I2C_CTRL_GLOBAL 0x0C /* Global Control Register */\n+#define I2C_CTRL_SRAM_EN BIT(0)\n \n /* I2C Device (Bus) Register */\n \n@@ -271,6 +273,29 @@ static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus)\n }\n }\n \n+static bool aspeed_i2c_check_sram(AspeedI2CBus *bus)\n+{\n+ AspeedI2CState *s = bus->controller;\n+ AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s);\n+\n+ if (!aic->check_sram) {\n+ return true;\n+ }\n+\n+ /*\n+ * AST2500: SRAM must be enabled before using the Buffer Pool or\n+ * DMA mode.\n+ */\n+ if (!(s->ctrl_global & I2C_CTRL_SRAM_EN) &&\n+ (bus->cmd & (I2CD_RX_DMA_ENABLE | I2CD_TX_DMA_ENABLE |\n+ I2CD_RX_BUFF_ENABLE | I2CD_TX_BUFF_ENABLE))) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"%s: SRAM is not enabled\\n\", __func__);\n+ return false;\n+ }\n+\n+ return true;\n+}\n+\n /*\n * The state machine needs some refinement. It is only used to track\n * invalid STOP commands for the moment.\n@@ -282,6 +307,10 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)\n bus->cmd &= ~0xFFFF;\n bus->cmd |= value & 0xFFFF;\n \n+ if (!aspeed_i2c_check_sram(bus)) {\n+ return;\n+ }\n+\n if (bus->cmd & I2CD_M_START_CMD) {\n uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?\n I2CD_MSTARTR : I2CD_MSTART;\n@@ -436,6 +465,8 @@ static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset,\n switch (offset) {\n case I2C_CTRL_STATUS:\n return s->intr_status;\n+ case I2C_CTRL_GLOBAL:\n+ return s->ctrl_global;\n default:\n qemu_log_mask(LOG_GUEST_ERROR, \"%s: Bad offset 0x%\" HWADDR_PRIx \"\\n\",\n __func__, offset);\n@@ -448,7 +479,12 @@ static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset,\n static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset,\n uint64_t value, unsigned size)\n {\n+ AspeedI2CState *s = opaque;\n+\n switch (offset) {\n+ case I2C_CTRL_GLOBAL:\n+ s->ctrl_global = value;\n+ break;\n case I2C_CTRL_STATUS:\n default:\n qemu_log_mask(LOG_GUEST_ERROR, \"%s: Bad offset 0x%\" HWADDR_PRIx \"\\n\",\n@@ -684,6 +720,7 @@ static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data)\n aic->pool_size = 0x100;\n aic->pool_base = 0x200;\n aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base;\n+ aic->check_sram = true;\n }\n \n static const TypeInfo aspeed_2500_i2c_info = {\n", "prefixes": [ "02/17" ] }