Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1197416/?format=api
{ "id": 1197416, "url": "http://patchwork.ozlabs.org/api/patches/1197416/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20191119114523.42490-1-sasha.neftin@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20191119114523.42490-1-sasha.neftin@intel.com>", "list_archive_url": null, "date": "2019-11-19T11:45:23", "name": "[v1,13/15] igc: Remove no need declaration of the igc_assign_vector", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "1e5f127bff947f9737d134572bf08de95237fe9d", "submitter": { "id": 69860, "url": "http://patchwork.ozlabs.org/api/people/69860/?format=api", "name": "Sasha Neftin", "email": "sasha.neftin@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20191119114523.42490-1-sasha.neftin@intel.com/mbox/", "series": [ { "id": 143759, "url": "http://patchwork.ozlabs.org/api/series/143759/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=143759", "date": "2019-11-19T11:43:32", "name": "[v1,01/15] igc: Remove no need declaration of the igc_clean_tx_ring", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/143759/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1197416/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1197416/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=osuosl.org (client-ip=140.211.166.137;\n\thelo=fraxinus.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 47HPDV1Q8jz9s4Y\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 19 Nov 2019 22:46:34 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 8FC4A868AB;\n\tTue, 19 Nov 2019 11:46:32 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id nCNzVBkcBvol; Tue, 19 Nov 2019 11:46:30 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id DF5228651D;\n\tTue, 19 Nov 2019 11:46:30 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 81B671BF83B\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 19 Nov 2019 11:46:29 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 79DD98830F\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 19 Nov 2019 11:46:29 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id ui6kHGWj9QTv for <intel-wired-lan@lists.osuosl.org>;\n\tTue, 19 Nov 2019 11:46:28 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id 954F886963\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 19 Nov 2019 11:46:28 +0000 (UTC)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Nov 2019 03:45:25 -0800", "from ccdlinuxdev08.iil.intel.com ([143.185.161.150])\n\tby fmsmga005.fm.intel.com with ESMTP; 19 Nov 2019 03:45:24 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.68,322,1569308400\"; d=\"scan'208\";a=\"406425707\"", "From": "Sasha Neftin <sasha.neftin@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Tue, 19 Nov 2019 13:45:23 +0200", "Message-Id": "<20191119114523.42490-1-sasha.neftin@intel.com>", "X-Mailer": "git-send-email 2.11.0", "Subject": "[Intel-wired-lan] [PATCH v1 13/15] igc: Remove no need declaration\n\tof the igc_assign_vector", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "We want to avoid forward-declarations of function if possible.\nRearrange the igc_assign_vector function implementation.\n\nSigned-off-by: Sasha Neftin <sasha.neftin@intel.com>\n---\n drivers/net/ethernet/intel/igc/igc_main.c | 123 +++++++++++++++---------------\n 1 file changed, 61 insertions(+), 62 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c\nindex 66a83c9509a5..bce18aee8d8f 100644\n--- a/drivers/net/ethernet/intel/igc/igc_main.c\n+++ b/drivers/net/ethernet/intel/igc/igc_main.c\n@@ -54,7 +54,6 @@ MODULE_DEVICE_TABLE(pci, igc_pci_tbl);\n /* forward declaration */\n static int igc_sw_init(struct igc_adapter *);\n static void igc_write_itr(struct igc_q_vector *q_vector);\n-static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector);\n \n enum latency_range {\n \tlowest_latency = 0,\n@@ -2196,6 +2195,67 @@ static void igc_configure(struct igc_adapter *adapter)\n }\n \n /**\n+ * igc_write_ivar - configure ivar for given MSI-X vector\n+ * @hw: pointer to the HW structure\n+ * @msix_vector: vector number we are allocating to a given ring\n+ * @index: row index of IVAR register to write within IVAR table\n+ * @offset: column offset of in IVAR, should be multiple of 8\n+ *\n+ * The IVAR table consists of 2 columns,\n+ * each containing an cause allocation for an Rx and Tx ring, and a\n+ * variable number of rows depending on the number of queues supported.\n+ */\n+static void igc_write_ivar(struct igc_hw *hw, int msix_vector,\n+\t\t\t int index, int offset)\n+{\n+\tu32 ivar = array_rd32(IGC_IVAR0, index);\n+\n+\t/* clear any bits that are currently set */\n+\tivar &= ~((u32)0xFF << offset);\n+\n+\t/* write vector and valid bit */\n+\tivar |= (msix_vector | IGC_IVAR_VALID) << offset;\n+\n+\tarray_wr32(IGC_IVAR0, index, ivar);\n+}\n+\n+static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector)\n+{\n+\tstruct igc_adapter *adapter = q_vector->adapter;\n+\tstruct igc_hw *hw = &adapter->hw;\n+\tint rx_queue = IGC_N0_QUEUE;\n+\tint tx_queue = IGC_N0_QUEUE;\n+\n+\tif (q_vector->rx.ring)\n+\t\trx_queue = q_vector->rx.ring->reg_idx;\n+\tif (q_vector->tx.ring)\n+\t\ttx_queue = q_vector->tx.ring->reg_idx;\n+\n+\tswitch (hw->mac.type) {\n+\tcase igc_i225:\n+\t\tif (rx_queue > IGC_N0_QUEUE)\n+\t\t\tigc_write_ivar(hw, msix_vector,\n+\t\t\t\t rx_queue >> 1,\n+\t\t\t\t (rx_queue & 0x1) << 4);\n+\t\tif (tx_queue > IGC_N0_QUEUE)\n+\t\t\tigc_write_ivar(hw, msix_vector,\n+\t\t\t\t tx_queue >> 1,\n+\t\t\t\t ((tx_queue & 0x1) << 4) + 8);\n+\t\tq_vector->eims_value = BIT(msix_vector);\n+\t\tbreak;\n+\tdefault:\n+\t\tWARN_ONCE(hw->mac.type != igc_i225, \"Wrong MAC type\\n\");\n+\t\tbreak;\n+\t}\n+\n+\t/* add q_vector eims value to global eims_enable_mask */\n+\tadapter->eims_enable_mask |= q_vector->eims_value;\n+\n+\t/* configure q_vector to set itr on first interrupt */\n+\tq_vector->set_itr = 1;\n+}\n+\n+/**\n * igc_configure_msix - Configure MSI-X hardware\n * @adapter: Pointer to adapter structure\n *\n@@ -2871,67 +2931,6 @@ static irqreturn_t igc_msix_other(int irq, void *data)\n \treturn IRQ_HANDLED;\n }\n \n-/**\n- * igc_write_ivar - configure ivar for given MSI-X vector\n- * @hw: pointer to the HW structure\n- * @msix_vector: vector number we are allocating to a given ring\n- * @index: row index of IVAR register to write within IVAR table\n- * @offset: column offset of in IVAR, should be multiple of 8\n- *\n- * The IVAR table consists of 2 columns,\n- * each containing an cause allocation for an Rx and Tx ring, and a\n- * variable number of rows depending on the number of queues supported.\n- */\n-static void igc_write_ivar(struct igc_hw *hw, int msix_vector,\n-\t\t\t int index, int offset)\n-{\n-\tu32 ivar = array_rd32(IGC_IVAR0, index);\n-\n-\t/* clear any bits that are currently set */\n-\tivar &= ~((u32)0xFF << offset);\n-\n-\t/* write vector and valid bit */\n-\tivar |= (msix_vector | IGC_IVAR_VALID) << offset;\n-\n-\tarray_wr32(IGC_IVAR0, index, ivar);\n-}\n-\n-static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector)\n-{\n-\tstruct igc_adapter *adapter = q_vector->adapter;\n-\tstruct igc_hw *hw = &adapter->hw;\n-\tint rx_queue = IGC_N0_QUEUE;\n-\tint tx_queue = IGC_N0_QUEUE;\n-\n-\tif (q_vector->rx.ring)\n-\t\trx_queue = q_vector->rx.ring->reg_idx;\n-\tif (q_vector->tx.ring)\n-\t\ttx_queue = q_vector->tx.ring->reg_idx;\n-\n-\tswitch (hw->mac.type) {\n-\tcase igc_i225:\n-\t\tif (rx_queue > IGC_N0_QUEUE)\n-\t\t\tigc_write_ivar(hw, msix_vector,\n-\t\t\t\t rx_queue >> 1,\n-\t\t\t\t (rx_queue & 0x1) << 4);\n-\t\tif (tx_queue > IGC_N0_QUEUE)\n-\t\t\tigc_write_ivar(hw, msix_vector,\n-\t\t\t\t tx_queue >> 1,\n-\t\t\t\t ((tx_queue & 0x1) << 4) + 8);\n-\t\tq_vector->eims_value = BIT(msix_vector);\n-\t\tbreak;\n-\tdefault:\n-\t\tWARN_ONCE(hw->mac.type != igc_i225, \"Wrong MAC type\\n\");\n-\t\tbreak;\n-\t}\n-\n-\t/* add q_vector eims value to global eims_enable_mask */\n-\tadapter->eims_enable_mask |= q_vector->eims_value;\n-\n-\t/* configure q_vector to set itr on first interrupt */\n-\tq_vector->set_itr = 1;\n-}\n-\n static irqreturn_t igc_msix_ring(int irq, void *data)\n {\n \tstruct igc_q_vector *q_vector = data;\n", "prefixes": [ "v1", "13/15" ] }