Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1191985/?format=api
{ "id": 1191985, "url": "http://patchwork.ozlabs.org/api/patches/1191985/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-40-linux@rasmusvillemoes.dk/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20191108130123.6839-40-linux@rasmusvillemoes.dk>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20191108130123.6839-40-linux@rasmusvillemoes.dk/", "date": "2019-11-08T13:01:15", "name": "[v4,39/47] soc: fsl: qe: avoid IS_ERR_VALUE in ucc_slow.c", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "d43a2aad4a9904e17ad807581b6367fddf7ac796", "submitter": { "id": 27394, "url": "http://patchwork.ozlabs.org/api/people/27394/?format=api", "name": "Rasmus Villemoes", "email": "linux@rasmusvillemoes.dk" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-40-linux@rasmusvillemoes.dk/mbox/", "series": [ { "id": 141654, "url": "http://patchwork.ozlabs.org/api/series/141654/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=141654", "date": "2019-11-08T13:00:38", "name": "QUICC Engine support on ARM and ARM64", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/141654/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1191985/comments/", "check": "success", "checks": "http://patchwork.ozlabs.org/api/patches/1191985/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 478kfK3J41z9sNT\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 02:27:21 +1100 (AEDT)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 478kfK0DYRzF7VF\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 02:27:21 +1100 (AEDT)", "from mail-lj1-x241.google.com (mail-lj1-x241.google.com\n\t[IPv6:2a00:1450:4864:20::241])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (2048 bits)\n\tserver-digest SHA256) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 478gR04h2kzF6tP\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tSat, 9 Nov 2019 00:02:20 +1100 (AEDT)", "by mail-lj1-x241.google.com with SMTP id l20so6127856lje.4\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 08 Nov 2019 05:02:20 -0800 (PST)", "from prevas-ravi.prevas.se ([81.216.59.226])\n\tby smtp.gmail.com with ESMTPSA id\n\td28sm2454725lfn.33.2019.11.08.05.02.16\n\t(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n\tFri, 08 Nov 2019 05:02:16 -0800 (PST)" ], "Authentication-Results": [ "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"H5JuEuP5\"; dkim-atps=neutral", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=rasmusvillemoes.dk (client-ip=2a00:1450:4864:20::241;\n\thelo=mail-lj1-x241.google.com; envelope-from=linux@rasmusvillemoes.dk;\n\treceiver=<UNKNOWN>)", "lists.ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "lists.ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"H5JuEuP5\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=rasmusvillemoes.dk; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=lTNGYmdFYnmbZW7BpDJGzJwkDqsYkg29EXzmXFmW/h8=;\n\tb=H5JuEuP5tLO+DynLcAFFP0N09+DzlW9tVKmrQ/dVJFts+vd+dHMtpA2iNiybLkrIue\n\tteBl/LORkM1qYI0PXUTGYUWBT+8bbWRDFfPbAjjljgCudgvFBX7mGvhQWjv0Q8EWQIuE\n\tPeMjAXLmxtZUTyKdS4F/EuhaR1nxaUmqhlnAI=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=lTNGYmdFYnmbZW7BpDJGzJwkDqsYkg29EXzmXFmW/h8=;\n\tb=O2CZ9A8zkroskTl3L6r2NQ47X3JYbcahSOrspYYR/phJ6zN8Wn/0b4XQx44b1ZmS6J\n\tPWKemwIFrsMtojpjLnk/2xNKXculDlNhS1o1czJsvrqn2aC3iioYETIbAUFzO4rXfvoC\n\tQVHSM6ROdjBYFcZ+86/FycQU06WhxKJMYuuCZhR0TJqsl3H4RvX/u5omrvhWDMk7Mt/b\n\tTpqHX8262YEPFPCgQ/Lequa1IOn8yga0N+JZpdqTInssh9zsB4YSmvD5XHFqwPpcF1dX\n\tXpNOArQAN8WtPEKWV84xW/o5/p40ucjVuDu8GdjkHmupRlQgYlZX4owAD3RPdWfZivEm\n\tz+dg==", "X-Gm-Message-State": "APjAAAWuSBWRtxg8yQ1ro1eEVyPsyIpmQJHvdzDXweTRVqQ5ptI/FBZz\n\tSvBbvvCHiucFFW2lpST3tx2p7g==", "X-Google-Smtp-Source": "APXvYqzP460JuRM8sVvJMljDGfhC7vukmbMbViHsvnghQLYn1lNCibVb6RIJWYFwFeSahEYRQku9KA==", "X-Received": "by 2002:a2e:894b:: with SMTP id\n\tb11mr6885689ljk.118.1573218137226; \n\tFri, 08 Nov 2019 05:02:17 -0800 (PST)", "From": "Rasmus Villemoes <linux@rasmusvillemoes.dk>", "To": "Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,\n\tChristophe Leroy <christophe.leroy@c-s.fr>", "Subject": "[PATCH v4 39/47] soc: fsl: qe: avoid IS_ERR_VALUE in ucc_slow.c", "Date": "Fri, 8 Nov 2019 14:01:15 +0100", "Message-Id": "<20191108130123.6839-40-linux@rasmusvillemoes.dk>", "X-Mailer": "git-send-email 2.23.0", "In-Reply-To": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "References": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Scott Wood <oss@buserror.net>,\n\tRasmus Villemoes <linux@rasmusvillemoes.dk>, \n\tlinuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "When trying to build this for a 64-bit platform, one gets warnings\nfrom using IS_ERR_VALUE on something which is not sizeof(long).\n\nInstead, change the various *_offset fields to store a signed integer,\nand simply check for a negative return from qe_muram_alloc(). Since\nqe_muram_free() now accepts and ignores a negative argument, we only\nneed to make sure these fields are initialized with -1, and we can\njust unconditionally call qe_muram_free() in ucc_slow_free().\n\nNote that the error case for us_pram_offset failed to set that field\nto 0 (which, as noted earlier, is anyway a bogus sentinel value).\n\nSigned-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>\n---\n drivers/soc/fsl/qe/ucc_slow.c | 22 +++++++++-------------\n include/soc/fsl/qe/ucc_slow.h | 6 +++---\n 2 files changed, 12 insertions(+), 16 deletions(-)", "diff": "diff --git a/drivers/soc/fsl/qe/ucc_slow.c b/drivers/soc/fsl/qe/ucc_slow.c\nindex 9b55fd0f50c6..274d34449846 100644\n--- a/drivers/soc/fsl/qe/ucc_slow.c\n+++ b/drivers/soc/fsl/qe/ucc_slow.c\n@@ -154,6 +154,9 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc\n \t\t\t__func__);\n \t\treturn -ENOMEM;\n \t}\n+\tuccs->rx_base_offset = -1;\n+\tuccs->tx_base_offset = -1;\n+\tuccs->us_pram_offset = -1;\n \n \t/* Fill slow UCC structure */\n \tuccs->us_info = us_info;\n@@ -179,7 +182,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc\n \t/* Get PRAM base */\n \tuccs->us_pram_offset =\n \t\tqe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);\n-\tif (IS_ERR_VALUE(uccs->us_pram_offset)) {\n+\tif (uccs->us_pram_offset < 0) {\n \t\tprintk(KERN_ERR \"%s: cannot allocate MURAM for PRAM\", __func__);\n \t\tucc_slow_free(uccs);\n \t\treturn -ENOMEM;\n@@ -206,10 +209,9 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc\n \tuccs->rx_base_offset =\n \t\tqe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),\n \t\t\t\tQE_ALIGNMENT_OF_BD);\n-\tif (IS_ERR_VALUE(uccs->rx_base_offset)) {\n+\tif (uccs->rx_base_offset < 0) {\n \t\tprintk(KERN_ERR \"%s: cannot allocate %u RX BDs\\n\", __func__,\n \t\t\tus_info->rx_bd_ring_len);\n-\t\tuccs->rx_base_offset = 0;\n \t\tucc_slow_free(uccs);\n \t\treturn -ENOMEM;\n \t}\n@@ -217,9 +219,8 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc\n \tuccs->tx_base_offset =\n \t\tqe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),\n \t\t\tQE_ALIGNMENT_OF_BD);\n-\tif (IS_ERR_VALUE(uccs->tx_base_offset)) {\n+\tif (uccs->tx_base_offset < 0) {\n \t\tprintk(KERN_ERR \"%s: cannot allocate TX BDs\", __func__);\n-\t\tuccs->tx_base_offset = 0;\n \t\tucc_slow_free(uccs);\n \t\treturn -ENOMEM;\n \t}\n@@ -352,14 +353,9 @@ void ucc_slow_free(struct ucc_slow_private * uccs)\n \tif (!uccs)\n \t\treturn;\n \n-\tif (uccs->rx_base_offset)\n-\t\tqe_muram_free(uccs->rx_base_offset);\n-\n-\tif (uccs->tx_base_offset)\n-\t\tqe_muram_free(uccs->tx_base_offset);\n-\n-\tif (uccs->us_pram)\n-\t\tqe_muram_free(uccs->us_pram_offset);\n+\tqe_muram_free(uccs->rx_base_offset);\n+\tqe_muram_free(uccs->tx_base_offset);\n+\tqe_muram_free(uccs->us_pram_offset);\n \n \tif (uccs->us_regs)\n \t\tiounmap(uccs->us_regs);\ndiff --git a/include/soc/fsl/qe/ucc_slow.h b/include/soc/fsl/qe/ucc_slow.h\nindex 8696fdea2ae9..d187a6be83bc 100644\n--- a/include/soc/fsl/qe/ucc_slow.h\n+++ b/include/soc/fsl/qe/ucc_slow.h\n@@ -185,7 +185,7 @@ struct ucc_slow_private {\n \tstruct ucc_slow_info *us_info;\n \tstruct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */\n \tstruct ucc_slow_pram *us_pram;\t/* a pointer to the parameter RAM */\n-\tu32 us_pram_offset;\n+\ts32 us_pram_offset;\n \tint enabled_tx;\t\t/* Whether channel is enabled for Tx (ENT) */\n \tint enabled_rx;\t\t/* Whether channel is enabled for Rx (ENR) */\n \tint stopped_tx;\t\t/* Whether channel has been stopped for Tx\n@@ -194,8 +194,8 @@ struct ucc_slow_private {\n \tstruct list_head confQ;\t/* frames passed to chip waiting for tx */\n \tu32 first_tx_bd_mask;\t/* mask is used in Tx routine to save status\n \t\t\t\t and length for first BD in a frame */\n-\tu32 tx_base_offset;\t/* first BD in Tx BD table offset (In MURAM) */\n-\tu32 rx_base_offset;\t/* first BD in Rx BD table offset (In MURAM) */\n+\ts32 tx_base_offset;\t/* first BD in Tx BD table offset (In MURAM) */\n+\ts32 rx_base_offset;\t/* first BD in Rx BD table offset (In MURAM) */\n \tstruct qe_bd *confBd;\t/* next BD for confirm after Tx */\n \tstruct qe_bd *tx_bd;\t/* next BD for new Tx request */\n \tstruct qe_bd *rx_bd;\t/* next BD to collect after Rx */\n", "prefixes": [ "v4", "39/47" ] }