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GET /api/patches/1191942/?format=api
{ "id": 1191942, "url": "http://patchwork.ozlabs.org/api/patches/1191942/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-30-linux@rasmusvillemoes.dk/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20191108130123.6839-30-linux@rasmusvillemoes.dk>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20191108130123.6839-30-linux@rasmusvillemoes.dk/", "date": "2019-11-08T13:01:05", "name": "[v4,29/47] serial: ucc_uart: replace ppc-specific IO accessors", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "1c5b7e914ee9f3a749cd4c301d5c9e3a8b86acdf", "submitter": { "id": 27394, "url": "http://patchwork.ozlabs.org/api/people/27394/?format=api", "name": "Rasmus Villemoes", "email": "linux@rasmusvillemoes.dk" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-30-linux@rasmusvillemoes.dk/mbox/", "series": [ { "id": 141654, "url": "http://patchwork.ozlabs.org/api/series/141654/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=141654", "date": "2019-11-08T13:00:38", "name": "QUICC Engine support on ARM and ARM64", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/141654/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1191942/comments/", "check": "warning", "checks": "http://patchwork.ozlabs.org/api/patches/1191942/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 478jpz3hC4z9s4Y\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 01:49:47 +1100 (AEDT)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 478jpz1pFxzF5gb\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 01:49:47 +1100 (AEDT)", "from mail-lj1-x244.google.com (mail-lj1-x244.google.com\n\t[IPv6:2a00:1450:4864:20::244])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (2048 bits)\n\tserver-digest SHA256) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 478gQn6NwbzF6t6\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tSat, 9 Nov 2019 00:02:09 +1100 (AEDT)", "by mail-lj1-x244.google.com with SMTP id m9so6114055ljh.8\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 08 Nov 2019 05:02:09 -0800 (PST)", "from prevas-ravi.prevas.se ([81.216.59.226])\n\tby smtp.gmail.com with ESMTPSA id\n\td28sm2454725lfn.33.2019.11.08.05.02.03\n\t(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n\tFri, 08 Nov 2019 05:02:04 -0800 (PST)" ], "Authentication-Results": [ "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"O+yeEkWa\"; dkim-atps=neutral", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=rasmusvillemoes.dk (client-ip=2a00:1450:4864:20::244;\n\thelo=mail-lj1-x244.google.com; envelope-from=linux@rasmusvillemoes.dk;\n\treceiver=<UNKNOWN>)", "lists.ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "lists.ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"O+yeEkWa\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=rasmusvillemoes.dk; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=hS3pT5hJRUv2sQ4gkA9yffpuVvSl9rsKjuV5JcyqFr4=;\n\tb=O+yeEkWaGUZ6VYnDQCoE2Cjlb8yBgEDi0UD8IMt6gctO4RuQyf37GpIxSG35z2HEG3\n\td+7mvnCEuy8fqwjLL9mpdlU7HrGeugNuYHnLCDrNOkhkONC7UaDP4a+HIbottYSmN/VR\n\t2HjXvJMvlCGqkpD4qUznMuuxek0SVBpE3xDUg=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=hS3pT5hJRUv2sQ4gkA9yffpuVvSl9rsKjuV5JcyqFr4=;\n\tb=bWFP/F5UrnsQejnaurSqKXLoTy4kqF0koSE+GsutasPx9SbIwORCGn1HkzGCax6w/E\n\twWg9dH9QvLRX51Re0/AfSDG705XRXIohgpMPq6wF87C0K9Ivd57LyWqYihcCLyLCdcLw\n\tj1YWvuOAIfx33Uo4TV/Sls7KXdz/UpHJuAjkKko+l+nLPuElEB1LwHihxZJhsPSfUGOY\n\t/q09E7svXzS34ImakI5BIi2qcKxVbkcfcIss2/2ZLI8WSAZcccVfiaulX808jocfIVxr\n\tmAYW1cMeMkbHaeOB+54QmMbNRxGgEhyB2lXgZ15D7GdPcIfzXPqo0oV9KhaIsMh+4csr\n\t2C7w==", "X-Gm-Message-State": "APjAAAVdHqwxykvsn7bXCwVEooAyTQF8jjThlcIRK7tk/jtZ1WqysfKZ\n\tpif3c3/8IoOfARoyeTMJT50qqA==", "X-Google-Smtp-Source": "APXvYqyf6CTGX7jlG0JmmRxxUqAcNS8wg+ixKwFu38goimMF3S/YGYcDpFJWbHkekD4zO1MDADr3xg==", "X-Received": "by 2002:a2e:9659:: with SMTP id\n\tz25mr6861550ljh.132.1573218124786; \n\tFri, 08 Nov 2019 05:02:04 -0800 (PST)", "From": "Rasmus Villemoes <linux@rasmusvillemoes.dk>", "To": "Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,\n\tChristophe Leroy <christophe.leroy@c-s.fr>", "Subject": "[PATCH v4 29/47] serial: ucc_uart: replace ppc-specific IO accessors", "Date": "Fri, 8 Nov 2019 14:01:05 +0100", "Message-Id": "<20191108130123.6839-30-linux@rasmusvillemoes.dk>", "X-Mailer": "git-send-email 2.23.0", "In-Reply-To": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "References": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Rasmus Villemoes <linux@rasmusvillemoes.dk>, linux-kernel@vger.kernel.org,\n\tScott Wood <oss@buserror.net>, linux-serial@vger.kernel.org,\n\tlinuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Some ARM-based SOCs (e.g. LS1021A) also have a QUICC engine. As\npreparation for allowing this driver to build on ARM, replace the\nppc-specific in_be16() etc. by the qe_io* helpers. Done via\ncoccinelle.\n\nSigned-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>\n---\n drivers/tty/serial/ucc_uart.c | 210 +++++++++++++++++-----------------\n 1 file changed, 102 insertions(+), 108 deletions(-)", "diff": "diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c\nindex 7e802616cba8..8a378ee5d34f 100644\n--- a/drivers/tty/serial/ucc_uart.c\n+++ b/drivers/tty/serial/ucc_uart.c\n@@ -258,11 +258,11 @@ static unsigned int qe_uart_tx_empty(struct uart_port *port)\n \tstruct qe_bd *bdp = qe_port->tx_bd_base;\n \n \twhile (1) {\n-\t\tif (in_be16(&bdp->status) & BD_SC_READY)\n+\t\tif (qe_ioread16be(&bdp->status) & BD_SC_READY)\n \t\t\t/* This BD is not done, so return \"not done\" */\n \t\t\treturn 0;\n \n-\t\tif (in_be16(&bdp->status) & BD_SC_WRAP)\n+\t\tif (qe_ioread16be(&bdp->status) & BD_SC_WRAP)\n \t\t\t/*\n \t\t\t * This BD is done and it's the last one, so return\n \t\t\t * \"done\"\n@@ -308,7 +308,7 @@ static void qe_uart_stop_tx(struct uart_port *port)\n \tstruct uart_qe_port *qe_port =\n \t\tcontainer_of(port, struct uart_qe_port, port);\n \n-\tclrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);\n+\tqe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);\n }\n \n /*\n@@ -343,10 +343,10 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)\n \t\tp = qe2cpu_addr(bdp->buf, qe_port);\n \n \t\t*p++ = port->x_char;\n-\t\tout_be16(&bdp->length, 1);\n-\t\tsetbits16(&bdp->status, BD_SC_READY);\n+\t\tqe_iowrite16be(1, &bdp->length);\n+\t\tqe_setbits_be16(&bdp->status, BD_SC_READY);\n \t\t/* Get next BD. */\n-\t\tif (in_be16(&bdp->status) & BD_SC_WRAP)\n+\t\tif (qe_ioread16be(&bdp->status) & BD_SC_WRAP)\n \t\t\tbdp = qe_port->tx_bd_base;\n \t\telse\n \t\t\tbdp++;\n@@ -365,7 +365,7 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)\n \t/* Pick next descriptor and fill from buffer */\n \tbdp = qe_port->tx_cur;\n \n-\twhile (!(in_be16(&bdp->status) & BD_SC_READY) &&\n+\twhile (!(qe_ioread16be(&bdp->status) & BD_SC_READY) &&\n \t (xmit->tail != xmit->head)) {\n \t\tcount = 0;\n \t\tp = qe2cpu_addr(bdp->buf, qe_port);\n@@ -378,11 +378,11 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)\n \t\t\t\tbreak;\n \t\t}\n \n-\t\tout_be16(&bdp->length, count);\n-\t\tsetbits16(&bdp->status, BD_SC_READY);\n+\t\tqe_iowrite16be(count, &bdp->length);\n+\t\tqe_setbits_be16(&bdp->status, BD_SC_READY);\n \n \t\t/* Get next BD. */\n-\t\tif (in_be16(&bdp->status) & BD_SC_WRAP)\n+\t\tif (qe_ioread16be(&bdp->status) & BD_SC_WRAP)\n \t\t\tbdp = qe_port->tx_bd_base;\n \t\telse\n \t\t\tbdp++;\n@@ -415,12 +415,12 @@ static void qe_uart_start_tx(struct uart_port *port)\n \t\tcontainer_of(port, struct uart_qe_port, port);\n \n \t/* If we currently are transmitting, then just return */\n-\tif (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)\n+\tif (qe_ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)\n \t\treturn;\n \n \t/* Otherwise, pump the port and start transmission */\n \tif (qe_uart_tx_pump(qe_port))\n-\t\tsetbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);\n+\t\tqe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);\n }\n \n /*\n@@ -431,7 +431,7 @@ static void qe_uart_stop_rx(struct uart_port *port)\n \tstruct uart_qe_port *qe_port =\n \t\tcontainer_of(port, struct uart_qe_port, port);\n \n-\tclrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);\n+\tqe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);\n }\n \n /* Start or stop sending break signal\n@@ -470,14 +470,14 @@ static void qe_uart_int_rx(struct uart_qe_port *qe_port)\n \t */\n \tbdp = qe_port->rx_cur;\n \twhile (1) {\n-\t\tstatus = in_be16(&bdp->status);\n+\t\tstatus = qe_ioread16be(&bdp->status);\n \n \t\t/* If this one is empty, then we assume we've read them all */\n \t\tif (status & BD_SC_EMPTY)\n \t\t\tbreak;\n \n \t\t/* get number of characters, and check space in RX buffer */\n-\t\ti = in_be16(&bdp->length);\n+\t\ti = qe_ioread16be(&bdp->length);\n \n \t\t/* If we don't have enough room in RX buffer for the entire BD,\n \t\t * then we try later, which will be the next RX interrupt.\n@@ -508,9 +508,10 @@ static void qe_uart_int_rx(struct uart_qe_port *qe_port)\n \t\t}\n \n \t\t/* This BD is ready to be used again. Clear status. get next */\n-\t\tclrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR |\n-\t\t\tBD_SC_OV | BD_SC_ID, BD_SC_EMPTY);\n-\t\tif (in_be16(&bdp->status) & BD_SC_WRAP)\n+\t\tqe_clrsetbits_be16(&bdp->status,\n+\t\t\t\t BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID,\n+\t\t\t\t BD_SC_EMPTY);\n+\t\tif (qe_ioread16be(&bdp->status) & BD_SC_WRAP)\n \t\t\tbdp = qe_port->rx_bd_base;\n \t\telse\n \t\t\tbdp++;\n@@ -569,8 +570,8 @@ static irqreturn_t qe_uart_int(int irq, void *data)\n \tu16 events;\n \n \t/* Clear the interrupts */\n-\tevents = in_be16(&uccp->ucce);\n-\tout_be16(&uccp->ucce, events);\n+\tevents = qe_ioread16be(&uccp->ucce);\n+\tqe_iowrite16be(events, &uccp->ucce);\n \n \tif (events & UCC_UART_UCCE_BRKE)\n \t\tuart_handle_break(&qe_port->port);\n@@ -601,17 +602,17 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)\n \tbdp = qe_port->rx_bd_base;\n \tqe_port->rx_cur = qe_port->rx_bd_base;\n \tfor (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {\n-\t\tout_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT);\n-\t\tout_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));\n-\t\tout_be16(&bdp->length, 0);\n+\t\tqe_iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);\n+\t\tqe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);\n+\t\tqe_iowrite16be(0, &bdp->length);\n \t\tbd_virt += qe_port->rx_fifosize;\n \t\tbdp++;\n \t}\n \n \t/* */\n-\tout_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);\n-\tout_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));\n-\tout_be16(&bdp->length, 0);\n+\tqe_iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);\n+\tqe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);\n+\tqe_iowrite16be(0, &bdp->length);\n \n \t/* Set the physical address of the host memory\n \t * buffers in the buffer descriptors, and the\n@@ -622,21 +623,21 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)\n \tqe_port->tx_cur = qe_port->tx_bd_base;\n \tbdp = qe_port->tx_bd_base;\n \tfor (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {\n-\t\tout_be16(&bdp->status, BD_SC_INTRPT);\n-\t\tout_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));\n-\t\tout_be16(&bdp->length, 0);\n+\t\tqe_iowrite16be(BD_SC_INTRPT, &bdp->status);\n+\t\tqe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);\n+\t\tqe_iowrite16be(0, &bdp->length);\n \t\tbd_virt += qe_port->tx_fifosize;\n \t\tbdp++;\n \t}\n \n \t/* Loopback requires the preamble bit to be set on the first TX BD */\n #ifdef LOOPBACK\n-\tsetbits16(&qe_port->tx_cur->status, BD_SC_P);\n+\tqe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);\n #endif\n \n-\tout_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT);\n-\tout_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));\n-\tout_be16(&bdp->length, 0);\n+\tqe_iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);\n+\tqe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);\n+\tqe_iowrite16be(0, &bdp->length);\n }\n \n /*\n@@ -658,78 +659,74 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)\n \tucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);\n \n \t/* Program the UCC UART parameter RAM */\n-\tout_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);\n-\tout_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);\n-\tout_be16(&uccup->common.mrblr, qe_port->rx_fifosize);\n-\tout_be16(&uccup->maxidl, 0x10);\n-\tout_be16(&uccup->brkcr, 1);\n-\tout_be16(&uccup->parec, 0);\n-\tout_be16(&uccup->frmec, 0);\n-\tout_be16(&uccup->nosec, 0);\n-\tout_be16(&uccup->brkec, 0);\n-\tout_be16(&uccup->uaddr[0], 0);\n-\tout_be16(&uccup->uaddr[1], 0);\n-\tout_be16(&uccup->toseq, 0);\n+\tqe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);\n+\tqe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);\n+\tqe_iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);\n+\tqe_iowrite16be(0x10, &uccup->maxidl);\n+\tqe_iowrite16be(1, &uccup->brkcr);\n+\tqe_iowrite16be(0, &uccup->parec);\n+\tqe_iowrite16be(0, &uccup->frmec);\n+\tqe_iowrite16be(0, &uccup->nosec);\n+\tqe_iowrite16be(0, &uccup->brkec);\n+\tqe_iowrite16be(0, &uccup->uaddr[0]);\n+\tqe_iowrite16be(0, &uccup->uaddr[1]);\n+\tqe_iowrite16be(0, &uccup->toseq);\n \tfor (i = 0; i < 8; i++)\n-\t\tout_be16(&uccup->cchars[i], 0xC000);\n-\tout_be16(&uccup->rccm, 0xc0ff);\n+\t\tqe_iowrite16be(0xC000, &uccup->cchars[i]);\n+\tqe_iowrite16be(0xc0ff, &uccup->rccm);\n \n \t/* Configure the GUMR registers for UART */\n \tif (soft_uart) {\n \t\t/* Soft-UART requires a 1X multiplier for TX */\n-\t\tclrsetbits_be32(&uccp->gumr_l,\n-\t\t\tUCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |\n-\t\t\tUCC_SLOW_GUMR_L_RDCR_MASK,\n-\t\t\tUCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |\n-\t\t\tUCC_SLOW_GUMR_L_RDCR_16);\n-\n-\t\tclrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,\n-\t\t\tUCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);\n+\t\tqe_clrsetbits_be32(&uccp->gumr_l,\n+\t\t\t\t UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,\n+\t\t\t\t UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | UCC_SLOW_GUMR_L_RDCR_16);\n+\n+\t\tqe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,\n+\t\t\t\t UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);\n \t} else {\n-\t\tclrsetbits_be32(&uccp->gumr_l,\n-\t\t\tUCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |\n-\t\t\tUCC_SLOW_GUMR_L_RDCR_MASK,\n-\t\t\tUCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |\n-\t\t\tUCC_SLOW_GUMR_L_RDCR_16);\n-\n-\t\tclrsetbits_be32(&uccp->gumr_h,\n-\t\t\tUCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,\n-\t\t\tUCC_SLOW_GUMR_H_RFW);\n+\t\tqe_clrsetbits_be32(&uccp->gumr_l,\n+\t\t\t\t UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,\n+\t\t\t\t UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);\n+\n+\t\tqe_clrsetbits_be32(&uccp->gumr_h,\n+\t\t\t\t UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,\n+\t\t\t\t UCC_SLOW_GUMR_H_RFW);\n \t}\n \n #ifdef LOOPBACK\n-\tclrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,\n-\t\tUCC_SLOW_GUMR_L_DIAG_LOOP);\n-\tclrsetbits_be32(&uccp->gumr_h,\n-\t\tUCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,\n-\t\tUCC_SLOW_GUMR_H_CDS);\n+\tqe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,\n+\t\t\t UCC_SLOW_GUMR_L_DIAG_LOOP);\n+\tqe_clrsetbits_be32(&uccp->gumr_h,\n+\t\t\t UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,\n+\t\t\t UCC_SLOW_GUMR_H_CDS);\n #endif\n \n \t/* Disable rx interrupts and clear all pending events. */\n-\tout_be16(&uccp->uccm, 0);\n-\tout_be16(&uccp->ucce, 0xffff);\n-\tout_be16(&uccp->udsr, 0x7e7e);\n+\tqe_iowrite16be(0, &uccp->uccm);\n+\tqe_iowrite16be(0xffff, &uccp->ucce);\n+\tqe_iowrite16be(0x7e7e, &uccp->udsr);\n \n \t/* Initialize UPSMR */\n-\tout_be16(&uccp->upsmr, 0);\n+\tqe_iowrite16be(0, &uccp->upsmr);\n \n \tif (soft_uart) {\n-\t\tout_be16(&uccup->supsmr, 0x30);\n-\t\tout_be16(&uccup->res92, 0);\n-\t\tout_be32(&uccup->rx_state, 0);\n-\t\tout_be32(&uccup->rx_cnt, 0);\n-\t\tout_8(&uccup->rx_bitmark, 0);\n-\t\tout_8(&uccup->rx_length, 10);\n-\t\tout_be32(&uccup->dump_ptr, 0x4000);\n-\t\tout_8(&uccup->rx_temp_dlst_qe, 0);\n-\t\tout_be32(&uccup->rx_frame_rem, 0);\n-\t\tout_8(&uccup->rx_frame_rem_size, 0);\n+\t\tqe_iowrite16be(0x30, &uccup->supsmr);\n+\t\tqe_iowrite16be(0, &uccup->res92);\n+\t\tqe_iowrite32be(0, &uccup->rx_state);\n+\t\tqe_iowrite32be(0, &uccup->rx_cnt);\n+\t\tqe_iowrite8(0, &uccup->rx_bitmark);\n+\t\tqe_iowrite8(10, &uccup->rx_length);\n+\t\tqe_iowrite32be(0x4000, &uccup->dump_ptr);\n+\t\tqe_iowrite8(0, &uccup->rx_temp_dlst_qe);\n+\t\tqe_iowrite32be(0, &uccup->rx_frame_rem);\n+\t\tqe_iowrite8(0, &uccup->rx_frame_rem_size);\n \t\t/* Soft-UART requires TX to be 1X */\n-\t\tout_8(&uccup->tx_mode,\n-\t\t\tUCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1);\n-\t\tout_be16(&uccup->tx_state, 0);\n-\t\tout_8(&uccup->resD4, 0);\n-\t\tout_be16(&uccup->resD5, 0);\n+\t\tqe_iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,\n+\t\t\t &uccup->tx_mode);\n+\t\tqe_iowrite16be(0, &uccup->tx_state);\n+\t\tqe_iowrite8(0, &uccup->resD4);\n+\t\tqe_iowrite16be(0, &uccup->resD5);\n \n \t\t/* Set UART mode.\n \t\t * Enable receive and transmit.\n@@ -743,22 +740,19 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)\n \t\t * ...\n \t\t * 6.Receiver must use 16x over sampling\n \t\t */\n-\t\tclrsetbits_be32(&uccp->gumr_l,\n-\t\t\tUCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |\n-\t\t\tUCC_SLOW_GUMR_L_RDCR_MASK,\n-\t\t\tUCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 |\n-\t\t\tUCC_SLOW_GUMR_L_RDCR_16);\n+\t\tqe_clrsetbits_be32(&uccp->gumr_l,\n+\t\t\t\t UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,\n+\t\t\t\t UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);\n \n-\t\tclrsetbits_be32(&uccp->gumr_h,\n-\t\t\tUCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,\n-\t\t\tUCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX |\n-\t\t\tUCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);\n+\t\tqe_clrsetbits_be32(&uccp->gumr_h,\n+\t\t\t\t UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,\n+\t\t\t\t UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);\n \n #ifdef LOOPBACK\n-\t\tclrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,\n-\t\t\t\tUCC_SLOW_GUMR_L_DIAG_LOOP);\n-\t\tclrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP |\n-\t\t\t UCC_SLOW_GUMR_H_CDS);\n+\t\tqe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,\n+\t\t\t\t UCC_SLOW_GUMR_L_DIAG_LOOP);\n+\t\tqe_clrbits_be32(&uccp->gumr_h,\n+\t\t\t\tUCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_CDS);\n #endif\n \n \t\tcecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);\n@@ -801,7 +795,7 @@ static int qe_uart_startup(struct uart_port *port)\n \t}\n \n \t/* Startup rx-int */\n-\tsetbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);\n+\tqe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);\n \tucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);\n \n \treturn 0;\n@@ -837,7 +831,7 @@ static void qe_uart_shutdown(struct uart_port *port)\n \n \t/* Stop uarts */\n \tucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);\n-\tclrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);\n+\tqe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);\n \n \t/* Shut them really down and reinit buffer descriptors */\n \tucc_slow_graceful_stop_tx(qe_port->us_private);\n@@ -857,9 +851,9 @@ static void qe_uart_set_termios(struct uart_port *port,\n \tstruct ucc_slow __iomem *uccp = qe_port->uccp;\n \tunsigned int baud;\n \tunsigned long flags;\n-\tu16 upsmr = in_be16(&uccp->upsmr);\n+\tu16 upsmr = qe_ioread16be(&uccp->upsmr);\n \tstruct ucc_uart_pram __iomem *uccup = qe_port->uccup;\n-\tu16 supsmr = in_be16(&uccup->supsmr);\n+\tu16 supsmr = qe_ioread16be(&uccup->supsmr);\n \tu8 char_length = 2; /* 1 + CL + PEN + 1 + SL */\n \n \t/* Character length programmed into the mode register is the\n@@ -957,10 +951,10 @@ static void qe_uart_set_termios(struct uart_port *port,\n \t/* Update the per-port timeout. */\n \tuart_update_timeout(port, termios->c_cflag, baud);\n \n-\tout_be16(&uccp->upsmr, upsmr);\n+\tqe_iowrite16be(upsmr, &uccp->upsmr);\n \tif (soft_uart) {\n-\t\tout_be16(&uccup->supsmr, supsmr);\n-\t\tout_8(&uccup->rx_length, char_length);\n+\t\tqe_iowrite16be(supsmr, &uccup->supsmr);\n+\t\tqe_iowrite8(char_length, &uccup->rx_length);\n \n \t\t/* Soft-UART requires a 1X multiplier for TX */\n \t\tqe_setbrg(qe_port->us_info.rx_clock, baud, 16);\n", "prefixes": [ "v4", "29/47" ] }