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GET /api/patches/1191912/?format=api
{ "id": 1191912, "url": "http://patchwork.ozlabs.org/api/patches/1191912/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-22-linux@rasmusvillemoes.dk/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20191108130123.6839-22-linux@rasmusvillemoes.dk>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20191108130123.6839-22-linux@rasmusvillemoes.dk/", "date": "2019-11-08T13:00:57", "name": "[v4,21/47] soc: fsl: qe: merge qe_ic.h headers into qe_ic.c", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "80d6f09f89fb4c0929394951658d666a44cc880a", "submitter": { "id": 27394, "url": "http://patchwork.ozlabs.org/api/people/27394/?format=api", "name": "Rasmus Villemoes", "email": "linux@rasmusvillemoes.dk" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-22-linux@rasmusvillemoes.dk/mbox/", "series": [ { "id": 141654, "url": "http://patchwork.ozlabs.org/api/series/141654/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=141654", "date": "2019-11-08T13:00:38", "name": "QUICC Engine support on ARM and ARM64", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/141654/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1191912/comments/", "check": "success", "checks": "http://patchwork.ozlabs.org/api/patches/1191912/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 478jBR6gw8z9s4Y\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 01:21:35 +1100 (AEDT)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 478jBR48BpzF6Tp\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 01:21:35 +1100 (AEDT)", "from mail-lj1-x242.google.com (mail-lj1-x242.google.com\n\t[IPv6:2a00:1450:4864:20::242])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (2048 bits)\n\tserver-digest SHA256) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 478gQb0Lj9zF6tH\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tSat, 9 Nov 2019 00:01:59 +1100 (AEDT)", "by mail-lj1-x242.google.com with SMTP id e9so6090203ljp.13\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 08 Nov 2019 05:01:58 -0800 (PST)", "from prevas-ravi.prevas.se ([81.216.59.226])\n\tby smtp.gmail.com with ESMTPSA id\n\td28sm2454725lfn.33.2019.11.08.05.01.53\n\t(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n\tFri, 08 Nov 2019 05:01:54 -0800 (PST)" ], "Authentication-Results": [ "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"WBMs6v+U\"; dkim-atps=neutral", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=rasmusvillemoes.dk (client-ip=2a00:1450:4864:20::242;\n\thelo=mail-lj1-x242.google.com; envelope-from=linux@rasmusvillemoes.dk;\n\treceiver=<UNKNOWN>)", "lists.ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "lists.ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"WBMs6v+U\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=rasmusvillemoes.dk; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=E3PC0GBgcRJcw1cBz/t/6fNHbK3513aW1cpvhBViR+w=;\n\tb=WBMs6v+Uh0xmpwMVXsT7kku+eUv6ehM5s5BtzPv6w6wkzVfa5b1BQxkcRDWq85RGSD\n\tH5b9mG06oI+OPmDTYOTY+B99OLzic5P1w5a4n7eoYSdJix0QPdu7zK9uNaRtUkB8iDzE\n\toS6vhvtkC/z7ModAsNkSJszPrqRGmYrn1sXsI=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=E3PC0GBgcRJcw1cBz/t/6fNHbK3513aW1cpvhBViR+w=;\n\tb=rvQQLrGXqHoBVFy3fPs7btLR3XD38wKUMPMsbAn1+o6fmEbPHZRjkUDiCmnRCNr1M2\n\t7KNU1GTkx1nSjEMsKSl9HBQq1e9ZEdb+DKGpDsBf5sSr9hD1f6dZ4YCq6AAT0aCfbvgi\n\t+o2AMw0xI8mu9xiT+FjRbKyBeo2/9YIFmt2yCs4ArHlMqp9VZH0LWykBhPti6XKSrKx4\n\tdmE91dUz9DkDQYIUOp4usMHtdI9TBASABr6ED4mEjI4WnolSDeiml42b5vLTbf0HzIHO\n\tRZX3xso3B3s29y9WGXD6aRv2MIWDImL8yjX+f3K8RxLH2H1Er32P6cjeJdFvlxN7hjbM\n\tXn3Q==", "X-Gm-Message-State": "APjAAAUTVc0gypDvNj8TjzxbNptQUTnN9oVmqzmdzYrbPD00pABliKgn\n\tvIHr07rKOZKkpzd0SO2KBei0kA==", "X-Google-Smtp-Source": "APXvYqyFjKen6CS3WKeuslEAOUiLMLvgkLI5pRXG/qK74c6+e1zNbbGvIpzUavZLjoV7FOqoB9rs/A==", "X-Received": "by 2002:a05:651c:87:: with SMTP id\n\t7mr6917372ljq.20.1573218114921; \n\tFri, 08 Nov 2019 05:01:54 -0800 (PST)", "From": "Rasmus Villemoes <linux@rasmusvillemoes.dk>", "To": "Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,\n\tChristophe Leroy <christophe.leroy@c-s.fr>", "Subject": "[PATCH v4 21/47] soc: fsl: qe: merge qe_ic.h headers into qe_ic.c", "Date": "Fri, 8 Nov 2019 14:00:57 +0100", "Message-Id": "<20191108130123.6839-22-linux@rasmusvillemoes.dk>", "X-Mailer": "git-send-email 2.23.0", "In-Reply-To": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "References": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Scott Wood <oss@buserror.net>,\n\tRasmus Villemoes <linux@rasmusvillemoes.dk>, \n\tlinuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "The public qe_ic.h header is no longer included by anything but\nqe_ic.c. Merge both headers into qe_ic.c, and drop the unused\nconstants.\n\nSigned-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>\n---\n drivers/soc/fsl/qe/qe_ic.c | 52 +++++++++++++++++++-\n drivers/soc/fsl/qe/qe_ic.h | 99 --------------------------------------\n include/soc/fsl/qe/qe_ic.h | 56 ---------------------\n 3 files changed, 50 insertions(+), 157 deletions(-)\n delete mode 100644 drivers/soc/fsl/qe/qe_ic.h\n delete mode 100644 include/soc/fsl/qe/qe_ic.h", "diff": "diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c\nindex 4832884da5bb..0dd5bdb04a14 100644\n--- a/drivers/soc/fsl/qe/qe_ic.c\n+++ b/drivers/soc/fsl/qe/qe_ic.c\n@@ -15,6 +15,7 @@\n #include <linux/kernel.h>\n #include <linux/init.h>\n #include <linux/errno.h>\n+#include <linux/irq.h>\n #include <linux/reboot.h>\n #include <linux/slab.h>\n #include <linux/stddef.h>\n@@ -25,9 +26,56 @@\n #include <asm/irq.h>\n #include <asm/io.h>\n #include <soc/fsl/qe/qe.h>\n-#include <soc/fsl/qe/qe_ic.h>\n \n-#include \"qe_ic.h\"\n+#define NR_QE_IC_INTS\t\t64\n+\n+/* QE IC registers offset */\n+#define QEIC_CICR\t\t0x00\n+#define QEIC_CIVEC\t\t0x04\n+#define QEIC_CIPXCC\t\t0x10\n+#define QEIC_CIPYCC\t\t0x14\n+#define QEIC_CIPWCC\t\t0x18\n+#define QEIC_CIPZCC\t\t0x1c\n+#define QEIC_CIMR\t\t0x20\n+#define QEIC_CRIMR\t\t0x24\n+#define QEIC_CIPRTA\t\t0x30\n+#define QEIC_CIPRTB\t\t0x34\n+#define QEIC_CHIVEC\t\t0x60\n+\n+struct qe_ic {\n+\t/* Control registers offset */\n+\tu32 __iomem *regs;\n+\n+\t/* The remapper for this QEIC */\n+\tstruct irq_domain *irqhost;\n+\n+\t/* The \"linux\" controller struct */\n+\tstruct irq_chip hc_irq;\n+\n+\t/* VIRQ numbers of QE high/low irqs */\n+\tunsigned int virq_high;\n+\tunsigned int virq_low;\n+};\n+\n+/*\n+ * QE interrupt controller internal structure\n+ */\n+struct qe_ic_info {\n+\t/* Location of this source at the QIMR register */\n+\tu32\tmask;\n+\n+\t/* Mask register offset */\n+\tu32\tmask_reg;\n+\n+\t/*\n+\t * For grouped interrupts sources - the interrupt code as\n+\t * appears at the group priority register\n+\t */\n+\tu8\tpri_code;\n+\n+\t/* Group priority register offset */\n+\tu32\tpri_reg;\n+};\n \n static DEFINE_RAW_SPINLOCK(qe_ic_lock);\n \ndiff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h\ndeleted file mode 100644\nindex 9420378d9b6b..000000000000\n--- a/drivers/soc/fsl/qe/qe_ic.h\n+++ /dev/null\n@@ -1,99 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0-or-later */\n-/*\n- * drivers/soc/fsl/qe/qe_ic.h\n- *\n- * QUICC ENGINE Interrupt Controller Header\n- *\n- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.\n- *\n- * Author: Li Yang <leoli@freescale.com>\n- * Based on code from Shlomi Gridish <gridish@freescale.com>\n- */\n-#ifndef _POWERPC_SYSDEV_QE_IC_H\n-#define _POWERPC_SYSDEV_QE_IC_H\n-\n-#include <soc/fsl/qe/qe_ic.h>\n-\n-#define NR_QE_IC_INTS\t\t64\n-\n-/* QE IC registers offset */\n-#define QEIC_CICR\t\t0x00\n-#define QEIC_CIVEC\t\t0x04\n-#define QEIC_CRIPNR\t\t0x08\n-#define QEIC_CIPNR\t\t0x0c\n-#define QEIC_CIPXCC\t\t0x10\n-#define QEIC_CIPYCC\t\t0x14\n-#define QEIC_CIPWCC\t\t0x18\n-#define QEIC_CIPZCC\t\t0x1c\n-#define QEIC_CIMR\t\t0x20\n-#define QEIC_CRIMR\t\t0x24\n-#define QEIC_CICNR\t\t0x28\n-#define QEIC_CIPRTA\t\t0x30\n-#define QEIC_CIPRTB\t\t0x34\n-#define QEIC_CRICR\t\t0x3c\n-#define QEIC_CHIVEC\t\t0x60\n-\n-/* Interrupt priority registers */\n-#define CIPCC_SHIFT_PRI0\t29\n-#define CIPCC_SHIFT_PRI1\t26\n-#define CIPCC_SHIFT_PRI2\t23\n-#define CIPCC_SHIFT_PRI3\t20\n-#define CIPCC_SHIFT_PRI4\t13\n-#define CIPCC_SHIFT_PRI5\t10\n-#define CIPCC_SHIFT_PRI6\t7\n-#define CIPCC_SHIFT_PRI7\t4\n-\n-/* CICR priority modes */\n-#define CICR_GWCC\t\t0x00040000\n-#define CICR_GXCC\t\t0x00020000\n-#define CICR_GYCC\t\t0x00010000\n-#define CICR_GZCC\t\t0x00080000\n-#define CICR_GRTA\t\t0x00200000\n-#define CICR_GRTB\t\t0x00400000\n-#define CICR_HPIT_SHIFT\t\t8\n-#define CICR_HPIT_MASK\t\t0x00000300\n-#define CICR_HP_SHIFT\t\t24\n-#define CICR_HP_MASK\t\t0x3f000000\n-\n-/* CICNR */\n-#define CICNR_WCC1T_SHIFT\t20\n-#define CICNR_ZCC1T_SHIFT\t28\n-#define CICNR_YCC1T_SHIFT\t12\n-#define CICNR_XCC1T_SHIFT\t4\n-\n-/* CRICR */\n-#define CRICR_RTA1T_SHIFT\t20\n-#define CRICR_RTB1T_SHIFT\t28\n-\n-/* Signal indicator */\n-#define SIGNAL_MASK\t\t3\n-#define SIGNAL_HIGH\t\t2\n-#define SIGNAL_LOW\t\t0\n-\n-struct qe_ic {\n-\t/* Control registers offset */\n-\tu32 __iomem *regs;\n-\n-\t/* The remapper for this QEIC */\n-\tstruct irq_domain *irqhost;\n-\n-\t/* The \"linux\" controller struct */\n-\tstruct irq_chip hc_irq;\n-\n-\t/* VIRQ numbers of QE high/low irqs */\n-\tunsigned int virq_high;\n-\tunsigned int virq_low;\n-};\n-\n-/*\n- * QE interrupt controller internal structure\n- */\n-struct qe_ic_info {\n-\tu32\tmask;\t /* location of this source at the QIMR register. */\n-\tu32\tmask_reg; /* Mask register offset */\n-\tu8\tpri_code; /* for grouped interrupts sources - the interrupt\n-\t\t\t code as appears at the group priority register */\n-\tu32\tpri_reg; /* Group priority register offset */\n-};\n-\n-#endif /* _POWERPC_SYSDEV_QE_IC_H */\ndiff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h\ndeleted file mode 100644\nindex 70bb5a0f6535..000000000000\n--- a/include/soc/fsl/qe/qe_ic.h\n+++ /dev/null\n@@ -1,56 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0-or-later */\n-/*\n- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.\n- *\n- * Authors: \tShlomi Gridish <gridish@freescale.com>\n- * \t\tLi Yang <leoli@freescale.com>\n- *\n- * Description:\n- * QE IC external definitions and structure.\n- */\n-#ifndef _ASM_POWERPC_QE_IC_H\n-#define _ASM_POWERPC_QE_IC_H\n-\n-#include <linux/irq.h>\n-\n-struct device_node;\n-struct qe_ic;\n-\n-#define NUM_OF_QE_IC_GROUPS\t6\n-\n-/* Flags when we init the QE IC */\n-#define QE_IC_SPREADMODE_GRP_W\t\t\t0x00000001\n-#define QE_IC_SPREADMODE_GRP_X\t\t\t0x00000002\n-#define QE_IC_SPREADMODE_GRP_Y\t\t\t0x00000004\n-#define QE_IC_SPREADMODE_GRP_Z\t\t\t0x00000008\n-#define QE_IC_SPREADMODE_GRP_RISCA\t\t0x00000010\n-#define QE_IC_SPREADMODE_GRP_RISCB\t\t0x00000020\n-\n-#define QE_IC_LOW_SIGNAL\t\t\t0x00000100\n-#define QE_IC_HIGH_SIGNAL\t\t\t0x00000200\n-\n-#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH\t0x00001000\n-#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH\t0x00002000\n-#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH\t0x00004000\n-#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH\t0x00008000\n-#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH\t0x00010000\n-#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH\t0x00020000\n-#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH\t0x00040000\n-#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH\t0x00080000\n-#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH\t0x00100000\n-#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH\t0x00200000\n-#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH\t0x00400000\n-#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH\t0x00800000\n-#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT\t\t(12)\n-\n-/* QE interrupt sources groups */\n-enum qe_ic_grp_id {\n-\tQE_IC_GRP_W = 0,\t/* QE interrupt controller group W */\n-\tQE_IC_GRP_X,\t\t/* QE interrupt controller group X */\n-\tQE_IC_GRP_Y,\t\t/* QE interrupt controller group Y */\n-\tQE_IC_GRP_Z,\t\t/* QE interrupt controller group Z */\n-\tQE_IC_GRP_RISCA,\t/* QE interrupt controller RISC group A */\n-\tQE_IC_GRP_RISCB\t\t/* QE interrupt controller RISC group B */\n-};\n-\n-#endif /* _ASM_POWERPC_QE_IC_H */\n", "prefixes": [ "v4", "21/47" ] }