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GET /api/patches/1191908/?format=api
{ "id": 1191908, "url": "http://patchwork.ozlabs.org/api/patches/1191908/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-18-linux@rasmusvillemoes.dk/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20191108130123.6839-18-linux@rasmusvillemoes.dk>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20191108130123.6839-18-linux@rasmusvillemoes.dk/", "date": "2019-11-08T13:00:53", "name": "[v4,17/47] soc: fsl: qe: remove unused qe_ic_set_* functions", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "015627cdd3dd9e451ecaacbec33e81192e8723c4", "submitter": { "id": 27394, "url": "http://patchwork.ozlabs.org/api/people/27394/?format=api", "name": "Rasmus Villemoes", "email": "linux@rasmusvillemoes.dk" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-18-linux@rasmusvillemoes.dk/mbox/", "series": [ { "id": 141654, "url": "http://patchwork.ozlabs.org/api/series/141654/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=141654", "date": "2019-11-08T13:00:38", "name": "QUICC Engine support on ARM and ARM64", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/141654/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1191908/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1191908/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 478hxB3tpCz9sNT\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 01:10:06 +1100 (AEDT)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 478hxB0CPhzDsxF\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 01:10:06 +1100 (AEDT)", "from mail-lf1-x144.google.com (mail-lf1-x144.google.com\n\t[IPv6:2a00:1450:4864:20::144])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (2048 bits)\n\tserver-digest SHA256) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 478gQT3qYGzF6sj\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tSat, 9 Nov 2019 00:01:53 +1100 (AEDT)", "by mail-lf1-x144.google.com with SMTP id m6so4421772lfl.3\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 08 Nov 2019 05:01:53 -0800 (PST)", "from prevas-ravi.prevas.se ([81.216.59.226])\n\tby smtp.gmail.com with ESMTPSA id\n\td28sm2454725lfn.33.2019.11.08.05.01.49\n\t(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n\tFri, 08 Nov 2019 05:01:49 -0800 (PST)" ], "Authentication-Results": [ "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"fdJQuwFQ\"; dkim-atps=neutral", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=rasmusvillemoes.dk (client-ip=2a00:1450:4864:20::144;\n\thelo=mail-lf1-x144.google.com; envelope-from=linux@rasmusvillemoes.dk;\n\treceiver=<UNKNOWN>)", "lists.ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "lists.ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"fdJQuwFQ\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=rasmusvillemoes.dk; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=z2c319/rjPUXp8iRV62XAcjKgiOjRbx515GvierWVkM=;\n\tb=fdJQuwFQEx3WiNuMOb1gdsH9SW9HI7w7+NIWF38nxViFmcIxtLR9epgSWnsWqGFr/4\n\t41v4fU4VePhq0oBGJYDl/RN7X1BEoWQl3Z5KthO6Przp/ZZJbJLo1K7p+2g9VgKelj7W\n\t2z4QZPD8TJ1MwkV9FRtWWs+r90Jdp/lOZJ2a4=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=z2c319/rjPUXp8iRV62XAcjKgiOjRbx515GvierWVkM=;\n\tb=rmzp3mlZEVXJvtNY6fgR0inmKngacoE+mW1fFJQgNXF7c2oMPpyw5ZswZLbQN+mN4p\n\t5uCRYq6OGyiWwq+IZjkYr+Z3+ZOTbZYyFFLZvUBIaVJ3+nQ00RBd7MtDu7aJCUy1FiXJ\n\tyupQZhl8lKnUFzAN47Sd4FVTZZZYvj5uiOslZFzVbmlohNa6/pYS3UW7F63WbEMmViR/\n\t3SETWKNsgTSteQYf2fsElTbYVrW76y1TrI8sqHUk8vP9INj9cMPl9HRKbQLrLJSeVPGQ\n\teG1KYgROXhXvxnFchoW+P3YWlo3r71H8MUfLdr1y3+1Jt1h3lUsalJ5zwVJg33t8K/qy\n\tejSQ==", "X-Gm-Message-State": "APjAAAWtK9Dsg3+OQLHXYcmIUFmmb5ytN3TZYFekeJZbKLahrMBJwx7c\n\t0/cA6/qub1qIcgLoSDbwO02hwA==", "X-Google-Smtp-Source": "APXvYqxHLvZgvF+EG0/l58iTz6Czvi2Tdy1nhKy8rpZoIP81L5RxYC4QrddV3/xHVXg3rNCq06dYbw==", "X-Received": "by 2002:a05:6512:509:: with SMTP id\n\to9mr6810861lfb.28.1573218110212; \n\tFri, 08 Nov 2019 05:01:50 -0800 (PST)", "From": "Rasmus Villemoes <linux@rasmusvillemoes.dk>", "To": "Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,\n\tChristophe Leroy <christophe.leroy@c-s.fr>", "Subject": "[PATCH v4 17/47] soc: fsl: qe: remove unused qe_ic_set_* functions", "Date": "Fri, 8 Nov 2019 14:00:53 +0100", "Message-Id": "<20191108130123.6839-18-linux@rasmusvillemoes.dk>", "X-Mailer": "git-send-email 2.23.0", "In-Reply-To": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "References": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Scott Wood <oss@buserror.net>,\n\tRasmus Villemoes <linux@rasmusvillemoes.dk>, \n\tlinuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "There are no current callers of these functions, and they use the\nppc-specific virq_to_hw(). So removing them gets us one step closer to\nbuilding QE support for ARM.\n\nIf the functionality is ever actually needed, the code can be dug out\nof git and then adapted to work on all architectures, but for future\nreference please note that I believe qe_ic_set_priority is buggy: The\n\"priority < 4\" should be \"priority <= 4\", and in the else branch 24\nshould be replaced by 28, at least if I'm reading the data sheet right.\n\nSigned-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>\n---\n drivers/soc/fsl/qe/qe_ic.c | 94 --------------------------------------\n include/soc/fsl/qe/qe_ic.h | 4 --\n 2 files changed, 98 deletions(-)", "diff": "diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c\nindex de2ca2e3a648..4839dcd5c5d3 100644\n--- a/drivers/soc/fsl/qe/qe_ic.c\n+++ b/drivers/soc/fsl/qe/qe_ic.c\n@@ -445,97 +445,3 @@ static int __init qe_ic_of_init(void)\n \treturn 0;\n }\n subsys_initcall(qe_ic_of_init);\n-\n-void qe_ic_set_highest_priority(unsigned int virq, int high)\n-{\n-\tstruct qe_ic *qe_ic = qe_ic_from_irq(virq);\n-\tunsigned int src = virq_to_hw(virq);\n-\tu32 temp = 0;\n-\n-\ttemp = qe_ic_read(qe_ic->regs, QEIC_CICR);\n-\n-\ttemp &= ~CICR_HP_MASK;\n-\ttemp |= src << CICR_HP_SHIFT;\n-\n-\ttemp &= ~CICR_HPIT_MASK;\n-\ttemp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;\n-\n-\tqe_ic_write(qe_ic->regs, QEIC_CICR, temp);\n-}\n-\n-/* Set Priority level within its group, from 1 to 8 */\n-int qe_ic_set_priority(unsigned int virq, unsigned int priority)\n-{\n-\tstruct qe_ic *qe_ic = qe_ic_from_irq(virq);\n-\tunsigned int src = virq_to_hw(virq);\n-\tu32 temp;\n-\n-\tif (priority > 8 || priority == 0)\n-\t\treturn -EINVAL;\n-\tif (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),\n-\t\t \"%s: Invalid hw irq number for QEIC\\n\", __func__))\n-\t\treturn -EINVAL;\n-\tif (qe_ic_info[src].pri_reg == 0)\n-\t\treturn -EINVAL;\n-\n-\ttemp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);\n-\n-\tif (priority < 4) {\n-\t\ttemp &= ~(0x7 << (32 - priority * 3));\n-\t\ttemp |= qe_ic_info[src].pri_code << (32 - priority * 3);\n-\t} else {\n-\t\ttemp &= ~(0x7 << (24 - priority * 3));\n-\t\ttemp |= qe_ic_info[src].pri_code << (24 - priority * 3);\n-\t}\n-\n-\tqe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);\n-\n-\treturn 0;\n-}\n-\n-/* Set a QE priority to use high irq, only priority 1~2 can use high irq */\n-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)\n-{\n-\tstruct qe_ic *qe_ic = qe_ic_from_irq(virq);\n-\tunsigned int src = virq_to_hw(virq);\n-\tu32 temp, control_reg = QEIC_CICNR, shift = 0;\n-\n-\tif (priority > 2 || priority == 0)\n-\t\treturn -EINVAL;\n-\tif (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),\n-\t\t \"%s: Invalid hw irq number for QEIC\\n\", __func__))\n-\t\treturn -EINVAL;\n-\n-\tswitch (qe_ic_info[src].pri_reg) {\n-\tcase QEIC_CIPZCC:\n-\t\tshift = CICNR_ZCC1T_SHIFT;\n-\t\tbreak;\n-\tcase QEIC_CIPWCC:\n-\t\tshift = CICNR_WCC1T_SHIFT;\n-\t\tbreak;\n-\tcase QEIC_CIPYCC:\n-\t\tshift = CICNR_YCC1T_SHIFT;\n-\t\tbreak;\n-\tcase QEIC_CIPXCC:\n-\t\tshift = CICNR_XCC1T_SHIFT;\n-\t\tbreak;\n-\tcase QEIC_CIPRTA:\n-\t\tshift = CRICR_RTA1T_SHIFT;\n-\t\tcontrol_reg = QEIC_CRICR;\n-\t\tbreak;\n-\tcase QEIC_CIPRTB:\n-\t\tshift = CRICR_RTB1T_SHIFT;\n-\t\tcontrol_reg = QEIC_CRICR;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tshift += (2 - priority) * 2;\n-\ttemp = qe_ic_read(qe_ic->regs, control_reg);\n-\ttemp &= ~(SIGNAL_MASK << shift);\n-\ttemp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;\n-\tqe_ic_write(qe_ic->regs, control_reg, temp);\n-\n-\treturn 0;\n-}\ndiff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h\nindex 43e4ce95c6a0..d47eb231519e 100644\n--- a/include/soc/fsl/qe/qe_ic.h\n+++ b/include/soc/fsl/qe/qe_ic.h\n@@ -63,8 +63,4 @@ static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)\n { return 0; }\n #endif /* CONFIG_QUICC_ENGINE */\n \n-void qe_ic_set_highest_priority(unsigned int virq, int high);\n-int qe_ic_set_priority(unsigned int virq, unsigned int priority);\n-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);\n-\n #endif /* _ASM_POWERPC_QE_IC_H */\n", "prefixes": [ "v4", "17/47" ] }