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GET /api/patches/1191880/?format=api
{ "id": 1191880, "url": "http://patchwork.ozlabs.org/api/patches/1191880/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-6-linux@rasmusvillemoes.dk/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20191108130123.6839-6-linux@rasmusvillemoes.dk>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20191108130123.6839-6-linux@rasmusvillemoes.dk/", "date": "2019-11-08T13:00:41", "name": "[v4,05/47] soc: fsl: qe: avoid ppc-specific io accessors", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "26f4b3db17306d86e8672015b9f66cc39bc97783", "submitter": { "id": 27394, "url": "http://patchwork.ozlabs.org/api/people/27394/?format=api", "name": "Rasmus Villemoes", "email": "linux@rasmusvillemoes.dk" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-6-linux@rasmusvillemoes.dk/mbox/", "series": [ { "id": 141654, "url": "http://patchwork.ozlabs.org/api/series/141654/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=141654", "date": "2019-11-08T13:00:38", "name": "QUICC Engine support on ARM and ARM64", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/141654/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1191880/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1191880/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 478h2p39f3z9s4Y\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 00:29:54 +1100 (AEDT)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 478h2n6xxbzF4m5\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 00:29:53 +1100 (AEDT)", "from mail-lf1-x141.google.com (mail-lf1-x141.google.com\n\t[IPv6:2a00:1450:4864:20::141])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (2048 bits)\n\tserver-digest SHA256) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 478gQB6Y02zF6qp\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tSat, 9 Nov 2019 00:01:38 +1100 (AEDT)", "by mail-lf1-x141.google.com with SMTP id z12so4389145lfj.9\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 08 Nov 2019 05:01:38 -0800 (PST)", "from prevas-ravi.prevas.se ([81.216.59.226])\n\tby smtp.gmail.com with ESMTPSA id\n\td28sm2454725lfn.33.2019.11.08.05.01.33\n\t(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n\tFri, 08 Nov 2019 05:01:33 -0800 (PST)" ], "Authentication-Results": [ "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"ZLrdoZll\"; dkim-atps=neutral", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=rasmusvillemoes.dk (client-ip=2a00:1450:4864:20::141;\n\thelo=mail-lf1-x141.google.com; envelope-from=linux@rasmusvillemoes.dk;\n\treceiver=<UNKNOWN>)", "lists.ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "lists.ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"ZLrdoZll\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=rasmusvillemoes.dk; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=9tOABT8Py4DEmejfsYkpbe8Y4MrdN9utZ1d8Z7Y4oFk=;\n\tb=ZLrdoZllzlmKWNxePUr2w2zELkj6EHNNcwfPM7ULBvrOl+1LXh8+1x3CgnatpT+ez0\n\t99vPuqpxGLPEW2ACbdubpWxlezsAlPlmF1tcJ1xTVO7YeZyYfWgc7HzLdobfquTZEkVx\n\tawQVPV8vVQPU4cnjzUXcMFpflhxqXnujpetC8=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=9tOABT8Py4DEmejfsYkpbe8Y4MrdN9utZ1d8Z7Y4oFk=;\n\tb=HC1/uEBWY+m066LJVDk3YReOtywANvbS8UUhHRJ/NBeaMvyQF3Lb9FJLBda5NFpadJ\n\tl82FApS8EtMb2xjOJ5veVLpV2xbwsf+OBpHt79ZpGctwx3Njn+Uwpr2sGwBI5cwLNEON\n\tX6xxSJsa1tTV/zBRYAXofdNAGZudSjXN0TDyZ2M07pOIOOFLRkGSeICZtZopqdOou971\n\txDEX4JPVP4bMA8BYXwSmMK8WXTX8ckudore1INu52d1GHuqAboRYYZ8+kQ9gVeqKcNBs\n\tJIw+u/E/jLQ0kLfA25efapvlYsbteUEiPbkBHWLFN+moTwZ79peQx3n8fDlDtDK7ahlG\n\t3m1A==", "X-Gm-Message-State": "APjAAAV1f6R2FkPadvYdz7zgT7VbayRoKK2CtnzaVM4lkAYUgAXUrLUA\n\tTh3f7wZb13OBgwkOgQnStuIL6w==", "X-Google-Smtp-Source": "APXvYqylTzkr4IPJiFrmC5GN0MZu+6lZ0HTBWClbfAuYvAjBSym0/ERt6lGLbzvPdel+Gv+ccjuzMQ==", "X-Received": "by 2002:a19:7607:: with SMTP id c7mr6747990lff.62.1573218094453; \n\tFri, 08 Nov 2019 05:01:34 -0800 (PST)", "From": "Rasmus Villemoes <linux@rasmusvillemoes.dk>", "To": "Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,\n\tChristophe Leroy <christophe.leroy@c-s.fr>", "Subject": "[PATCH v4 05/47] soc: fsl: qe: avoid ppc-specific io accessors", "Date": "Fri, 8 Nov 2019 14:00:41 +0100", "Message-Id": "<20191108130123.6839-6-linux@rasmusvillemoes.dk>", "X-Mailer": "git-send-email 2.23.0", "In-Reply-To": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "References": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Scott Wood <oss@buserror.net>,\n\tRasmus Villemoes <linux@rasmusvillemoes.dk>, \n\tlinuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "In preparation for allowing to build QE support for architectures\nother than PPC, replace the ppc-specific io accessors by the qe_io*\nmacros. Done via\n\n$ spatch --sp-file io.cocci --in-place drivers/soc/fsl/qe/\n\nwhere io.cocci is\n\n@@\nexpression addr, val;\n@@\n- out_be32(addr, val)\n+ qe_iowrite32be(val, addr)\n\n@@\nexpression addr;\n@@\n- in_be32(addr)\n+ qe_ioread32be(addr)\n\n@@\nexpression addr, val;\n@@\n- out_be16(addr, val)\n+ qe_iowrite16be(val, addr)\n\n@@\nexpression addr;\n@@\n- in_be16(addr)\n+ qe_ioread16be(addr)\n\n@@\nexpression addr, val;\n@@\n- out_8(addr, val)\n+ qe_iowrite8(val, addr)\n\n@@\nexpression addr;\n@@\n- in_8(addr)\n+ qe_ioread8(addr)\n\n@@\nexpression addr, clr, set;\n@@\n- clrsetbits_be32(addr, clr, set)\n+ qe_clrsetbits_be32(addr, clr, set)\n\n@@\nexpression addr, clr, set;\n@@\n- clrsetbits_be16(addr, clr, set)\n+ qe_clrsetbits_be16(addr, clr, set)\n\n@@\nexpression addr, clr, set;\n@@\n- clrsetbits_8(addr, clr, set)\n+ qe_clrsetbits_8(addr, clr, set)\n\n@@\nexpression addr, set;\n@@\n- setbits32(addr, set)\n+ qe_setbits_be32(addr, set)\n\n@@\nexpression addr, set;\n@@\n- setbits16(addr, set)\n+ qe_setbits_be16(addr, set)\n\n@@\nexpression addr, set;\n@@\n- setbits8(addr, set)\n+ qe_setbits_8(addr, set)\n\n@@\nexpression addr, clr;\n@@\n- clrbits32(addr, clr)\n+ qe_clrbits_be32(addr, clr)\n\n@@\nexpression addr, clr;\n@@\n- clrbits16(addr, clr)\n+ qe_clrbits_be16(addr, clr)\n\n@@\nexpression addr, clr;\n@@\n- clrbits8(addr, clr)\n+ qe_clrbits_8(addr, clr)\n\nSigned-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>\n---\n drivers/soc/fsl/qe/gpio.c | 34 +++++++++--------\n drivers/soc/fsl/qe/qe.c | 38 ++++++++++---------\n drivers/soc/fsl/qe/qe_ic.c | 5 ++-\n drivers/soc/fsl/qe/qe_io.c | 40 +++++++++-----------\n drivers/soc/fsl/qe/qe_tdm.c | 8 ++--\n drivers/soc/fsl/qe/ucc.c | 16 ++++----\n drivers/soc/fsl/qe/ucc_fast.c | 71 ++++++++++++++++++-----------------\n drivers/soc/fsl/qe/ucc_slow.c | 38 +++++++++----------\n drivers/soc/fsl/qe/usb.c | 2 +-\n 9 files changed, 129 insertions(+), 123 deletions(-)", "diff": "diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c\nindex f0c29ed8f0ff..12bdfd9cbe7c 100644\n--- a/drivers/soc/fsl/qe/gpio.c\n+++ b/drivers/soc/fsl/qe/gpio.c\n@@ -41,13 +41,13 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)\n \t\tcontainer_of(mm_gc, struct qe_gpio_chip, mm_gc);\n \tstruct qe_pio_regs __iomem *regs = mm_gc->regs;\n \n-\tqe_gc->cpdata = in_be32(®s->cpdata);\n+\tqe_gc->cpdata = qe_ioread32be(®s->cpdata);\n \tqe_gc->saved_regs.cpdata = qe_gc->cpdata;\n-\tqe_gc->saved_regs.cpdir1 = in_be32(®s->cpdir1);\n-\tqe_gc->saved_regs.cpdir2 = in_be32(®s->cpdir2);\n-\tqe_gc->saved_regs.cppar1 = in_be32(®s->cppar1);\n-\tqe_gc->saved_regs.cppar2 = in_be32(®s->cppar2);\n-\tqe_gc->saved_regs.cpodr = in_be32(®s->cpodr);\n+\tqe_gc->saved_regs.cpdir1 = qe_ioread32be(®s->cpdir1);\n+\tqe_gc->saved_regs.cpdir2 = qe_ioread32be(®s->cpdir2);\n+\tqe_gc->saved_regs.cppar1 = qe_ioread32be(®s->cppar1);\n+\tqe_gc->saved_regs.cppar2 = qe_ioread32be(®s->cppar2);\n+\tqe_gc->saved_regs.cpodr = qe_ioread32be(®s->cpodr);\n }\n \n static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)\n@@ -56,7 +56,7 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)\n \tstruct qe_pio_regs __iomem *regs = mm_gc->regs;\n \tu32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);\n \n-\treturn !!(in_be32(®s->cpdata) & pin_mask);\n+\treturn !!(qe_ioread32be(®s->cpdata) & pin_mask);\n }\n \n static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)\n@@ -74,7 +74,7 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)\n \telse\n \t\tqe_gc->cpdata &= ~pin_mask;\n \n-\tout_be32(®s->cpdata, qe_gc->cpdata);\n+\tqe_iowrite32be(qe_gc->cpdata, ®s->cpdata);\n \n \tspin_unlock_irqrestore(&qe_gc->lock, flags);\n }\n@@ -101,7 +101,7 @@ static void qe_gpio_set_multiple(struct gpio_chip *gc,\n \t\t}\n \t}\n \n-\tout_be32(®s->cpdata, qe_gc->cpdata);\n+\tqe_iowrite32be(qe_gc->cpdata, ®s->cpdata);\n \n \tspin_unlock_irqrestore(&qe_gc->lock, flags);\n }\n@@ -255,11 +255,15 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)\n \tspin_lock_irqsave(&qe_gc->lock, flags);\n \n \tif (second_reg) {\n-\t\tclrsetbits_be32(®s->cpdir2, mask2, sregs->cpdir2 & mask2);\n-\t\tclrsetbits_be32(®s->cppar2, mask2, sregs->cppar2 & mask2);\n+\t\tqe_clrsetbits_be32(®s->cpdir2, mask2,\n+\t\t\t\t sregs->cpdir2 & mask2);\n+\t\tqe_clrsetbits_be32(®s->cppar2, mask2,\n+\t\t\t\t sregs->cppar2 & mask2);\n \t} else {\n-\t\tclrsetbits_be32(®s->cpdir1, mask2, sregs->cpdir1 & mask2);\n-\t\tclrsetbits_be32(®s->cppar1, mask2, sregs->cppar1 & mask2);\n+\t\tqe_clrsetbits_be32(®s->cpdir1, mask2,\n+\t\t\t\t sregs->cpdir1 & mask2);\n+\t\tqe_clrsetbits_be32(®s->cppar1, mask2,\n+\t\t\t\t sregs->cppar1 & mask2);\n \t}\n \n \tif (sregs->cpdata & mask1)\n@@ -267,8 +271,8 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)\n \telse\n \t\tqe_gc->cpdata &= ~mask1;\n \n-\tout_be32(®s->cpdata, qe_gc->cpdata);\n-\tclrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);\n+\tqe_iowrite32be(qe_gc->cpdata, ®s->cpdata);\n+\tqe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);\n \n \tspin_unlock_irqrestore(&qe_gc->lock, flags);\n }\ndiff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c\nindex 2a0e6e642776..456bd7416876 100644\n--- a/drivers/soc/fsl/qe/qe.c\n+++ b/drivers/soc/fsl/qe/qe.c\n@@ -112,7 +112,7 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)\n \n \tspin_lock_irqsave(&qe_lock, flags);\n \tif (cmd == QE_RESET) {\n-\t\tout_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));\n+\t\tqe_iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);\n \t} else {\n \t\tif (cmd == QE_ASSIGN_PAGE) {\n \t\t\t/* Here device is the SNUM, not sub-block */\n@@ -129,15 +129,14 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)\n \t\t\t\tmcn_shift = QE_CR_MCN_NORMAL_SHIFT;\n \t\t}\n \n-\t\tout_be32(&qe_immr->cp.cecdr, cmd_input);\n-\t\tout_be32(&qe_immr->cp.cecr,\n-\t\t\t (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)\n-\t\t\t mcn_protocol << mcn_shift));\n+\t\tqe_iowrite32be(cmd_input, &qe_immr->cp.cecdr);\n+\t\tqe_iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) | (u32)mcn_protocol << mcn_shift),\n+\t\t\t &qe_immr->cp.cecr);\n \t}\n \n \t/* wait for the QE_CR_FLG to clear */\n-\tret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,\n-\t\t\t 100, 0);\n+\tret = spin_event_timeout((qe_ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,\n+\t\t\t\t 100, 0);\n \t/* On timeout (e.g. failure), the expression will be false (ret == 0),\n \t otherwise it will be true (ret == 1). */\n \tspin_unlock_irqrestore(&qe_lock, flags);\n@@ -230,7 +229,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)\n \ttempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |\n \t\tQE_BRGC_ENABLE | div16;\n \n-\tout_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);\n+\tqe_iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);\n \n \treturn 0;\n }\n@@ -377,9 +376,10 @@ static int qe_sdma_init(void)\n \t\t\treturn -ENOMEM;\n \t}\n \n-\tout_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);\n-\tout_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |\n-\t\t (0x1 << QE_SDMR_CEN_SHIFT)));\n+\tqe_iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK,\n+\t\t &sdma->sdebcr);\n+\tqe_iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),\n+\t\t &sdma->sdmr);\n \n \treturn 0;\n }\n@@ -417,14 +417,14 @@ static void qe_upload_microcode(const void *base,\n \t\t\t\"uploading microcode '%s'\\n\", ucode->id);\n \n \t/* Use auto-increment */\n-\tout_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |\n-\t\tQE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);\n+\tqe_iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,\n+\t\t &qe_immr->iram.iadd);\n \n \tfor (i = 0; i < be32_to_cpu(ucode->count); i++)\n-\t\tout_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));\n+\t\tqe_iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);\n \t\n \t/* Set I-RAM Ready Register */\n-\tout_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));\n+\tqe_iowrite32be(be32_to_cpu(QE_IRAM_READY), &qe_immr->iram.iready);\n }\n \n /*\n@@ -509,7 +509,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)\n \t * If the microcode calls for it, split the I-RAM.\n \t */\n \tif (!firmware->split)\n-\t\tsetbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);\n+\t\tqe_setbits_be16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);\n \n \tif (firmware->soc.model)\n \t\tprintk(KERN_INFO\n@@ -543,11 +543,13 @@ int qe_upload_firmware(const struct qe_firmware *firmware)\n \t\t\tu32 trap = be32_to_cpu(ucode->traps[j]);\n \n \t\t\tif (trap)\n-\t\t\t\tout_be32(&qe_immr->rsp[i].tibcr[j], trap);\n+\t\t\t\tqe_iowrite32be(trap,\n+\t\t\t\t\t &qe_immr->rsp[i].tibcr[j]);\n \t\t}\n \n \t\t/* Enable traps */\n-\t\tout_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));\n+\t\tqe_iowrite32be(be32_to_cpu(ucode->eccr),\n+\t\t\t &qe_immr->rsp[i].eccr);\n \t}\n \n \tqe_firmware_uploaded = 1;\ndiff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c\nindex 791adcd121d1..8c874372416b 100644\n--- a/drivers/soc/fsl/qe/qe_ic.c\n+++ b/drivers/soc/fsl/qe/qe_ic.c\n@@ -24,6 +24,7 @@\n #include <linux/spinlock.h>\n #include <asm/irq.h>\n #include <asm/io.h>\n+#include <soc/fsl/qe/qe.h>\n #include <soc/fsl/qe/qe_ic.h>\n \n #include \"qe_ic.h\"\n@@ -173,13 +174,13 @@ static struct qe_ic_info qe_ic_info[] = {\n \n static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)\n {\n-\treturn in_be32(base + (reg >> 2));\n+\treturn qe_ioread32be(base + (reg >> 2));\n }\n \n static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,\n \t\t\t u32 value)\n {\n-\tout_be32(base + (reg >> 2), value);\n+\tqe_iowrite32be(value, base + (reg >> 2));\n }\n \n static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)\ndiff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c\nindex 3657e296a8a2..5e3471ac09dd 100644\n--- a/drivers/soc/fsl/qe/qe_io.c\n+++ b/drivers/soc/fsl/qe/qe_io.c\n@@ -57,16 +57,16 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,\n \tpin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));\n \n \t/* Set open drain, if required */\n-\ttmp_val = in_be32(&par_io->cpodr);\n+\ttmp_val = qe_ioread32be(&par_io->cpodr);\n \tif (open_drain)\n-\t\tout_be32(&par_io->cpodr, pin_mask1bit | tmp_val);\n+\t\tqe_iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);\n \telse\n-\t\tout_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);\n+\t\tqe_iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);\n \n \t/* define direction */\n \ttmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?\n-\t\tin_be32(&par_io->cpdir2) :\n-\t\tin_be32(&par_io->cpdir1);\n+\t\tqe_ioread32be(&par_io->cpdir2) :\n+\t\tqe_ioread32be(&par_io->cpdir1);\n \n \t/* get all bits mask for 2 bit per port */\n \tpin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -\n@@ -78,34 +78,30 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,\n \n \t/* clear and set 2 bits mask */\n \tif (pin > (QE_PIO_PINS / 2) - 1) {\n-\t\tout_be32(&par_io->cpdir2,\n-\t\t\t ~pin_mask2bits & tmp_val);\n+\t\tqe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);\n \t\ttmp_val &= ~pin_mask2bits;\n-\t\tout_be32(&par_io->cpdir2, new_mask2bits | tmp_val);\n+\t\tqe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);\n \t} else {\n-\t\tout_be32(&par_io->cpdir1,\n-\t\t\t ~pin_mask2bits & tmp_val);\n+\t\tqe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);\n \t\ttmp_val &= ~pin_mask2bits;\n-\t\tout_be32(&par_io->cpdir1, new_mask2bits | tmp_val);\n+\t\tqe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);\n \t}\n \t/* define pin assignment */\n \ttmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?\n-\t\tin_be32(&par_io->cppar2) :\n-\t\tin_be32(&par_io->cppar1);\n+\t\tqe_ioread32be(&par_io->cppar2) :\n+\t\tqe_ioread32be(&par_io->cppar1);\n \n \tnew_mask2bits = (u32) (assignment << (QE_PIO_PINS -\n \t\t\t(pin % (QE_PIO_PINS / 2) + 1) * 2));\n \t/* clear and set 2 bits mask */\n \tif (pin > (QE_PIO_PINS / 2) - 1) {\n-\t\tout_be32(&par_io->cppar2,\n-\t\t\t ~pin_mask2bits & tmp_val);\n+\t\tqe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);\n \t\ttmp_val &= ~pin_mask2bits;\n-\t\tout_be32(&par_io->cppar2, new_mask2bits | tmp_val);\n+\t\tqe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);\n \t} else {\n-\t\tout_be32(&par_io->cppar1,\n-\t\t\t ~pin_mask2bits & tmp_val);\n+\t\tqe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);\n \t\ttmp_val &= ~pin_mask2bits;\n-\t\tout_be32(&par_io->cppar1, new_mask2bits | tmp_val);\n+\t\tqe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);\n \t}\n }\n EXPORT_SYMBOL(__par_io_config_pin);\n@@ -133,12 +129,12 @@ int par_io_data_set(u8 port, u8 pin, u8 val)\n \t/* calculate pin location */\n \tpin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));\n \n-\ttmp_val = in_be32(&par_io[port].cpdata);\n+\ttmp_val = qe_ioread32be(&par_io[port].cpdata);\n \n \tif (val == 0)\t\t/* clear */\n-\t\tout_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);\n+\t\tqe_iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);\n \telse\t\t\t/* set */\n-\t\tout_be32(&par_io[port].cpdata, pin_mask | tmp_val);\n+\t\tqe_iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);\n \n \treturn 0;\n }\ndiff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c\nindex e37ebc3be661..7d7d78d3ee50 100644\n--- a/drivers/soc/fsl/qe/qe_tdm.c\n+++ b/drivers/soc/fsl/qe/qe_tdm.c\n@@ -169,10 +169,10 @@ void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)\n \t\t\t\t &siram[siram_entry_id * 32 + 0x200 + i]);\n \t}\n \n-\tsetbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],\n-\t\t SIR_LAST);\n-\tsetbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],\n-\t\t SIR_LAST);\n+\tqe_setbits_be16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],\n+\t\t\tSIR_LAST);\n+\tqe_setbits_be16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],\n+\t\t\tSIR_LAST);\n \n \t/* Set SIxMR register */\n \tsixmr = SIMR_SAD(siram_entry_id);\ndiff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c\nindex ae9f2cf560cb..da3d7e2dd837 100644\n--- a/drivers/soc/fsl/qe/ucc.c\n+++ b/drivers/soc/fsl/qe/ucc.c\n@@ -35,8 +35,8 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)\n \t\treturn -EINVAL;\n \n \tspin_lock_irqsave(&cmxgcr_lock, flags);\n-\tclrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,\n-\t\tucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);\n+\tqe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,\n+\t\t\t ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);\n \tspin_unlock_irqrestore(&cmxgcr_lock, flags);\n \n \treturn 0;\n@@ -80,8 +80,8 @@ int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)\n \t\treturn -EINVAL;\n \t}\n \n-\tclrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,\n-\t\tUCC_GUEMR_SET_RESERVED3 | speed);\n+\tqe_clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,\n+\t\t\tUCC_GUEMR_SET_RESERVED3 | speed);\n \n \treturn 0;\n }\n@@ -109,9 +109,9 @@ int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)\n \tget_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);\n \n \tif (set)\n-\t\tsetbits32(cmxucr, mask << shift);\n+\t\tqe_setbits_be32(cmxucr, mask << shift);\n \telse\n-\t\tclrbits32(cmxucr, mask << shift);\n+\t\tqe_clrbits_be32(cmxucr, mask << shift);\n \n \treturn 0;\n }\n@@ -207,8 +207,8 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,\n \tif (mode == COMM_DIR_RX)\n \t\tshift += 4;\n \n-\tclrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,\n-\t\tclock_bits << shift);\n+\tqe_clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,\n+\t\t\t clock_bits << shift);\n \n \treturn 0;\n }\ndiff --git a/drivers/soc/fsl/qe/ucc_fast.c b/drivers/soc/fsl/qe/ucc_fast.c\nindex af4d80e38521..ca0452497a20 100644\n--- a/drivers/soc/fsl/qe/ucc_fast.c\n+++ b/drivers/soc/fsl/qe/ucc_fast.c\n@@ -29,41 +29,42 @@ void ucc_fast_dump_regs(struct ucc_fast_private * uccf)\n \tprintk(KERN_INFO \"Base address: 0x%p\\n\", uccf->uf_regs);\n \n \tprintk(KERN_INFO \"gumr : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));\n+\t\t &uccf->uf_regs->gumr, qe_ioread32be(&uccf->uf_regs->gumr));\n \tprintk(KERN_INFO \"upsmr : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));\n+\t\t &uccf->uf_regs->upsmr, qe_ioread32be(&uccf->uf_regs->upsmr));\n \tprintk(KERN_INFO \"utodr : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));\n+\t\t &uccf->uf_regs->utodr, qe_ioread16be(&uccf->uf_regs->utodr));\n \tprintk(KERN_INFO \"udsr : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));\n+\t\t &uccf->uf_regs->udsr, qe_ioread16be(&uccf->uf_regs->udsr));\n \tprintk(KERN_INFO \"ucce : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));\n+\t\t &uccf->uf_regs->ucce, qe_ioread32be(&uccf->uf_regs->ucce));\n \tprintk(KERN_INFO \"uccm : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));\n+\t\t &uccf->uf_regs->uccm, qe_ioread32be(&uccf->uf_regs->uccm));\n \tprintk(KERN_INFO \"uccs : addr=0x%p, val=0x%02x\\n\",\n-\t\t &uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs));\n+\t\t &uccf->uf_regs->uccs, qe_ioread8(&uccf->uf_regs->uccs));\n \tprintk(KERN_INFO \"urfb : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));\n+\t\t &uccf->uf_regs->urfb, qe_ioread32be(&uccf->uf_regs->urfb));\n \tprintk(KERN_INFO \"urfs : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));\n+\t\t &uccf->uf_regs->urfs, qe_ioread16be(&uccf->uf_regs->urfs));\n \tprintk(KERN_INFO \"urfet : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));\n+\t\t &uccf->uf_regs->urfet, qe_ioread16be(&uccf->uf_regs->urfet));\n \tprintk(KERN_INFO \"urfset: addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));\n+\t\t &uccf->uf_regs->urfset,\n+\t\t qe_ioread16be(&uccf->uf_regs->urfset));\n \tprintk(KERN_INFO \"utfb : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));\n+\t\t &uccf->uf_regs->utfb, qe_ioread32be(&uccf->uf_regs->utfb));\n \tprintk(KERN_INFO \"utfs : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));\n+\t\t &uccf->uf_regs->utfs, qe_ioread16be(&uccf->uf_regs->utfs));\n \tprintk(KERN_INFO \"utfet : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));\n+\t\t &uccf->uf_regs->utfet, qe_ioread16be(&uccf->uf_regs->utfet));\n \tprintk(KERN_INFO \"utftt : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));\n+\t\t &uccf->uf_regs->utftt, qe_ioread16be(&uccf->uf_regs->utftt));\n \tprintk(KERN_INFO \"utpt : addr=0x%p, val=0x%04x\\n\",\n-\t\t &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));\n+\t\t &uccf->uf_regs->utpt, qe_ioread16be(&uccf->uf_regs->utpt));\n \tprintk(KERN_INFO \"urtry : addr=0x%p, val=0x%08x\\n\",\n-\t\t &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));\n+\t\t &uccf->uf_regs->urtry, qe_ioread32be(&uccf->uf_regs->urtry));\n \tprintk(KERN_INFO \"guemr : addr=0x%p, val=0x%02x\\n\",\n-\t\t &uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr));\n+\t\t &uccf->uf_regs->guemr, qe_ioread8(&uccf->uf_regs->guemr));\n }\n EXPORT_SYMBOL(ucc_fast_dump_regs);\n \n@@ -85,7 +86,7 @@ EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);\n \n void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)\n {\n-\tout_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);\n+\tqe_iowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr);\n }\n EXPORT_SYMBOL(ucc_fast_transmit_on_demand);\n \n@@ -97,7 +98,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)\n \tuf_regs = uccf->uf_regs;\n \n \t/* Enable reception and/or transmission on this UCC. */\n-\tgumr = in_be32(&uf_regs->gumr);\n+\tgumr = qe_ioread32be(&uf_regs->gumr);\n \tif (mode & COMM_DIR_TX) {\n \t\tgumr |= UCC_FAST_GUMR_ENT;\n \t\tuccf->enabled_tx = 1;\n@@ -106,7 +107,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)\n \t\tgumr |= UCC_FAST_GUMR_ENR;\n \t\tuccf->enabled_rx = 1;\n \t}\n-\tout_be32(&uf_regs->gumr, gumr);\n+\tqe_iowrite32be(gumr, &uf_regs->gumr);\n }\n EXPORT_SYMBOL(ucc_fast_enable);\n \n@@ -118,7 +119,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)\n \tuf_regs = uccf->uf_regs;\n \n \t/* Disable reception and/or transmission on this UCC. */\n-\tgumr = in_be32(&uf_regs->gumr);\n+\tgumr = qe_ioread32be(&uf_regs->gumr);\n \tif (mode & COMM_DIR_TX) {\n \t\tgumr &= ~UCC_FAST_GUMR_ENT;\n \t\tuccf->enabled_tx = 0;\n@@ -127,7 +128,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)\n \t\tgumr &= ~UCC_FAST_GUMR_ENR;\n \t\tuccf->enabled_rx = 0;\n \t}\n-\tout_be32(&uf_regs->gumr, gumr);\n+\tqe_iowrite32be(gumr, &uf_regs->gumr);\n }\n EXPORT_SYMBOL(ucc_fast_disable);\n \n@@ -259,7 +260,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc\n \tgumr |= uf_info->tenc;\n \tgumr |= uf_info->tcrc;\n \tgumr |= uf_info->mode;\n-\tout_be32(&uf_regs->gumr, gumr);\n+\tqe_iowrite32be(gumr, &uf_regs->gumr);\n \n \t/* Allocate memory for Tx Virtual Fifo */\n \tuccf->ucc_fast_tx_virtual_fifo_base_offset =\n@@ -286,15 +287,17 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc\n \t}\n \n \t/* Set Virtual Fifo registers */\n-\tout_be16(&uf_regs->urfs, uf_info->urfs);\n-\tout_be16(&uf_regs->urfet, uf_info->urfet);\n-\tout_be16(&uf_regs->urfset, uf_info->urfset);\n-\tout_be16(&uf_regs->utfs, uf_info->utfs);\n-\tout_be16(&uf_regs->utfet, uf_info->utfet);\n-\tout_be16(&uf_regs->utftt, uf_info->utftt);\n+\tqe_iowrite16be(uf_info->urfs, &uf_regs->urfs);\n+\tqe_iowrite16be(uf_info->urfet, &uf_regs->urfet);\n+\tqe_iowrite16be(uf_info->urfset, &uf_regs->urfset);\n+\tqe_iowrite16be(uf_info->utfs, &uf_regs->utfs);\n+\tqe_iowrite16be(uf_info->utfet, &uf_regs->utfet);\n+\tqe_iowrite16be(uf_info->utftt, &uf_regs->utftt);\n \t/* utfb, urfb are offsets from MURAM base */\n-\tout_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);\n-\tout_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);\n+\tqe_iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset,\n+\t\t &uf_regs->utfb);\n+\tqe_iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset,\n+\t\t &uf_regs->urfb);\n \n \t/* Mux clocking */\n \t/* Grant Support */\n@@ -362,14 +365,14 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc\n \t}\n \n \t/* Set interrupt mask register at UCC level. */\n-\tout_be32(&uf_regs->uccm, uf_info->uccm_mask);\n+\tqe_iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);\n \n \t/* First, clear anything pending at UCC level,\n \t * otherwise, old garbage may come through\n \t * as soon as the dam is opened. */\n \n \t/* Writing '1' clears */\n-\tout_be32(&uf_regs->ucce, 0xffffffff);\n+\tqe_iowrite32be(0xffffffff, &uf_regs->ucce);\n \n \t*uccf_ret = uccf;\n \treturn 0;\ndiff --git a/drivers/soc/fsl/qe/ucc_slow.c b/drivers/soc/fsl/qe/ucc_slow.c\nindex 34f0ec3a63b5..9b55fd0f50c6 100644\n--- a/drivers/soc/fsl/qe/ucc_slow.c\n+++ b/drivers/soc/fsl/qe/ucc_slow.c\n@@ -78,7 +78,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)\n \tus_regs = uccs->us_regs;\n \n \t/* Enable reception and/or transmission on this UCC. */\n-\tgumr_l = in_be32(&us_regs->gumr_l);\n+\tgumr_l = qe_ioread32be(&us_regs->gumr_l);\n \tif (mode & COMM_DIR_TX) {\n \t\tgumr_l |= UCC_SLOW_GUMR_L_ENT;\n \t\tuccs->enabled_tx = 1;\n@@ -87,7 +87,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)\n \t\tgumr_l |= UCC_SLOW_GUMR_L_ENR;\n \t\tuccs->enabled_rx = 1;\n \t}\n-\tout_be32(&us_regs->gumr_l, gumr_l);\n+\tqe_iowrite32be(gumr_l, &us_regs->gumr_l);\n }\n EXPORT_SYMBOL(ucc_slow_enable);\n \n@@ -99,7 +99,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)\n \tus_regs = uccs->us_regs;\n \n \t/* Disable reception and/or transmission on this UCC. */\n-\tgumr_l = in_be32(&us_regs->gumr_l);\n+\tgumr_l = qe_ioread32be(&us_regs->gumr_l);\n \tif (mode & COMM_DIR_TX) {\n \t\tgumr_l &= ~UCC_SLOW_GUMR_L_ENT;\n \t\tuccs->enabled_tx = 0;\n@@ -108,7 +108,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)\n \t\tgumr_l &= ~UCC_SLOW_GUMR_L_ENR;\n \t\tuccs->enabled_rx = 0;\n \t}\n-\tout_be32(&us_regs->gumr_l, gumr_l);\n+\tqe_iowrite32be(gumr_l, &us_regs->gumr_l);\n }\n EXPORT_SYMBOL(ucc_slow_disable);\n \n@@ -198,7 +198,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc\n \t\treturn ret;\n \t}\n \n-\tout_be16(&uccs->us_pram->mrblr, us_info->max_rx_buf_length);\n+\tqe_iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr);\n \n \tINIT_LIST_HEAD(&uccs->confQ);\n \n@@ -228,27 +228,27 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc\n \tbd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);\n \tfor (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {\n \t\t/* clear bd buffer */\n-\t\tout_be32(&bd->buf, 0);\n+\t\tqe_iowrite32be(0, &bd->buf);\n \t\t/* set bd status and length */\n-\t\tout_be32((u32 *) bd, 0);\n+\t\tqe_iowrite32be(0, (u32 *)bd);\n \t\tbd++;\n \t}\n \t/* for last BD set Wrap bit */\n-\tout_be32(&bd->buf, 0);\n-\tout_be32((u32 *) bd, cpu_to_be32(T_W));\n+\tqe_iowrite32be(0, &bd->buf);\n+\tqe_iowrite32be(cpu_to_be32(T_W), (u32 *)bd);\n \n \t/* Init Rx bds */\n \tbd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);\n \tfor (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {\n \t\t/* set bd status and length */\n-\t\tout_be32((u32*)bd, 0);\n+\t\tqe_iowrite32be(0, (u32 *)bd);\n \t\t/* clear bd buffer */\n-\t\tout_be32(&bd->buf, 0);\n+\t\tqe_iowrite32be(0, &bd->buf);\n \t\tbd++;\n \t}\n \t/* for last BD set Wrap bit */\n-\tout_be32((u32*)bd, cpu_to_be32(R_W));\n-\tout_be32(&bd->buf, 0);\n+\tqe_iowrite32be(cpu_to_be32(R_W), (u32 *)bd);\n+\tqe_iowrite32be(0, &bd->buf);\n \n \t/* Set GUMR (For more details see the hardware spec.). */\n \t/* gumr_h */\n@@ -269,7 +269,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc\n \t\tgumr |= UCC_SLOW_GUMR_H_TXSY;\n \tif (us_info->rtsm)\n \t\tgumr |= UCC_SLOW_GUMR_H_RTSM;\n-\tout_be32(&us_regs->gumr_h, gumr);\n+\tqe_iowrite32be(gumr, &us_regs->gumr_h);\n \n \t/* gumr_l */\n \tgumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |\n@@ -282,7 +282,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc\n \t\tgumr |= UCC_SLOW_GUMR_L_TINV;\n \tif (us_info->tend)\n \t\tgumr |= UCC_SLOW_GUMR_L_TEND;\n-\tout_be32(&us_regs->gumr_l, gumr);\n+\tqe_iowrite32be(gumr, &us_regs->gumr_l);\n \n \t/* Function code registers */\n \n@@ -292,8 +292,8 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc\n \tuccs->us_pram->rbmr = UCC_BMR_BO_BE;\n \n \t/* rbase, tbase are offsets from MURAM base */\n-\tout_be16(&uccs->us_pram->rbase, uccs->rx_base_offset);\n-\tout_be16(&uccs->us_pram->tbase, uccs->tx_base_offset);\n+\tqe_iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase);\n+\tqe_iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase);\n \n \t/* Mux clocking */\n \t/* Grant Support */\n@@ -323,14 +323,14 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc\n \t}\n \n \t/* Set interrupt mask register at UCC level. */\n-\tout_be16(&us_regs->uccm, us_info->uccm_mask);\n+\tqe_iowrite16be(us_info->uccm_mask, &us_regs->uccm);\n \n \t/* First, clear anything pending at UCC level,\n \t * otherwise, old garbage may come through\n \t * as soon as the dam is opened. */\n \n \t/* Writing '1' clears */\n-\tout_be16(&us_regs->ucce, 0xffff);\n+\tqe_iowrite16be(0xffff, &us_regs->ucce);\n \n \t/* Issue QE Init command */\n \tif (us_info->init_tx && us_info->init_rx)\ndiff --git a/drivers/soc/fsl/qe/usb.c b/drivers/soc/fsl/qe/usb.c\nindex 32d8269fa692..890f236ea697 100644\n--- a/drivers/soc/fsl/qe/usb.c\n+++ b/drivers/soc/fsl/qe/usb.c\n@@ -43,7 +43,7 @@ int qe_usb_clock_set(enum qe_clock clk, int rate)\n \n \tspin_lock_irqsave(&cmxgcr_lock, flags);\n \n-\tclrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);\n+\tqe_clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);\n \n \tspin_unlock_irqrestore(&cmxgcr_lock, flags);\n \n", "prefixes": [ "v4", "05/47" ] }