Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1191877/?format=api
{ "id": 1191877, "url": "http://patchwork.ozlabs.org/api/patches/1191877/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-5-linux@rasmusvillemoes.dk/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20191108130123.6839-5-linux@rasmusvillemoes.dk>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20191108130123.6839-5-linux@rasmusvillemoes.dk/", "date": "2019-11-08T13:00:40", "name": "[v4,04/47] soc: fsl: qe: introduce qe_io{read,write}* wrappers", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "91068886704bfe34a26ba9ff2e67dc858ac95cc4", "submitter": { "id": 27394, "url": "http://patchwork.ozlabs.org/api/people/27394/?format=api", "name": "Rasmus Villemoes", "email": "linux@rasmusvillemoes.dk" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-5-linux@rasmusvillemoes.dk/mbox/", "series": [ { "id": 141654, "url": "http://patchwork.ozlabs.org/api/series/141654/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=141654", "date": "2019-11-08T13:00:38", "name": "QUICC Engine support on ARM and ARM64", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/141654/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1191877/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1191877/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 478gph25Zxz9sPk\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 00:19:24 +1100 (AEDT)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 478gph0HTxzF3fR\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 00:19:24 +1100 (AEDT)", "from mail-lf1-x143.google.com (mail-lf1-x143.google.com\n\t[IPv6:2a00:1450:4864:20::143])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (2048 bits)\n\tserver-digest SHA256) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 478gQ86tntzF6t8\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tSat, 9 Nov 2019 00:01:36 +1100 (AEDT)", "by mail-lf1-x143.google.com with SMTP id j14so4393156lfb.8\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 08 Nov 2019 05:01:36 -0800 (PST)", "from prevas-ravi.prevas.se ([81.216.59.226])\n\tby smtp.gmail.com with ESMTPSA id\n\td28sm2454725lfn.33.2019.11.08.05.01.31\n\t(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n\tFri, 08 Nov 2019 05:01:32 -0800 (PST)" ], "Authentication-Results": [ "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"arBXPaYv\"; dkim-atps=neutral", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=rasmusvillemoes.dk (client-ip=2a00:1450:4864:20::143;\n\thelo=mail-lf1-x143.google.com; envelope-from=linux@rasmusvillemoes.dk;\n\treceiver=<UNKNOWN>)", "lists.ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "lists.ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"arBXPaYv\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=rasmusvillemoes.dk; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=KoynnpqyM2T+oZqn3mX12olVYK6D1zjkp8rnCkTSUvs=;\n\tb=arBXPaYvk7b9VQYEk27Lbsm2eaj47OMjYlVYaqSiH0ymjHtJ0z8jMJOs56Fvd8UuBJ\n\tNKk3dJoZqQrq8Qd6neEX/y/JOno76+Cbx1L38NbXMark/8C5i8DIGjC8HDXiz6AkmhZZ\n\tZs4D4v6HFqp/TvlK8kAms9Xw0N+CDuG7slgBM=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=KoynnpqyM2T+oZqn3mX12olVYK6D1zjkp8rnCkTSUvs=;\n\tb=luo7mTCg8IZxNHcRvffd6fAAdZjYIDSwreSp4eXVLyskEoIldLFsQBKEIRpUGxTeEA\n\t39HZKso4cn4V9hYINDwMiM8tyx1rWHI9Tj4l3bLJv0ZuAjNTjch5eVsiJN/nfNY0wbR7\n\tl3amaag0j/2hO/z2MRi1yIH+JJ0dkzbjsBLlWbV6xexrYPv4gEDQHq8jiCF+e7MzLPVd\n\tToK8IJS+dTbn2clG6DPFMDMSMdIRjtsJZzGI1SD+qffxvTt5hMVmT9xc7A+xSXOLQfLT\n\tnfnhaYJHsBBfIVwOskbzMLvTpndTj27qRIkKVDaJ08sLWosb1jVHSAG48sb4dvZuOPvV\n\tDAoA==", "X-Gm-Message-State": "APjAAAVn+5UNQmOo0DZGFAONhDu8LvHHy4QGt1izb4YvRJQ+Eq+NVjz3\n\tl/b0SR+mzFxgthwbFZvnexY3zw==", "X-Google-Smtp-Source": "APXvYqw8ntNr9Y7KtuD0WwqwQ/l6wehUmvqisdSJSXgT0uYQXoY9XMkvlc3TmtbKf6RhjcbTykfXxg==", "X-Received": "by 2002:a19:f107:: with SMTP id p7mr6501640lfh.91.1573218092860; \n\tFri, 08 Nov 2019 05:01:32 -0800 (PST)", "From": "Rasmus Villemoes <linux@rasmusvillemoes.dk>", "To": "Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,\n\tChristophe Leroy <christophe.leroy@c-s.fr>", "Subject": "[PATCH v4 04/47] soc: fsl: qe: introduce qe_io{read,\n\twrite}* wrappers", "Date": "Fri, 8 Nov 2019 14:00:40 +0100", "Message-Id": "<20191108130123.6839-5-linux@rasmusvillemoes.dk>", "X-Mailer": "git-send-email 2.23.0", "In-Reply-To": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "References": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Scott Wood <oss@buserror.net>,\n\tRasmus Villemoes <linux@rasmusvillemoes.dk>, \n\tlinuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "The QUICC engine drivers use the powerpc-specific out_be32() etc. In\norder to allow those drivers to build for other architectures, those\nmust be replaced by iowrite32be(). However, on powerpc, out_be32() is\na simple inline function while iowrite32be() is out-of-line. So in\norder not to introduce a performance regression on powerpc when making\nthe drivers work on other architectures, introduce qe_io* helpers.\n\nAlso define the qe_{clr,set,clrset}bits* helpers in terms of these new\nmacros.\n\nSigned-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>\n---\n include/soc/fsl/qe/qe.h | 34 +++++++++++++++++++++++++---------\n 1 file changed, 25 insertions(+), 9 deletions(-)", "diff": "diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h\nindex a1aa4eb28f0c..9cac04c692fd 100644\n--- a/include/soc/fsl/qe/qe.h\n+++ b/include/soc/fsl/qe/qe.h\n@@ -241,21 +241,37 @@ static inline int qe_alive_during_sleep(void)\n #define qe_muram_offset cpm_muram_offset\n #define qe_muram_dma cpm_muram_dma\n \n-#define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))\n-#define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))\n+#ifdef CONFIG_PPC32\n+#define qe_iowrite8(val, addr) out_8(addr, val)\n+#define qe_iowrite16be(val, addr) out_be16(addr, val)\n+#define qe_iowrite32be(val, addr) out_be32(addr, val)\n+#define qe_ioread8(addr) in_8(addr)\n+#define qe_ioread16be(addr) in_be16(addr)\n+#define qe_ioread32be(addr) in_be32(addr)\n+#else\n+#define qe_iowrite8(val, addr) iowrite8(val, addr)\n+#define qe_iowrite16be(val, addr) iowrite16be(val, addr)\n+#define qe_iowrite32be(val, addr) iowrite32be(val, addr)\n+#define qe_ioread8(addr) ioread8(addr)\n+#define qe_ioread16be(addr) ioread16be(addr)\n+#define qe_ioread32be(addr) ioread32be(addr)\n+#endif\n+\n+#define qe_setbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) | (_v), (_addr))\n+#define qe_clrbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) & ~(_v), (_addr))\n \n-#define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))\n-#define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))\n+#define qe_setbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) | (_v), (_addr))\n+#define qe_clrbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) & ~(_v), (_addr))\n \n-#define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))\n-#define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))\n+#define qe_setbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) | (_v), (_addr))\n+#define qe_clrbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) & ~(_v), (_addr))\n \n #define qe_clrsetbits_be32(addr, clear, set) \\\n-\tiowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))\n+\tqe_iowrite32be((qe_ioread32be(addr) & ~(clear)) | (set), (addr))\n #define qe_clrsetbits_be16(addr, clear, set) \\\n-\tiowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))\n+\tqe_iowrite16be((qe_ioread16be(addr) & ~(clear)) | (set), (addr))\n #define qe_clrsetbits_8(addr, clear, set) \\\n-\tiowrite8((ioread8(addr) & ~(clear)) | (set), (addr))\n+\tqe_iowrite8((qe_ioread8(addr) & ~(clear)) | (set), (addr))\n \n /* Structure that defines QE firmware binary files.\n *\n", "prefixes": [ "v4", "04/47" ] }